Littérature scientifique sur le sujet « Hardware Model Checking »
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Articles de revues sur le sujet "Hardware Model Checking"
Pixley, Carl, et Vigyan Singhal. « Model checking : a hardware design perspective ». International Journal on Software Tools for Technology Transfer (STTT) 2, no 3 (1 novembre 1999) : 288–306. http://dx.doi.org/10.1007/s100090050036.
Texte intégralGong, Wei, et Jun Wei Jia. « Comparison of Model Checking Tools ». Advanced Materials Research 659 (janvier 2013) : 181–85. http://dx.doi.org/10.4028/www.scientific.net/amr.659.181.
Texte intégralVasudevan, Shobha, E. Allen Emerson et Jacob A. Abraham. « Efficient Model Checking of Hardware Using Conditioned Slicing ». Electronic Notes in Theoretical Computer Science 128, no 6 (mai 2005) : 279–94. http://dx.doi.org/10.1016/j.entcs.2005.04.017.
Texte intégralMoiseenko, Evgenii, Michalis Kokologiannakis et Viktor Vafeiadis. « Model checking for a multi-execution memory model ». Proceedings of the ACM on Programming Languages 6, OOPSLA2 (31 octobre 2022) : 758–85. http://dx.doi.org/10.1145/3563315.
Texte intégralLi, Dejian, Qizhi Zhang, Dongyan Zhao, Lei Li, Jiaji He, Yidong Yuan et Yiqiang Zhao. « Hardware Trojan Detection Using Effective Property-Checking Method ». Electronics 11, no 17 (24 août 2022) : 2649. http://dx.doi.org/10.3390/electronics11172649.
Texte intégralMcMillan, K. L. « A methodology for hardware verification using compositional model checking ». Science of Computer Programming 37, no 1-3 (mai 2000) : 279–309. http://dx.doi.org/10.1016/s0167-6423(99)00030-1.
Texte intégralBjesse, Per. « Word level bitwidth reduction for unbounded hardware model checking ». Formal Methods in System Design 35, no 1 (7 juillet 2009) : 56–72. http://dx.doi.org/10.1007/s10703-009-0080-2.
Texte intégralZhang, Jie, Jian Qi et Yong Guan. « Research on Hardware Design Verification Methods ». Advanced Materials Research 588-589 (novembre 2012) : 1208–13. http://dx.doi.org/10.4028/www.scientific.net/amr.588-589.1208.
Texte intégralCooke, John. « Symbolic Model Checking ». Microprocessors and Microsystems 18, no 5 (juin 1994) : 297. http://dx.doi.org/10.1016/0141-9331(94)90007-8.
Texte intégralBen-David, Shoham, Cindy Eisner, Daniel Geist et Yaron Wolfsthal. « Model Checking at IBM ». Formal Methods in System Design 22, no 2 (mars 2003) : 101–8. http://dx.doi.org/10.1023/a:1022905120346.
Texte intégralThèses sur le sujet "Hardware Model Checking"
Ford, Gregory Fick. « Hardware Emulation of Sequential ATPG-Based Bounded Model Checking ». Case Western Reserve University School of Graduate Studies / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=case1384265165.
Texte intégralRaju, Akhilesh. « Trojan Detection in Hardware Designs ». University of Cincinnati / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1504781162418081.
Texte intégralVENDRAMINETTO, DANILO. « Advanced Techniques for Bit-Level Model Checking ». Doctoral thesis, Politecnico di Torino, 2016. http://hdl.handle.net/11583/2643478.
Texte intégralMarques, Luis Gustavo Perpetuo Costa. « Metodologia de desenvolvimento de VHDL sintetizável com uso de model checking ». reponame:Repositório Institucional da UFSC, 2016. https://repositorio.ufsc.br/xmlui/handle/123456789/168246.
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Essa dissertação foi elaborada em uma companhia que desenvolve equipamentos para proteção e automação de subestações, sendo que a maior parte deles possui um FPGA programado em VHDL como unidade principal de processamento. O código VHDL sintetizável e validado através de simulação e testes em equipamento, método bastante comum mas que não e suficiente para garantir a satisfação de propriedades tanto gerais quanto orientadas a aplicação, devido ao fato de não ser exaustivo. Na direção de aumentar a confiabilidade do circuito projetado para o FPGA, o objetivo principal da dissertação e apresentar uma metodologia de desenvolvimento de codigo VHDL sintetizável que aprimore as atuais técnicas utilizadas, ao incorporar métodos formais para verificação de propriedades, sendo que o método formal utilizado e o model checking. A metodologia e construída de um modo que o uso do model checking seja transparente ao desenvolvedor VHDL, mantendo a interface com o processo de verificação formal em linguagem de usuário,evitando a necessidade de aprendizado de novas linguagens. Para atingir esse objetivo específico, e proposto que as propriedades sejam representadas através de padrões orientados a VHDL que são baseados na biblioteca OVL. Alem disso, os contraexemplos gerados no processo de model checking retornam como test bench VHDL, permitindo ao usuário identificar o comportamento indesejado através de simulação. O ambiente de verificação adotado utiliza modelos em linguagem intermediaria FIACRE como front-end e por isso são propostas regras de tradução VHDL-FIACRE para que a transformação possa ocorrer no contexto de engenharia dirigida a modelos e assim evitar erros no processo de tradução. O uso da linguagem intermediaria e vantajoso, pois permite a utilização das ferramentas de verificação, as quais são de código aberto,sem que seja necessária a tradução direta do VHDL para os formalismos matemáticos em que essas ferramentas se baseiam. A metodologia e validada com a aplicação em quatro exemplos de código VHDL, sendo dois deles utilizados em projetos desenvolvidos na empresa: uma função de proteção e um controlador de acesso a um barramento de transferência de dados. Os resultados da aplicação indicam que a proposta e viável,pois foi possível fazer a verificação dos exemplos, sendo que em um deles foi identificado um erro que havia passado despercebido por simulação, sinalizando que a proposta contribui no aumento da confiabilidade do código desenvolvido.
Abstract: This dissertation was elaborated in a company that develops equipment for substation protection and automation, most of them having an FPGA programmed in VHDL as the main processing unit. The synthesizable VHDL code is validated through simulation and tests on equipment, a fairly common method that is not enough to ensure the satisfaction of both general and application-oriented properties, due tothe fact of being non exhaustive. In the direction of increasing the reliability of the designed FPGA circuit, the main objective of thiswork is to present a synthesizable VHDL code development methodology that enhances the current techniques by incorporating formal methods for verication of properties, with model checking being theselected method. The methodology is constructed in such a way thatthe use of model checking procedure should be transparent to VHDL designers, keeping the interface with the formal verication process inuser language, avoiding the need to learn new languages. To achievethis specic objective, it is proposed that the properties are represented by VHDL oriented patterns based on OVL library. In addition, the counter examples generated in the model checking process for properties that failed, return as VHDL test bench, allowing the user to identify theundesired behavior through simulation. The verication environment used in the methodology requires models described with the intermediatelanguage FIACRE as front-end and so VHDL-FIACRE translation rules are proposed to allow the transformation to occur in the context of model driven engineering, and thus prevent errors in the translation process. The use of an intermediate language is advantageous because it allows the use of the verication tools, which are open source, withoutthe need of translating VHDL directly to the mathematical formalismin which these tools are based. The methodology is validated by the application in four examples of VHDL code, two of them are used in designs developed by the company: a protection function and a controller to access a data transfer bus. The application results indicate that the proposal is viable because it was possible to verify the examples,and for one of them was identied an error that had passed unnoticed by simulation, showing that the proposal contributes to increase the reliability of the created code.
Dharmadhikari, Pranav Hemant. « Hardware Trojan Detection in Sequential Logic Designs ». University of Cincinnati / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1543919236213844.
Texte intégralBingham, Brad. « Leveraging distributed explicit-state model checking for practical verification of liveness in hardware protocols ». Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/52670.
Texte intégralScience, Faculty of
Computer Science, Department of
Graduate
Ou, Jen-Chieh. « HARDWARE DESCRIPTION LANGUAGE PROGRAM SLICING AND WAY TO REDUCE BOUNDED MODEL CHECKING SEARCH OVERHEAD ». Case Western Reserve University School of Graduate Studies / OhioLINK, 2007. http://rave.ohiolink.edu/etdc/view?acc_num=case1159738055.
Texte intégralAdams, Sara Elisabeth. « Abstraction discovery and refinement for model checking by symbolic trajectory evaluation ». Thesis, University of Oxford, 2014. http://ora.ox.ac.uk/objects/uuid:27276f9c-eba5-42a9-985d-1812097773f8.
Texte intégralJafri, Nisrine. « Formal fault injection vulnerability detection in binaries : a software process and hardware validation ». Thesis, Rennes 1, 2019. http://www.theses.fr/2019REN1S014/document.
Texte intégralFault injection is a well known method to test the robustness and security vulnerabilities of systems. Detecting fault injection vulnerabilities has been approached with a variety of different but limited methods. Software-based and hardware-based approaches have both been used to detect fault injection vulnerabilities. Software-based approaches can provide broad and rapid coverage, but may not correlate with genuine hardware vulnerabilities. Hardware-based approaches are indisputable in their results, but rely upon expensive expert knowledge, manual testing, and can not confirm what fault model represent the created effect. First, this thesis focuses on the software-based approach and proposes a general process that uses model checking to detect fault injection vulnerabilities in binaries. The efficacy and scalability of this process is demonstrated by detecting vulnerabilities in different cryptographic real-world implementations. Then, this thesis bridges software-based and hardware-based fault injection vulnerability detection by contrasting results of the two approaches. This demonstrates that: not all software-based vulnerabilities can be reproduced in hardware; prior conjectures on the fault model for electromagnetic pulse attacks may not be accurate; and that there is a relationship between software-based and hardware-based approaches. Further, combining both software-based and hardware-based approaches can yield a vastly more accurate and efficient approach to detect genuine fault injection vulnerabilities
PASINI, PAOLO. « Improving bit-level model checking algorithms for scalability through circuit-based reasoning ». Doctoral thesis, Politecnico di Torino, 2017. http://hdl.handle.net/11583/2680998.
Texte intégralLivres sur le sujet "Hardware Model Checking"
Hana, Chockler, et Hu, Alan J. (Alan John), dir. Hardware and software : Verification and testing : 4th International Haifa Verification Conference, HVC 2008, Haifa, Israel, October 27-30, 2008 : proceedings. Berlin : Springer, 2009.
Trouver le texte intégralNamjoshi, Kedar S. Hardware and Software : Verification and Testing : 5th International Haifa Verification Conference, HVC 2009, Haifa, Israel, October 19-22, 2009, Revised Selected Papers. Berlin, Heidelberg : Springer Berlin Heidelberg, 2011.
Trouver le texte intégralDominique, Borrione, Paul Wolfgang J. 1951- et IFIP WG 10 5, dir. Correct hardware design and verification methods : 13th IFIP WG 10.5 advanced research working conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005 ; proceedings. Berlin : Springer, 2005.
Trouver le texte intégralChapitres de livres sur le sujet "Hardware Model Checking"
Eisner, Cindy, et Dana Fisman. « Functional Specification of Hardware via Temporal Logic ». Dans Handbook of Model Checking, 795–829. Cham : Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-10575-8_24.
Texte intégralRoman, Carlos M., Gary De Palma et Robert Kurshan. « Model Checking without Hardware Drivers ». Dans Advances in Hardware Design and Verification, 127. Boston, MA : Springer US, 1997. http://dx.doi.org/10.1007/978-0-387-35190-2_8.
Texte intégralYu, Zhengqi, Armin Biere et Keijo Heljanko. « Certifying Hardware Model Checking Results ». Dans Formal Methods and Software Engineering, 498–502. Cham : Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-32409-4_32.
Texte intégralVardi, Moshe Y. « Automata-Theoretic Model Checking Revisited ». Dans Hardware and Software : Verification and Testing, 2. Berlin, Heidelberg : Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-01702-5_2.
Texte intégralHenzinger, Thomas A. « Model Checking : From Hardware to Software ». Dans Programming Languages and Systems, 176–77. Berlin, Heidelberg : Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-40018-9_12.
Texte intégralLeucker, Martin. « On Model Checking Synchronised Hardware Circuits ». Dans Advances in Computing Science — ASIAN 2000, 182–98. Berlin, Heidelberg : Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-44464-5_14.
Texte intégralBeyer, Dirk, et Thomas Lemberger. « Software Verification : Testing vs. Model Checking ». Dans Hardware and Software : Verification and Testing, 99–114. Cham : Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-70389-3_7.
Texte intégralYu, Emily, Armin Biere et Keijo Heljanko. « Progress in Certifying Hardware Model Checking Results ». Dans Computer Aided Verification, 363–86. Cham : Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-81688-9_17.
Texte intégralBloemen, Vincent, et Jaco van de Pol. « Multi-core SCC-Based LTL Model Checking ». Dans Hardware and Software : Verification and Testing, 18–33. Cham : Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-49052-6_2.
Texte intégralAndrés, Miguel E., Pedro D’Argenio et Peter van Rossum. « Significant Diagnostic Counterexamples in Probabilistic Model Checking ». Dans Hardware and Software : Verification and Testing, 129–48. Berlin, Heidelberg : Springer Berlin Heidelberg, 2009. http://dx.doi.org/10.1007/978-3-642-01702-5_15.
Texte intégralActes de conférences sur le sujet "Hardware Model Checking"
Biere, Armin, Tom van Dijk et Keijo Heljanko. « Hardware model checking competition 2017 ». Dans 2017 Formal Methods in Computer Aided Design (FMCAD). IEEE, 2017. http://dx.doi.org/10.23919/fmcad.2017.8102233.
Texte intégralSingh, Gaurav, et Sandeep K. Shukla. « Model Checking Bluespec Specified Hardware Designs ». Dans 2007 IEEE International Workshop on Microprocessor Test and Verification (MTV). IEEE, 2007. http://dx.doi.org/10.1109/mtv.2007.9.
Texte intégralBormann, Jörg, Jörg Lohse, Michael Payer et Gerd Venzl. « Model checking in industrial hardware design ». Dans the 32nd ACM/IEEE conference. New York, New York, USA : ACM Press, 1995. http://dx.doi.org/10.1145/217474.217545.
Texte intégralJorg Bormann. « Model Checking in Industrial Hardware Design ». Dans 32nd Design Automation Conference. ACM, 1995. http://dx.doi.org/10.1109/dac.1995.249963.
Texte intégralCruz, Jonathan, Farimah Farahmandi, Alif Ahmed et Prabhat Mishra. « Hardware Trojan Detection Using ATPG and Model Checking ». Dans 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID). IEEE, 2018. http://dx.doi.org/10.1109/vlsid.2018.43.
Texte intégralKumar, Binod, Akshay Kumar Jaiswal, V. S. Vineesh et Rushikesh Shinde. « Analyzing Hardware Security Properties of Processors through Model Checking ». Dans 2020 33rd International Conference on VLSI Design and 2020 19th International Conference on Embedded Systems (VLSID). IEEE, 2020. http://dx.doi.org/10.1109/vlsid49098.2020.00036.
Texte intégralBerryhill, Ryan, et Andreas Veneris. « Chasing Minimal Inductive Validity Cores in Hardware Model Checking ». Dans 2019 Formal Methods in Computer Aided Design (FMCAD). IEEE, 2019. http://dx.doi.org/10.23919/fmcad.2019.8894268.
Texte intégralSeufert, Tobias, et Christoph Scholl. « Combining PDR and reverse PDR for hardware model checking ». Dans 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2018. http://dx.doi.org/10.23919/date.2018.8341978.
Texte intégralBradfield, Chris, et Cynthia Sturton. « Model checking to find vulnerabilities in an instruction set architecture ». Dans 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). IEEE, 2016. http://dx.doi.org/10.1109/hst.2016.7495566.
Texte intégralIwasaki, Naoki, et Katsumi Wasaki. « A Meta Hardware Description Language Melasy for Model-Checking Systems ». Dans 2008 Fifth International Conference on Information Technology : New Generations (ITNG). IEEE, 2008. http://dx.doi.org/10.1109/itng.2008.135.
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