Littérature scientifique sur le sujet « Hardware field simulator »
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Articles de revues sur le sujet "Hardware field simulator"
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Ihrens, Jana, Stefan Möws, Lennard Wilkening, Thorsten A. Kern et Christian Becker. « The Impact of Time Delays for Power Hardware-in-the-Loop Investigations ». Energies 14, no 11 (28 mai 2021) : 3154. http://dx.doi.org/10.3390/en14113154.
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Power hardware-in-the-loop (PHiL) simulations provide a powerful environment in the critical process of testing new components and controllers. In this work, we aim to explain the impact of time delays in a PHiL setup and recommend how to consider them in different investigations. The general concept of PHiL, with its necessary components, is explained and the benefits compared to pure simulation and implemented field tests are presented. An example for a flexible PHiL environment is shown in form of the Power Hardware-in-the-Loop Simulation Laboratory (PHiLsLab) at TU Hamburg. In the PHiLsLab, different hardware components are used as the simulator to provide a grid interface via an amplifier system, a real-time simulator by OPAL-RT, a programmable logic controller by Bachmann, and an M-DUINO microcontroller. Benefits and limitations of the different simulators are shown using case examples of conducted investigations. Essentially, all platforms prove to be appropriate and sufficiently powerful simulators, if the time constants and complexity of the investigated case fit the simulator performance. The communication interfaces used between simulator and amplifier system differ in communication speed and delay; therefore, they have to be considered to determine the level of dynamic interactions between the simulated rest of system and the hardware under test.
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Kozlova, A., Z. Li, J. R. Natvig, S. Watanabe, Y. Zhou, K. Bratvedt et S. H. Lee. « A Real-Field Multiscale Black-Oil Reservoir Simulator ». SPE Journal 21, no 06 (25 octobre 2016) : 2049–61. http://dx.doi.org/10.2118/173226-pa.
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Summary Simulation technology is constantly evolving to take advantage of the best-available computational algorithms and computing hardware. A new technology is being jointly developed by an integrated energy company and a service company to provide a step change to reservoir-simulator performance. Multiscale methods have been rapidly developed during the past few years. Multiscale technology promises to improve simulation run time by an order of magnitude compared with current simulator performance in traditional reservoir-engineering work flows. Following that trend, the two companies have been working in collaboration on a multiscale algorithm that significantly increases performance of reservoir simulators. In this paper, we report the development of multiscale black-oil reservoir-simulation technology in a reservoir simulator used by the industry, as well as the performance and accuracy of the results obtained by use of this implementation. The multiscale method has proved to be accurate and reliable for large real-data models, and the new solver is capable of solving very-large models an order of magnitude faster than the current commercial version of the solver.
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Queiroz, Janailson, Sarah Carvalho, Camila Barros, Luciano Barros et Daniel Barbosa. « Embedding an Electrical System Real-Time Simulator with Floating-Point Arithmetic in a Field Programmable Gate Array ». Energies 14, no 24 (13 décembre 2021) : 8404. http://dx.doi.org/10.3390/en14248404.
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Real-Time Digital Simulation (RTDS) is a powerful tool in modeling and analyzing electrical and drive systems because it provides an efficient and accurate process. There are several hardware devices for this type of simulation; however, their high costs have led to the increasing use of more affordable and reconfigurable technologies. In this context, many logic blocks and storage elements make the Field Programmable Gate Array (FPGA) an ideal device to perform RTDS. This work proposes a technique to embed a real-time digital simulator in an FPGA through Hardware Description Language (HDL) since it provides liberty in the architecture choice and no dependency on commercial ready-made hardware–software packages. The approach proposed focuses on system design developing with expression tree graph, synthesizing and verifying, prioritizing the performance and design accuracy concerning area and power consumption. Thus, the result acquisition occurs at a time step considered in real-time. A simulation of a direct current (DC) motor speed control has been incorporated into this work as an example of application, which includes the embedding and simulation of the electric machine and its drive system. Performance tests have shown that the developed simulator is real-time and makes possible realistic analysis of the interaction between the plant and its control. In addition, an idea of the hardware requirement for real-time simulation is proposed based on the number of mathematical operations.
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Nayak, B. Sathish, Sidharth Bhonge, K. Krishna Naik, Odelu Ojjela et Surendra Pal. « Multi GNSS IRNSS L5 IRNSS S1 and GPS L1 Hybrid Simulator A Reconfigurable Low cost Solution for Research and Defence Applications ». Defence Science Journal 72, no 4 (26 août 2022) : 581–91. http://dx.doi.org/10.14429/dsj.72.17873.
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Satellite-based positioning field of research is growing rapidly as there is an increase in demand for precise position requirements in various civil and commercial applications. There are many errors that affect the GNSS signals while propagation from satellite to receiver, which eventually induces errors in pseudo-range measurements. In order to assess the receiver characteristics for a specific error condition, the real-time signals may not be appropriate, and it is challenging to perform repeated experiments with the same error condition. The advantage of the GNSS simulator is that users can model the different scenarios for any given location on the globe, which are repeatable at any point of time. The conventional hardware simulators are expensive and have few limitations. In this paper, a reconfigurable hybrid simulator is proposed with some advantages over traditional hardware simulators, such as low cost, reconfigurability, and controllability over fundamental parameters. It can be able to record intermediate stage data, which makes it more suitable for the GNSS research field. The proposed multi-GNSS simulator considered implementing IRNSS-L5, IRNSS-S1, and GPS-L1 band signals. A general-purpose computer can perform the necessary calculations for signal generation. The hybrid simulator can be able to generate the digital I/Q data, which can be stored as I/Q data or can be connected to a general-purpose SDR (Software Defined Radio) for RF signal generation (bladeRF in this case). The I/Q data can be used with the software receiver to analyse the receiver performance concerning the specific error. The generated GNSS signals are validated with software and hardware receivers, and the obtained position is observed as expected.
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Vela-Garcia, L., J. Vázquez Castillo, R. Parra-Michel et Matthias Pätzold. « An Accurate Hardware Sum-of-Cisoids Fading Channel Simulator for Isotropic and Non-Isotropic Mobile Radio Environments ». Modelling and Simulation in Engineering 2012 (2012) : 1–12. http://dx.doi.org/10.1155/2012/542198.
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The rapid technological development in the field of wireless communications calls for devices capable of reproducing and simulating the behavior of the channel under realistic propagation conditions. This paper presents a hardware fading channel simulator that is able to generate stochastic processes characterized by symmetrical and asymmetrical Doppler power spectral densities (PSDs) depending on the assumption of isotropic or non-isotropic scattering. The concept of the proposed hardware simulator is based on an implementation of the sum-of-cisoids (SOC) method. The hardware simulator is capable of handling any configuration of the cisoid's amplitudes, frequencies, and phases. Each of the cisoids that constitutes the SOC model is implemented using a piecewise polynomial approximation technique. The investigation of the higher-order statistics of the generated fading processes, like the level-crossing rate (LCR) and the average duration of fades (ADF), shows that our design is able to reproduce accurately the key features of realistic channel models that are considered as candidates for the latest wireless communication standards.
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Casolino, Giovanni, Mario Russo, Pietro Varilone et Daniele Pescosolido. « Hardware-in-the-Loop Validation of Energy Management Systems for Microgrids : A Short Overview and a Case Study ». Energies 11, no 11 (1 novembre 2018) : 2978. http://dx.doi.org/10.3390/en11112978.
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The energy management system (EMS) of a microgrid often presents a complex structure and a large number of control functions, which must be validated to ensure a reliable and optimal operation of the microgrid. Control system validation is typically performed by using hardware-in-the-loop (HIL) architectures in which the microgrid is simulated in real time and interfaced with the actual system under test. The simulation must ensure both an accurate representation of the microgrid and a reliable replica of the field communication of the EMS with all the control devices. In this paper, an overview of the various HIL architectures proposed in the literature is firstly outlined. Then, an HIL validation facility is presented and used to validate the EMS of an industrial microgrid. Finally, some results of the validation tests are reported to give evidence of the effectiveness of the proposed facility. In the proposed architecture, the soft real-time digital simulator of the microgrid is interfaced with the actual EMS using the same communication system and protocol as on the field. The main advantages of the proposed testing facility are: (i) the use of commercial PCs and the absence of dedicated interface modules, resulting in inexpensive hardware components; (ii) the capability to validate both control and communication functions of the EMS; (iii) the applicability to microgrids of different types (industrial, commercial, residential), as well as of various dimensions, including large microgrids; (iv) the easiness in changing the microgrid and the EMS under validation by only software modifications of the simulator tasks and of the exchange interface. As drawbacks, the proposed testing facility presents the need to adapt the software interface between EMS and the field to the EMS under test and the possibility of testing only the EMS functions and not fast-acting local controllers of the microgrid such as the protection systems.
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Sriram, Vinay, et David Kearney. « Towards A Multi-FPGA Infrared Simulator ». Journal of Defense Modeling and Simulation : Applications, Methodology, Technology 4, no 4 (octobre 2007) : 343–55. http://dx.doi.org/10.1177/154851290700400404.
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High speed infrared (IR) scene simulation is used extensively in defense and homeland security to test sensitivity of IR cameras and accuracy of IR threat detection and tracking algorithms used commonly in IR missile approach warning systems (MAWS). A typical MAWS requires an input scene rate of over 100 scenes/second. Infrared scene simulations typically take 32 minutes to simulate a single IR scene that accounts for effects of atmospheric turbulence, refraction, optical blurring and charge-coupled device (CCD) camera electronic noise on a Pentium 4 (2.8GHz) dual core processor [7]. Thus, in IR scene simulation, the processing power of modern computers is a limiting factor. In this paper we report our research to accelerate IR scene simulation using high performance reconfigurable computing. We constructed a multi Field Programmable Gate Array (FPGA) hardware acceleration platform and accelerated a key computationally intensive IR algorithm over the hardware acceleration platform. We were successful in reducing the computation time of IR scene simulation by over 36%. This research acts as a unique case study for accelerating large scale defense simulations using a high performance multi-FPGA reconfigurable computer.
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Jin, Shuo, Hao Yu, Xiaopeng Fu, Zhiying Wang, Kai Yuan et Peng Li. « A Universal Design of FPGA-Based Real-Time Simulator for Active Distribution Networks Based on Reconfigurable Computing ». Energies 12, no 11 (31 mai 2019) : 2086. http://dx.doi.org/10.3390/en12112086.
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Reconfigurable computing is that the logical resources in the system can be reconfigured according to the real-time changing data flow to achieve different calculation functions. The reconfigurable computing system has both high efficiency on hardware and universality of software. The field programmable gate array (FPGA)-based real-time simulator for active distribution networks (ADNs) requires a long compilation time for case modification, with low efficiency and low versatility, making it inconvenient and difficult for users. To solve the problem of long compile time with a new case, a universal design of the FPGA-based real-time simulator for ADNs based on reconfigurable computing is proposed in this paper. It includes the universal design of the simulation parameter configuration, the simulation initial value setting, the linear equations solving module and the simulation result output module. The proposed universal design of the simulator makes the modification and change of the cases and parameters without recompiling and further improves the simulation efficiency. Simulation results are conducted and compared with PSCAD/EMTDC to validate the correctness and effectiveness of the universal design.
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Chung, Yi, et Yee-Pien Yang. « Hardware-in-the-Loop Simulation of Self-Driving Electric Vehicles by Dynamic Path Planning and Model Predictive Control ». Electronics 10, no 19 (8 octobre 2021) : 2447. http://dx.doi.org/10.3390/electronics10192447.
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This paper applies a dynamic path planning and model predictive control (MPC) to simulate self-driving and parking for an electric van on a hardware-in-the-loop (HiL) platform. The hardware platform is a simulator which consists of an electric power steering system, accelerator and brake pedals, and an Nvidia drive PX2 with a robot operating system (ROS). The vehicle dynamics model, sensors, controller, and test field map are virtually built with the PreScan simulation platform. Both manual and autonomous driving modes can be simulated, and a graphic user interface allows a test driver to select a target parking space on a display screen. Three scenarios are demonstrated: forward parking, reverse parking, and obstacle avoidance. When the vehicle perceives an obstacle, the map is updated and the route is adaptively planned. The effectiveness of the proposed MPC is verified in experiments and proved to be superior to a traditional proportional–integral–derivative controller with regards to safety, energy-saving, comfort, and agility.
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Muñoz-Quijada, Maria, Luis Sanz et Hipolito Guzman-Miranda. « A Virtual Device for Simulation-Based Fault Injection ». Electronics 9, no 12 (24 novembre 2020) : 1989. http://dx.doi.org/10.3390/electronics9121989.
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This paper describes the design and implementation of a virtual device to perform simulation-based fault injection campaigns. The virtual device is fully compatible with the same user software that is already being used to perform fault injection campaigns in existing FPGA (Field Programmable Gate Array)-based hardware devices. Multiple instances of the virtual device can be launched in parallel in order to speed-up the fault injection campaigns, without any preexisting limitations on number, such as available license seats, since the virtual device can be compiled with the open-source simulator GHDL. This virtual device also allows one to find bugs in both software and firmware, and to reproduce in simulation, with total visibility of the internal states, corner cases that may have occurred in the real hardware.
Thèses sur le sujet "Hardware field simulator"
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Massi, Pavan Alessandro. « A hardware field simulator for photovoltaic materials applications ». Doctoral thesis, Università degli studi di Trieste, 2008. http://hdl.handle.net/10077/2757.
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2006/2007Il presente lavoro riguarda la descrizione di un simulatore di campo fotovoltaico (in seguito simulatore). Il simulatore è un convertitore elettronico di potenza che, alimentato dalla rete elettrica, riproduce la caratteristica tensione corrente di un campo fotovoltaico (insieme di moduli fotovoltaici connessi in serie e in parallelo) operante in condizioni climatiche di temperatura e irraggiamento arbitrarie. Il nuovo dispositivo verrà impiegato nell’ambito del laboratorio fotovoltaico cui fa riferimento l’impianto in via di realizzazione sul tetto dell’edificio che ospita il Dipartimento dei Materiali e delle Risorse Naturali dell’Università di Trieste. Il simulatore viene proposto come utile strumento per i progettisti di dispositivi solari funzionanti in sistemi fotovoltaici connessi in rete. In particolare, il simulatore permetterà di prevedere il funzionamento di nuovi moduli fotovoltaici operanti in condizioni di ombreggiamento arbitrario e inseriti in un sistema fotovoltaico reale. L’uso del simulatore sarà particolarmente efficace nel caso di simulazioni di tecnologie in film sottile come, ad esempio, il silicio amorfo, il tellururo di cadmio, ecc. Il simulatore sarà anche necessario per testare i componenti che fanno parte di un sistema fotovoltaico connesso in rete, con particolare riferimento ai sistemi di condizionamento della potenza (detti anche inverter). Tali sistemi, oltre a convertire la tensione continua prodotta dai moduli fotovoltaici in una tensione compatibile e sincronizzata con quella della rete, devono garantire istante per istante l’inseguimento del punto di massima potenza estraibile dal campo fotovoltaico cui sono connessi. Il lavoro è stato suddiviso in cinque capitoli. Il primo capitolo fornisce una breve descrizione dello stato dell’arte e di alcune aspetti economici relativi alla tecnologia fotovoltaica. Nel secondo capitolo vengono richiamati il modello classico di una cella solare e le definizioni riguardo le sue caratteristiche principali (punto di massima potenza, efficienza, fill factor, ecc.). Nello stesso capitolo un’overview sui materiali e sulle tecnologie utilizzate nella realizzazione dei dispositivi fotovoltaici divide, come suggerito da Martin Green, le celle solari in tre diverse generazioni: la prima comprende i dispositivi realizzati in silicio cristallino (mono e policrisallino), la seconda quelli in film sottile (in silicio amorfo, tellururo di cadmio CdTe, diseleniuro di rame e indio CIS, diseleniuro di rame, indio e gallio CIGS, diseleniuro di rame, indio, gallio e zolfo CIGSS) e le celle di Graetzel, e la terza le celle multigiunzione, a banda intermedia e quelle organiche. Nel capitolo tre viene fornita una descrizione dei componenti costituenti un sistema fotovoltaico connesso in rete e viene proposto un nuovo metodo per la determinazione delle caratteristiche corrente tensione e potenza tensione prodotte da dispositivi fotovoltaici. Il metodo risulta efficace in quanto non necessita di misure sperimentali da effetture sui diversi dispositivi. I dati forniti nei comuni data sheet che vengono forniti a corredo dei moduli fotovoltaici sono sufficienti a determinarne il comportamento al variare della temperatura di funzionamento e del livello di radiazione solare. L’efficienza di un sistema fotovoltaico (Balance Of the System, BOS) viene calcolata nel capitolo quattro. Particolare enfasi viene data all’effetto di mismatching che è tanto più importante quanto più è elevato il livello di ombreggiamento presente sul piano dei moduli fotovoltaici costituenti l’impianto. Infine, l’ultimo capitolo riguarda la descrizione del simulatore e delle sue applicazioni.
The subject of this work is a power electronic device, hereafter named photovoltaic field simulator, which converts the grid voltage into a current voltage characteristic. This characteristic replicates the behavior of a real photovoltaic field working in arbitrary conditions of irradiance and temperature. After building, the photovoltaic field simulator will be used in the photovoltaic laboratory which is connected to the experimental photovoltaic plant which will be installed on the roof top of the Materials and Natural Resources Department of Trieste University. The photovoltaic field simulator will be used for photovoltaic module parameters design with particular reference to its behavior when inserted in a photovoltaic field operating under shaded conditions. The use of the simulator will be particularly effective when simulating thin-film technologies as, for example, amorphous silicon, cadmium telluride, and etc. The photovoltaic field simulator will also be used for testing the components of grid connected photovoltaic systems with particular reference to the power conditioning units (also named inverters). These systems, which convert the direct current produced by the photovoltaic modules into a utility grade current (typically alternate and sinusoidal at a frequency of 50-60Hz), must extract maximum power from the photovoltaic field. The work is divided into five chapters. In the first a brief description of photovoltaic technology and its economic aspects is given. Chapter two is on classic solar cell modelling basics and on the definition of the parameters of photovoltaic technology (maximum power point, efficiency, fill factor, and etc.). In the same chapter a materials and technologies overview splits, as suggested by Martin Green, solar cells in three different generations: the first comprises crystalline silicon (mono and polycrystalline) devices, the second thin-film devices (amorphous silicon, cadmium telluride CdTe, copper indium diselenide CIS, copper indium gallium diselenide CIGS, copper indium gallium sulphur diselenide CIGSS), and the Graetzel cells, while the third multi-junction, intermediate band and organic photovoltaic devices. The third chapter briefly describes photovoltaic grid connected system components. In particular a new model for plotting photovoltaic current voltage and power voltage characteristics is provided. The method is original because only module data sheet parameters are used and experimental measurements are not needed in order to determine the photovoltaic modules behavior with reference to irradiance and working temperatures changes. In chapter four the Balance of a photovoltaic System (BOS) is calculated. In particular the importance of the mismatching effect of photovoltaic modules due to shaded conditions is shown. The last chapter is on simulator description and its applications.
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Sedaghat, Maman Reza. « Fault emulation reconfigurable hardware based fault simulation using logic emulation systems with optimized mapping / ». [S.l. : s.n.], 1999. http://deposit.ddb.de/cgi-bin/dokserv?idn=95853893X.
Texte intégral
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Mekala, Priyanka. « Field Programmable Gate Array Based Target Detection and Gesture Recognition ». FIU Digital Commons, 2012. http://digitalcommons.fiu.edu/etd/723.
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The move from Standard Definition (SD) to High Definition (HD) represents a six times increases in data, which needs to be processed. With expanding resolutions and evolving compression, there is a need for high performance with flexible architectures to allow for quick upgrade ability. The technology advances in image display resolutions, advanced compression techniques, and video intelligence. Software implementation of these systems can attain accuracy with tradeoffs among processing performance (to achieve specified frame rates, working on large image data sets), power and cost constraints. There is a need for new architectures to be in pace with the fast innovations in video and imaging. It contains dedicated hardware implementation of the pixel and frame rate processes on Field Programmable Gate Array (FPGA) to achieve the real-time performance.
The following outlines the contributions of the dissertation. (1) We develop a target detection system by applying a novel running average mean threshold (RAMT) approach to globalize the threshold required for background subtraction. This approach adapts the threshold automatically to different environments (indoor and outdoor) and different targets (humans and vehicles). For low power consumption and better performance, we design the complete system on FPGA. (2) We introduce a safe distance factor and develop an algorithm for occlusion occurrence detection during target tracking. A novel mean-threshold is calculated by motion-position analysis. (3) A new strategy for gesture recognition is developed using Combinational Neural Networks (CNN) based on a tree structure. Analysis of the method is done on American Sign Language (ASL) gestures. We introduce novel point of interests approach to reduce the feature vector size and gradient threshold approach for accurate classification. (4) We design a gesture recognition system using a hardware/ software co-simulation neural network for high speed and low memory storage requirements provided by the FPGA. We develop an innovative maximum distant algorithm which uses only 0.39% of the image as the feature vector to train and test the system design. Database set gestures involved in different applications may vary. Therefore, it is highly essential to keep the feature vector as low as possible while maintaining the same accuracy and performance
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Cemin, Paulo Roberto. « Plataforma de medição de consumo para comparação entre software e hardware em projetos energeticamente eficientes ». Universidade Tecnológica Federal do Paraná, 2015. http://repositorio.utfpr.edu.br/jspui/handle/1/1310.
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A popularização dos dispositivos móveis impulsionou a pesquisa e o desenvolvimento de soluções de baixo consumo. A evolução destas aplicações demanda ferramentas que permitam avaliar diferentes alternativas de implementação, fornecendo, aos desenvolvedores, informações valiosas para a criação de soluções energeticamente eficientes. Este trabalho desenvolveu uma nova plataforma de medição de consumo que permite comparar a eficiência energética de diferentes algoritmos implementados em software e em hardware. A plataforma é capaz de medir o consumo energético de um processo específico em execução em um processador de propósito geral com um sistema operacional padrão, além de comparar o resultado obtido com algoritmos equivalentes implementados em uma FPGA. Isto permite ao desenvolvedor dividir o processamento da aplicação entre software e hardware de forma a obter a solução mais energeticamente eficiente. Comparada com o estado da arte, a plataforma de medição criada possui três característica inovadoras: suporte a medição de consumo de software e hardware; medição de trechos de código específicos executados pelo processador; e suporte a alteração dinâmica do clock. Também é mostrado neste trabalho como a plataforma desenvolvida tem sido utilizada para analisar o consumo energético de algoritmos de detecção de intrusão de rede para ataques do tipo probing.The large number of mobile devices increased the interest in low-power designs. Tools that allow the evaluation of alternative implementations give the designer actionable information to create energy-efficient designs. This paper presents a new power measurement platform able to compare the energy consumption of different algorithms implemented in software and in hardware. The proposed platform is able to measure the energy consumption of a specific process running in a general-purpose CPU with a standard operating system, and to compare the results with equivalent algorithms running in an FPGA. This allows the designer to choose the most energy-efficient software vs. hardware partitioning for a given application. Compared with the current state-of-the-art, the presented platform has four distinguishing features: (i) support for both software and hardware power measurements, (ii) measurement of individual code sections in the CPU, (iii) support for dynamic clock frequencies, and (iv) improvement of measurement precision. We also demonstrate how the developed platform has been used to analyze the energy consumption of network intrusion detection algorithms aimed at detecting probing attacks.
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Palm, Johan. « High Performance FPGA-Based Computation and Simulation for MIMO Measurement and Control Systems ». Thesis, Mälardalen University, School of Innovation, Design and Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-7477.
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The Stressometer system is a measurement and control system used in cold rolling to improve the flatness of a metal strip. In order to achieve this goal the system employs a multiple input multiple output (MIMO) control system that has a considerable number of sensors and actuators. As a consequence the computational load on the Stressometer control system becomes very high if too advance functions are used. Simultaneously advances in rolling mill mechanical design makes it necessary to implement more complex functions in order for the Stressometer system to stay competitive. Most industrial players in this market considers improved computational power, for measurement, control and modeling applications, to be a key competitive factor. Accordingly there is a need to improve the computational power of the Stressometer system. Several different approaches towards this objective have been identified, e.g. exploiting hardware parallelism in modern general purpose and graphics processors.
Another approach is to implement different applications in FPGA-based hardware, either tailored to a specific problem or as a part of hardware/software co-design. Through the use of a hardware/software co-design approach the efficiency of the Stressometer system can be increased, lowering overall demand for processing power since the available resources can be exploited more fully. Hardware accelerated platforms can be used to increase the computational power of the Stressometer control system without the need for major changes in the existing hardware. Thus hardware upgrades can be as simple as connecting a cable to an accelerator platform while hardware/software co-design is used to find a suitable hardware/software partition, moving applications between software and hardware.
In order to determine whether this hardware/software co-design approach is realistic or not, the feasibility of implementing simulator, computational and control applications in FPGAbased hardware needs to be determined. This is accomplished by selecting two specific applications for a closer study, determining the feasibility of implementing a Stressometer measuring roll simulator and a parallel Cholesky algorithm in FPGA-based hardware.
Based on these studies this work has determined that the FPGA device technology is perfectly suitable for implementing both simulator and computational applications. The Stressometer measuring roll simulator was able to approximate the force and pulse signals of the Stressometer measuring roll at a relative modest resource consumption, only consuming 1747 slices and eight DSP slices. This while the parallel FPGA-based Cholesky component is able to provide performance in the range of GFLOP/s, exceeding the performance of the personal computer used for comparison in several simulations, although at a very high resource consumption. The result of this thesis, based on the two feasibility studies, indicates that it is possible to increase the processing power of the Stressometer control system using the FPGA device technology.
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Shirai, Alysson Hikaru. « Estudo e implementação de sistemas de localização em hardware de lógica programável para utilização em rede de sensores sem fio ». Universidade Tecnológica Federal do Paraná, 2013. http://repositorio.utfpr.edu.br/jspui/handle/1/511.
Texte intégralRésumé :
CAPESRedes de sensores sem fio (RSSF) têm sido tema central de diversos estudos na atualidade. Em certas aplicações, como, por exemplo, as que necessitam saber de onde os dados estão sendo enviados ou em casos em que o próprio nó sensor precisa saber sua posição para executar alguma ação, mecanismos de localização se tornam imprescindíveis. Porém, a execução deste tipo de algoritmo é custosa para os nós sensores. Concomitantemente, o advento das low power FPGAs têm viabilizado a aplicação de dispositivos programáveis em RSSFs e aplicações envolvendo reconfiguração dinâmica de FPGA em nós sensores têm aumentado o uso destes dispositivos nestas redes. Unindo-se estas demandas, o objetivo desta dissertação é estudar e implementar sistemas de localização em hardware de lógica programável, visando atender aplicações voltadas a RSSF. Utilizando-se no nó sensor um bloco de hardware dedicado para realizar os cálculos de posição minimiza a utilização de seu CPU, podendo este hardware, inclusive, ser apenas uma parte de um sistema maior implementado na FPGA. O processo de localização baseia-se na utilização das distâncias entre o nó de posição desconhecida e os nós de referência, determinadas através de medição de RSSI, e o uso de algoritmos específicos que calculam a posição desejada. As principais etapas foram: revisão da literatura, modelagem do comportamento das medições de RSSI, análise do desempenho dos algoritmos e projeto de hardware. Através das simulações realizadas pôde-se desenvolver metodologias e ferramentas para a geração otimizada do hardware de localização. O desenvolvimento deste trabalho possibilitou analisar a aplicabilidade do ponto flutuante e ponto fixo, definir a arquitetura adequada para o hardware e o dimensionamento adequado da quantidade de bits necessária nas implementações.
Wireless sensor networks (WSN) have been the central theme of many researches in actuality. In certain applications, like, for example, the ones that need to know from where the data is being sent or in cases which the sensor node need to know its own position to perform some action, location mechanism is indispensable. However, the execution of these algorithms is costly for the sensor nodes. Concomitantly, the advent of low power FPGAs made feasible the application of programmable devices in WSNs and applications involving dynamic reconfiguration of FPGA in sensor nodes increased the use of these devices in WSNs. Joining these demands, the goal of this master thesis is to study and implement locating systems in programmable logic hardware, aiming at meeting applications in WSN. Employing a dedicated hardware block in sensor node to compute the position minimizes its CPU usage, and this hardware can even be just a part of a larger system implemented in FPGA. The localization process is based on the use of distances, measured between the sensor node with unknown position and the reference nodes, determined from RSSI measurements, and the use of specific algorithms that calculate the desired position. The main steps were: review of the literature, modeling the behavior of the RSSI measurements, performance analysis of the algorithms and hardware design. Through the performed simulations it was possible to develop methodologies and tools to generate optimized locating hardware. The development of this work allowed to evaluate the feasibility of the floating point and fixed point, to set the appropriate architecture for the hardware and to find the proper dimension of the number of bits required in the implementations.
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Santos, Vitor Alexandre. « Caso de estudo de sistema de emulação em hardware para aplicação com controlador lógico programável ». Universidade Tecnológica Federal do Paraná, 2016. http://repositorio.utfpr.edu.br/jspui/handle/1/2720.
Texte intégralRésumé :
Este trabalho consiste em um caso de estudo de um emulador de planta industrial implementado em FPGA (Field Programmable Gate Array), a fim de simulação de sistemas em conjunto com um CLP (Controlador Lógico Programável). Com isso, fundamentado na indústria de manufatura, são confrontados resultados práticos de um protótipo de processo industrial com os resultados de um modelo aplicado em FPGA. Dessa maneira, tem-se como objetivo o auxílio em testes em níveis de validação de aplicação em desenvolvimento, aproximação de condições de chão de fábrica, otimização de controle de processo e treinamento em automação industrial baseada em CLP. Como proposta para os modelos, a pesquisa utiliza características de um sistema em malha fechada de controle de velocidade de esteira e a partir desse, um processo de sistema discreto, o qual utiliza como base um processo manufatureiro. Inicialmente a revisão bibliográfica apresenta trabalhos em torno de simulação de sistemas e emuladores baseados em hardware reconfigurável. Também são revisados temas relacionados à indústria de manufatura com a aplicação do CLP, assim como a técnica de modelagem GRAFCET. Em seguida, são apresentadas questões referentes à lógica reconfigurável em torno dos dispositivos FPGA. Na sequência da explanação do tema, é realizada a descrição dos protótipos utilizados, assim como os modelos desenvolvidos em FPGA para o emulador, e assim a realização das comparações dos dados. Com a apresentação dos resultados é possível a verificação da semelhança entre os dois sistemas, físico e modelado na FPGA. As pequenas diferenças detectadas nos resultados obtidos, em alguns pontos da simulação, são discutidas no final do trabalho.This work is a case study of an industrial plant emulator implemented in FPGA (Field Programmable Gate Array), to simulate systems together with a PLC (Programmable Logic Controller). Based in manufacturing industry, practical results of an industrial process prototype are confronted with the results of an applied model in FPGA. The objective is to assist in testing application validation levels in development, approximation of factory floor conditions, optimization of control process and training in industrial automation based on PLC. As a proposal for the models, the research use characteristics of a closed loop speed control system and from this, a discrete system process, which uses as a basis a manufacturing process. Initially the bibliographic review presents works around simulation of systems and emulators based on reconfigurable hardware. Also are reviewed topics related to the manufacturing industry with the application of PLC, beside the GRAFCET modeling technique. Next, questions will set out questions about reconfigurable logic around FPGA devices. Following the explanation of the theme, we describe the used prototypes and the developed models developed in FPGA for the emulator. Finally the obtained data are compared. With the presentation of the results is possible to verify the similarity between the two systems, physical and modeling in the FPGA. The small differences detected in the results obtained, in some points of the simulation, are discussed at the end of the work.
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Assef, Amauri Amorin. « Arquitetura de hardware multicanal reconfigurável com excitação multinível para desenvolvimento e testes de novos métodos de geração de imagens por ultrassom ». Universidade Tecnológica Federal do Paraná, 2013. http://repositorio.utfpr.edu.br/jspui/handle/1/889.
Texte intégralRésumé :
UTFPR; CNPq; CAPES; Fundação Araucária; Ministério da SaúdeOs sistemas de diagnóstico por imagem de ultrassom (US) figuram entre os mais sofisticados equipamentos de processamento de sinais na atualidade. Apesar da alta tecnologia envolvida, a maioria dos sistemas comerciais de imagem possui arquitetura típica “fechada”, não atendendo às exigências de flexibilidade e acesso aos dados de radiofrequência (RF) para desenvolvimento e teste de novas modalidades e técnicas do US. Este trabalho apresenta uma nova arquitetura modular de hardware (front-end), baseada em dispositivos FPGA (Field Programmable Gated Array), e software (back-end), baseada em PC ou DSP, totalmente programável, aberta e flexível, para pesquisa e investigação de técnicas inovadoras para geração de imagens médicas por US. A plataforma desenvolvida ULTRA-ORS (do inglês Ultrasound Open Research System) permite conexão com transdutores multielementos dos tipos lineares, convexos e phased array com frequência central entre 500 kHz e 20 MHz, e capacidade de expansão para operação com transdutores de até 1024 elementos multiplexados. O módulo eletrônico lógico para formação do feixe (beamformer transmitter) possibilita excitação simultaneamente, através de sinais PWM, de 128 canais com formas de ondas arbitrárias, abertura programável, e tensão de excitação de até 200 Vpp, permitindo controle individual de habilitação, amplitude de apodização com até 256 níveis, ângulo de fase e atraso temporal de disparo adequado para focalização na transmissão. O módulo de recepção (beamformer receiver) realiza a aquisição simultânea de 128 canais com taxa de amostragem programável até 50 MHz e resolução de 12 bits. Como item imprescindível deste trabalho, a plataforma proposta possibilita acesso e transferência dos dados de RF digitalizados para um computador através de interfaces seriais ou para kits de DSP para processamento das imagens. Como resultado do projeto de pesquisa, é apresentado um novo sistema digital de US que pode ser utilizado para avaliações das imagens geradas pela técnica beamforming, utilizando como referência a ferramenta de simulação Field II e comparações com as imagens geradas por equipamentos comerciais em phantom mimetizador de tecidos biológicos de US.
Medical ultrasound (US) scanners are amongst the most sophisticated signal processing machines in use today. Even with the recent advances in electronic technology, their typical architecture is often “closed” and does not fit the requirements of flexibility and RF data access to the development and test of new modalities and US techniques. This work presents the development of a novel modular hardware architecture (front-end), FPGA-based (Field Programmable Gated Array) and software (back-end), PC-based or DSP-based, fully programmable, open and flexible, for research and investigation of new techniques for medical US imaging. The proposed platform, ULTRA-ORS (Ultrasound Open Research System), allows connection to linear, convex and phased array transducers with center frequency between 500 kHz and 20 MHz, and expansion capability for operation with transducers up to 1024 multiplexed elements. The transmitter beamformer can excite simultaneously, using PWM signals, 128-channel with arbitrary waveform, programmable aperture, and 200 Vpp excitation voltage, allowing individual enable control, amplitude apodization up to 256 levels, phase angle and proper time delay for focusing on transmission. The receiver beamformer can handle simultaneous 128-channels acquisition with programmable sampling rate up to 50 MHz and 12-bit resolution. As essential item of this work, the platform enables access to the raw RF signals to be transferred to a computer through serial ports or DSP kits for imaging processing. As a result of the research project, we present a new digital US system that can be used for evaluation of images generated by the beamforming technique, using as reference the Field II simulation tool and comparisons with commercial equipment using US tissue-mimicking phantom.
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Oliveira, Alisson Antônio de. « Estudo e implementação de operações em ponto fixo em FPGA com VHDL 2008 : aplicação em controle de sistemas em tempo discreto ». Universidade Tecnológica Federal do Paraná, 2012. http://repositorio.utfpr.edu.br/jspui/handle/1/473.
Texte intégralRésumé :
Existem máquinas que necessitam de uma grande velocidade de processamento para seu correto trabalho, essas máquinas possuem um tempo de processamento de resposta crítico. Quando considera-se este aspecto somado à necessidade de um controle do comportamento estático e dinâmico de um sistema chega-se ao controlador com fortes demandas de tempo de execução. Essa dissertação compara controladores discretos implementados em ponto fixo, com diferentes precisões, usando para tanto a simulação do comportamento de controladores confeccionados em linguagem de comandos Matlab e em linguagem VHDL 2008.
Esta última está em desenvolvimento e padronização pelo IEEE. A linguagem VHDL é usada nas FPGAs que são dispositivos de alta velocidade e capacidade de processamento paralelo. O principal objetivo do trabalho é o estudo e a implementação de controladores discretos em FPGA com o auxílio da linguagem VHDL 2008, determinando suas virtudes e limitações, em particular quanto à estrutura de programação, análise de erro e a demanda por recursos. Os resultados alcançados demonstram que algumas melhorias ainda precisam ser feitas para que o VHDL 4.0, conhecido como VHDL 2008, seja entregue ao mercado como padrão estável. Entretanto, quando conhecidas suas limitações, já é possível seu uso em implementações com conversão de sinais discretos para analógicos, como é o caso de controle e simulação de sistemas dinâmicos como servomecanismos.There are machines that need large processing speed for its correct working, these machines have a critical time response processing. When it is considered that aspect coupled with the need for control of static and dynamic behavior of a system arrives at the controller with strong demands on runtime. This dissertation compares discrete controllers implemented in fixed point with different accuracies, using for both the simulation of the behavior of controllers manufactured in Matlab command language and VHDL 2008. VHDL 2008 still in development and standardization by the IEEE. The VHDL language is used in FPGAs that are high speed devices with parallel processing capability. The main objective of this work is the study and implementation of discrete controllers in FPGA with the help of the VHDL 2008 language, determining its strengths and limitations, particularly in regard to the structure of programming, error analysis and demand for resources. Results show that accuracy still need some improvements a standard to the VHDL 4.0, known as VHDL 2008, is delivered to the market a stable standard. However, knowing it limitations, it is possible implementations and use in conversion of analog signals to discrete, such as control and dynamic systems simulation like servomechanisms.
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Lin, Heng-An, et 林恆安. « The magnetic field simulation instrument for the hardware-in-the-loop testing of Satellite attitude control ». Thesis, 2018. http://ndltd.ncl.edu.tw/handle/4ktg59.
Texte intégralRésumé :
碩士國立中央大學
機械工程學系
106
This study is to develop a programmable, high-resolution dynamic magnetic field simulator by the Helmholtz Coil, which uses feed-forward control and feedback control to offset the external magnetic field disturbance to make a highly accurate dynamic magnetic field to supply Magnetic systems perform hardware-in-the-loop testing. The magnetic field is planned to have two modes: static magnetic field and dynamic magnetic field. The magnetic field range is +100000nT~-100000nT. The dynamic magnetic field can set the satellite orbit and initial attitude, simulate the magnetic field history of the satellite running in the orbit, and accept the satellite force feedback to calculate the attitude history, provide magnetic actuation attitude control system verification, and hardware-in-the-loop testing. Static magnetic fields can provide magnetic sensor for calibration and hardware-in-the-loop testing.
Livres sur le sujet "Hardware field simulator"
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Cangelosi, Angelo, et Minoru Asada, dir. Cognitive Robotics. The MIT Press, 2022. http://dx.doi.org/10.7551/mitpress/13780.001.0001.
Texte intégralRésumé :
The current state of the art in cognitive robotics, covering the challenges of building AI-powered intelligent robots inspired by natural cognitive systems. A novel approach to building AI-powered intelligent robots takes inspiration from the way natural cognitive systems—in humans, animals, and biological systems—develop intelligence by exploiting the full power of interactions between body and brain, the physical and social environment in which they live, and phylogenetic, developmental, and learning dynamics. This volume reports on the current state of the art in cognitive robotics, offering the first comprehensive coverage of building robots inspired by natural cognitive systems. Contributors first provide a systematic definition of cognitive robotics and a history of developments in the field. They describe in detail five main approaches: developmental, neuro, evolutionary, swarm, and soft robotics. They go on to consider methodologies and concepts, treating topics that include commonly used cognitive robotics platforms and robot simulators, biomimetic skin as an example of a hardware-based approach, machine-learning methods, and cognitive architecture. Finally, they cover the behavioral and cognitive capabilities of a variety of models, experiments, and applications, looking at issues that range from intrinsic motivation and perception to robot consciousness. Cognitive Robotics is aimed at an interdisciplinary audience, balancing technical details and examples for the computational reader with theoretical and experimental findings for the empirical scientist.
Chapitres de livres sur le sujet "Hardware field simulator"
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Dalton, Damian, Vivian Bessler, Jeffery Griffiths, Andrew McCarthy, Abhay Vadher, Rory O’Kane, Rob Quigley et Declan O’Connor. « APPLES : A Full Gate-Timing FPGA-Based Hardware Simulator ». Dans Field Programmable Logic and Application, 1162–65. Berlin, Heidelberg : Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45234-8_144.
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Parreira, A., J. P. Teixeira, A. Pantelimon, M. B. Santos et J. T. de Sousa. « Fault Simulation Using Partially Reconfigurable Hardware ». Dans Field Programmable Logic and Application, 839–48. Berlin, Heidelberg : Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45234-8_81.
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Lyu, Zhi feng, Li guo Xu, Xiao hu Fan, Jian yong Wang et Ning Liu. « Geomagnetic Field Simulation in Hardware-in-the-Loop Simulation System for Geomagnetic Navigation ». Dans Advances in Intelligent Systems and Computing, 173–80. Singapore : Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-1843-7_22.
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Xing, Zhaodong. « Multi-tracking Channels’ Hardware Simulation for GNSS Integrity Receiver Design in Transport Field ». Dans Proceedings of the 2013 International Conference on Electrical and Information Technologies for Rail Transportation (EITRT2013)-Volume I, 403–12. Berlin, Heidelberg : Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-642-53778-3_39.
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Wang, Liang, et Jianxin Zhao. « Performance Accelerators ». Dans Architecture of Advanced Numerical Analysis Systems, 191–213. Berkeley, CA : Apress, 2022. http://dx.doi.org/10.1007/978-1-4842-8853-5_7.
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AbstractThe Graphics Processing Unit (GPU) has become one of the most important types of hardware accelerators. It is designed to render 3D graphics and videos and still is core to the gaming industry. Besides creating stunning visual effects, programmers also take advantage of the GPU’s advantage in parallel processing in many fields to perform computing-heavy tasks, such as in health data analytics, physical simulation, artificial intelligence, etc.
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Borgeest, Kai, et Daniel Kern. « Safe Development Environments for Radiation Tracing Robots ». Dans Handbook of Research on Advanced Mechatronic Systems and Intelligent Robotics, 126–38. IGI Global, 2020. http://dx.doi.org/10.4018/978-1-7998-0137-5.ch006.
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Robots can substitute for men in radioactively-contaminated areas. This is a suitable field to deploy robots for measurements, repair, or clearance, but development and test of such robots could be dangerous, because radiation sources need to be handled. To avoid these hazards in development or public demonstrations, safe alternatives to radiation samples have been sought using an already existing robot (EtaBot). One proposed solution is an optical substitution (“light follower”), the other one a fully-digital simulation of the contaminated area and the robot movement inside it using a hardware-in-the-loop simulator (HiL).
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Ryan, Conor, Michael Tetteh, Jack McEllin, Douglas Mota-Dias, Richard Conway et Enrique Naredo. « ADDC : Automatic Design of Digital Circuit ». Dans Genetic Algorithms [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.104410.
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Digital circuits are one of the most important enabling technologies in the world today. Powerful tools, such as Hardware Description Languages (HDLs) have evolved over the past number of decades to allow designers to operate at high levels of abstraction and expressiveness, rather than at the gate level, which circuits are actually constructed from. Similarly, highly accurate digital circuit simulators permit designers to test their circuits before committing them to silicon. This is still a highly complex and generally manual task, however, with complex circuits taking months or even years to go from planning to silicon. We show how Grammatical Evolution (GE) can harness the standard tools of silicon design and be used to create a fully automatic circuit design system. Specifically, we use a HDL known as SystemVerilog and Icarus, a free, but powerful simulator, to generate circuits from high level descriptions. We apply our system to several well known digital circuit literature benchmarks and demonstrate that GE can successfully evolve functional circuits, including several which have been subsequently rendered in Field Programmable Gate Arrays (FPGAs).
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Gazzano, Julio Daniel Dondo, Fernando Rincon Calle, Julian Caba, David de la Fuente et Jesus Barba Romero. « Dynamic Reconfiguration for Internal Monitoring Services ». Dans Field-Programmable Gate Array (FPGA) Technologies for High Performance Instrumentation, 124–36. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-5225-0299-9.ch006.
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In hardware design flow, testing is the most important step to hardware quality assurance before a hardware component is released. However simulation and verification during design steps are not enough to guarantee a system without failures. In many cases the system fails after have been deployed. Dynamically reconfigurable FPGAs have the ability to reconfigure part of its architecture during run time without stopping the whole system. This feature is an added value that can be exploited for internal system monitoring and verification. Using partial reconfiguration, an Internal Monitoring System can be implemented in reconfigurable areas for monitoring different conditions and signals in the circuit, after implementation. This allows detecting and identifying those failures that were not possible to detect during simulation process.
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Tarver, Emily. « Virtual Simulation ». Dans Emerging Advancements for Virtual and Augmented Reality in Healthcare, 65–81. IGI Global, 2022. http://dx.doi.org/10.4018/978-1-7998-8371-5.ch005.
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Virtual simulation is a learning tool that employs specific hardware and software technology for simulation-based provider training within a digital domain. Extended reality or XR software includes virtual reality (VR), augmented reality (AR), and mixed reality (MR) programs that represent a rapidly growing area within the field of virtual simulation. This training may provide either provider- or patient-centered learning modules, with dedicated hardware and software centered on skill-based, 3D modeling or case-based learning. Demand for these learning programs in healthcare education was fueled by the remote learning needs of the COVID-19 pandemic. In addition to this growing demand, there is a significant role for many virtual simulation software programs within the traditional classroom and lecture hall. This is a previously untapped resource for simulation education. The flipped classroom model provides an opportune framework for the incorporation of immersive, virtual simulation learning programs within spaces previously limited to the more passive, podium-based lecture.
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Mahmoud, Imbaby Ismail, et Mohamed S. El Tokhy. « Development of Algorithms and Their Hardware Implementation for Gamma Radiation Spectrometry ». Dans Field-Programmable Gate Array (FPGA) Technologies for High Performance Instrumentation, 17–41. IGI Global, 2016. http://dx.doi.org/10.4018/978-1-5225-0299-9.ch002.
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The chapter describes how to develop algorithms for Gamma ray spectrometry portable instruments and then to implement them on FPGA devices as hardware platform. At first we consider the development of more accurate spectrum evaluation programs including pileup detection and recovery, dead time correction, coincidence summing and resolution enhancement algorithms which are implemented in MATLAB. The input signals are obtained through experimental setup or simulated model. Four different approaches are studied and evaluated for peak pileup problem within a spectroscopy system. In addition, x-ray spectrum evaluation enhancements are carried out and several algorithms are developed and compared. Hardware implementation using Xilinx DSP Boards as well as further improvements and modifications are discussed.
Actes de conférences sur le sujet "Hardware field simulator"
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Karkee, Manoj, Madhu Monga, Brian L. Steward, Joseph Zambreno et Atul G. Kelkar. « Real-Time Simulation and Visualization Architecture With Field Programmable Gate Array (FPGA) Simulator ». Dans ASME 2010 World Conference on Innovative Virtual Reality. ASMEDC, 2010. http://dx.doi.org/10.1115/winvr2010-3772.
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Real-time simulation of dynamic vehicle system models is essential to facilitate advances in operator and hardware in the loop simulation and virtual prototyping. Real-time virtual reality-based simulation enables users to visualize and perceive the effect of their actions during the simulation. As model complexity is increased to improve the model fidelity, the computational requirements will also increase, thus increasing the challenge to meet real-time constraints. A distributed simulator architecture was developed for off-road vehicle dynamic models and 3D graphics visualization to distribute the overall computational load across multiple computational platforms. This architecture consisted of three major components: a dynamic model simulator, a virtual reality simulator, and an interface to controller and input hardware devices. The dynamic model simulator component was developed using Matlab/Simulink Real Time Workshop on a PC and also using Field Programmable Gate Arrays (FPGA), which offered a highly parallel hardware platform. The simulator architecture reduced the computational load to an individual platform and increased the real-time simulation capability with complex off-road vehicle system models and controllers. The architecture was used to develop, simulate and visualize a tractor and towed implement steering dynamics model. The model also included a steering valve subsystem which contained very high frequency hydraulic dynamics and required 10 μs integration time step for numerical stability. The real-time simulation goal was not achievable for the model with this level of complexity when the PC-based simulator was used. However, the FPGA-based simulator achieved a real-time goal taking only 2 μs to complete one integration time step.
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Culic, Ioana, Alexandru Radovici et Calin Dumitru. « HARDWARE SIMULATOR FOR TEACHING INTERNET OF THINGS ». Dans eLSE 2020. University Publishing House, 2020. http://dx.doi.org/10.12753/2066-026x-20-098.
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Some of the significant technological advancements nowadays are related to the Internet of Things (IoT) field. While connected systems have been used for a long time, they were considered a niche area and were mostly used in the industry. Currently, connected devices and sensors have become extremely popular, and the IoT is now considered a subject that any technical person should be aware of. The result is that it has become a vital component of all computer science classes. Today, most high-schools and universities have introduced IoT in their curricula. For many institutions, especially high-schools, the costs of acquiring the hardware equipment necessary to teach Internet of Things courses are very high, and most of the time, students have to share the hardware kits available. What is more, students can interact with the hardware for a limited number of hours a week, during classes, leaving them with no possibility to practice the skills they acquire at home, except if they purchase the same hardware kits they use at classes. In this paper, we present an open-source software platform designed to simulate hardware devices, allowing teachers and students to build and run simple IoT applications without the need for actual hardware. The platform simulates a Raspberry Pi device, the most popular hardware platform used in education. While not designed to replace the hardware components completely, the simulator is built as a complementary solution to the development platforms, enabling students to quickly prototype simple applications, which can then be run on the actual hardware. The result is an open and free to use platform that allows simple IoT programs to be run outside an actual hardware platform, making the teaching process faster and less expensive.
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Martins Mothé, João Elias, et Cedric Cordeiro. « Nanosats’ behavior hardware in the loop simulator under earth’s low orbit magnetic field, LEO. » Dans 24th ABCM International Congress of Mechanical Engineering. ABCM, 2017. http://dx.doi.org/10.26678/abcm.cobem2017.cob17-2175.
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Özdemirci, Sahir Deniz, et Filip Škultéty. « Upgrade of the BITD to an online multirole simulator ». Dans Práce a štúdie. University of Žilina, 2021. http://dx.doi.org/10.26552/pas.z.2021.1.19.
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Thanks to the possibility of new technologies, there are several alternatives to upgrade the current hardware and software of flight simulators, such as the implementation of photorealistic scenarios, a better field of view or a realistic flight model of a selected aircraft. A part is devoted to the current technical parameters of the ELITE S612 BITD simulator. The practical part describes three options for computer software, followed by three options for replacing hardware and three options for updating the visual system.
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Pavan, A. Massi, S. Castellan et G. Sulligoi. « An innovative photovoltaic field simulator for hardware-in-the-loop test of power conditioning units ». Dans 2009 International Conference on Clean Electrical Power (ICCEP). IEEE, 2009. http://dx.doi.org/10.1109/iccep.2009.5212086.
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Höhn, Patrick, Roger Aragall, Michael Koppe et Joachim Oppelt. « Modeling, Simulation and Validation of the Fluid Temperature of a Physical Drilling Simulator for Experimental Planning ». Dans ASME 2018 37th International Conference on Ocean, Offshore and Arctic Engineering. American Society of Mechanical Engineers, 2018. http://dx.doi.org/10.1115/omae2018-77275.
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Drilling equipment tests during field operations are always affected by uncertainties and variations regarding the local conditions in the borehole. In order to provide a more controlled testing environment for research, a hardware simulator was established at the Drilling Simulator Celle, Clausthal University of Technology. The simulator replicates the last 25 meters of a horizontal borehole and permits the drilling of a five-meter long rock sample. The setup includes a flow loop with two pumps for borehole cleaning and cuttings transport during the drilling process. During operation, temperature of the fluid increases due to pressure losses in the loop. This paper introduces a basic model to determine the maximum allowable continuous operation time of the hardware setup. Further improvements can be achieved by doing sensitivity analyses of the parameters affecting the system behavior, e.g. ambient temperatures or mass flow rate. Measurements from the hardware setup are used for validation of the model and show consistent results.
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Galindo-Garci´a, Iva´n F., Antonio Tavira-Mondrago´n et Sau´l Rodri´guez-Lozano. « A Hydroelectric Plant Simulation Model to Test the Performance of Actual Governor Control Systems ». Dans ASME 2008 Power Conference. ASMEDC, 2008. http://dx.doi.org/10.1115/power2008-60152.
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A simulation model of the hydraulic system of a hydroelectric power plant is developed and implemented in a real time simulator. The main purpose of the simulator is to test the performance of actual governor control systems using hardware-in-the-loop techniques, in which the actual governor control system is connected to a real time simulator instead of being connected to real equipment. This paper focuses on the modeling of the hydraulic system to be implemented in the simulator. The model consists of an unrestricted reservoir, conduits to transport water, and a turbine to convert the potential energy of the fluid into mechanical power. A nonlinear mathematical model for a non-elastic water column is implemented. Effects due to a surge tank and to various turbines connected to a common tunnel are included in the model by considering head and flow variations at the junction of the common tunnel and the individual penstocks. The model is evaluated by comparing results from simulations with field tests from a four-unit hydroelectric power plant (55 MW per unit). Comparisons show that the model reproduces the general behavior of the field tests. However some deviations are observed during the transient response, in particular the simulation results appear to respond faster than field data.
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Middya, Usuf, Abdulrahman Manea, Maitham Alhubail, Todd Ferguson, Thomas Byer et Ali Dogru. « A Massively Parallel Reservoir Simulator on the GPU Architecture ». Dans SPE Reservoir Simulation Conference. SPE, 2021. http://dx.doi.org/10.2118/203918-ms.
Texte intégralRésumé :
Abstract Reservoir simulation computational costs have been continuously growing due to high-resolution reservoir characterization, increasing model complexity, and uncertainty analysis workflows. Reducing simulation costs by upscaling is often necessary for operational requirements. Fast evolving High-Performance-Computing (HPC) technologies offer opportunities to reduce cost without compromising fidelity. This work presents a novel in-house massively parallel full-physics reservoir simulator running on the emerging graphics processing unit (GPU) architecture. Almost all the simulation kernels have been designed and implemented to honor the GPU single insruction, multiple data (SIMD) programming paradigm. These kernels include physical property calculations, phase equilibrium computations, Jacobian construction, linear and nonlinear solvers, and wells. Novel techniques are devised in various kernels to expose enough parallelism to ensure that the control and data-flow patterns are well suited for the GPU environment. Mixed-precision computation is also employed when appropriate (e.g., in derivative calculation) to reduce computational costs without compromising the solution accuracy. The GPU implementation of the simulator is tested and benchmarked using various reservoir models, ranging from the synthetic SPE10 Benchmark (Christie & Blunt, 2001) to several industrial-scale models. These real field models range in size from tens of millions to hundreds of millions of cells with black-oil and multicomponent compositional fluid. The GPU simulator is benchmarked on the IBM AC922 massively parallel architecture having tens of Nvidia Volta V100 GPUs. To compare performance with CPU architectures, an optimized CPU implementation of the simulator is benchmarked on the IBM AC922 CPUs and on a cluster consisting of thousands of Intel Haswell-EP Xeon® CPU E5-2680 v3. Detailed analysis of several numerical experiments comparing the simulator performance on the GPU and the CPU architectures is presented. In almost all of the cases, the analysis shows that the use of hardware acceleration offers substantial benefits in terms of wall time and power consumption. This novel in-house full-physics, black-oil and compositional reservoir simulator employs several novel techniques in various simulation kernels to ensure full utilization of the GPU resources. Detailed analysis is presented to highlight the simulator performance in terms of runtime reduction, parallel scalability and power savings.
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Kim, Sung-Soo, Wan Hee Jeong et Seonghoon Kim. « Compliance Effect Consideration for Real-Time Multibody Vehicle Dynamics Using Quasi-Static Analysis ». Dans ASME 2007 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2007. http://dx.doi.org/10.1115/detc2007-34739.
Texte intégralRésumé :
HILS (Hardware-in-the Loop Simulation) vehicle simulator is one of the most effective tools to develop control subsystems for the intelligent vehicles, since expensive vehicle field tests can be replaced with virtual tests in the HILS simulator. In the HILS simulator, the software vehicle dynamics model must be solved in real-time, and it must also reproduce the real vehicle motions. Compliance effects from suspension bush elements significantly influences the vehicle behavior. In order to include such compliance effects to the vehicle model, normally the spring-damper model of the bush elements is used. However, high stiffness of the bush elements hinders real-time simulations. Thus, it is necessary to have an efficient method to include compliance effects for the real-time multibody vehicle dynamics model. In this paper, compliance model for real-time multibody vehicle dynamics is proposed using quasi-static analysis. The multibody vehicle model without bush elements is used based on the subsystem synthesis method which provides real-time computation on the multibody vehicle model. Reaction forces are computed in the suspension subsystem. According to deformation from the quasi-static analysis using reaction forces and bush stiffness, suspension hardpoint locations and suspension linkage orientation are changed. To validate the proposed method, quarter car simulations and full car bump run simulations are carried out comparing with the ADAMS vehicle model with bush elements. CPU times are also measured to see the real-time capabilities of the proposed method.
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Ghabcheloo, Reza, Mika Hyvo¨nen, Jarno Uusisalo, Otso Karhu, Juha Ja¨ra¨ et Kalevi Huhtala. « Autonomous Motion Control of a Wheel Loader ». Dans ASME 2009 Dynamic Systems and Control Conference. ASMEDC, 2009. http://dx.doi.org/10.1115/dscc2009-2653.
Texte intégralRésumé :
This paper addresses the problem of autonomous control of a hydraulically actuated articulated-frame-steering (AFS) mobile machine— a wheel loader. Our autonomous motion control system includes a mission planning graphical user interface, an improved odometry algorithm and a GPS device for navigation purposes, together with a model based path-following control strategy, and speed control. The test platform is a small prototype wheel loader based on Avant-635 whose hydraulic components are substituted by electrically controlled equivalents. System development and preliminary calibrations are done using GIMsim— an elaborated semi-empirical hardware-in-the-loop simulator. Some field experiments are presented that demonstrate satisfactory performance of the system at this stage. Further tunings are required to reach a desired performance.