Articles de revues : « Embedded software design and verification »

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Geng, Bo, et Qing Hua Cao. « Design and Realization of Simulation Environment of Embedded Software and Hardware Intergration Based on GEF ». Advanced Materials Research 756-759 (septembre 2013) : 2226–30. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.2226.

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Embedded software and hardware integration simulation platform is developed for simulating the embedded systems design process in current engineering system, which can facilitate finding various problems in system design process. For example, in the system scheme phase, the scheme and design verification are untimely and inadequate. In the early prototype phase, software development lags behind result in deferral of the overall progress of the system. And in the late prototype stage, the problem is lacking configuration item test environment. Embedded software and hardware integration simulation platform can provide verification of hardware and software integration and test development environment. Therefore, the quality of software development in embedded systems can be significantly improved and development cycle can be remarkably shortened by using this simulation platform.

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Dasgupta, Pallab, Mandayam K. Srivas et Rajdeep Mukherjee. « Formal Hardware/Software Co-Verification of Embedded Power Controllers ». IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, n^o 12 (décembre 2014) : 2025–29. http://dx.doi.org/10.1109/tcad.2014.2354297.

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Chen, Ce, Shao Cai Zhao, Yong Hu et Guo Kai He. « Design and Realization of Universal Integrated Testing Platform for Equipment-Embedded Software ». Applied Mechanics and Materials 635-637 (septembre 2014) : 1175–78. http://dx.doi.org/10.4028/www.scientific.net/amm.635-637.1175.

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An universal testing platform for equipment-embedded software is designed and realized to support the dynamic verification test of embedded software on CI level and system level. This Platform, based on LAN and USB bus architecture, has provided the function of system interface modelling, test project management, test case script code, test result control and analysis, and test report generation, and is available for real time, closed-loop and non-invasive dynamic testing on the embedded software with the characteristic of portability, easy operation, flexibility in size configuration and universality of protocol description.

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Chen, Xi, Harry Hsieh, Felice Balarin et Yosinori Watanabe. « Formal Verification for Embedded System Designs ». Design Automation for Embedded Systems 8, n^o 2/3 (juin 2003) : 139–53. http://dx.doi.org/10.1023/b:daem.0000003959.60964.4d.

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Chen, Xi, Harry Hsieh et Felice Balarin. « Verification Approach of Metropolis Design Framework for Embedded Systems ». International Journal of Parallel Programming 34, n^o 1 (25 janvier 2006) : 3–27. http://dx.doi.org/10.1007/s10766-005-0002-x.

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Park, Sa-Choun, Gi-Hwon Kwon et Soon-Hoi Ha. « Automatic Verification of the Control Flow Model for Effective Embedded Software Design ». KIPS Transactions:PartA 12A, n^o 7 (1 décembre 2005) : 563–70. http://dx.doi.org/10.3745/kipsta.2005.12a.7.563.

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Dong, Zhijiang, Yujian Fu et Yue Fu. « Runtime Verification on Robotics Systems ». International Journal of Robotics Applications and Technologies 3, n^o 1 (janvier 2015) : 23–40. http://dx.doi.org/10.4018/ijrat.2015010102.

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Runtime verification is a technique for generating monitors from formal specification of expected behaviors for the underlying system. It can be applied to automatically evaluate system execution, either on-line or off-line, analyzing extracted execution traces; or it can be used online during operation, potentially steering the application back to a safety region if a property is violated. As a so-called light-weighted formal method, runtime verification bridges the gap between system design and implementation and shorten the distance of software quality assurance between the software testing and model checking and theorem proving. Runtime verification is considered as a highly scalable and automatic technique. Most of current runtime verification research are endeavored on the program context, in other words, on the program side and falls in the implementation level. These applications limited the benefits of runtime verification that bridges the gap among types of applications. With the proliferation of embedded systems and mobile device, dynamically verifying the firmware and mobile apps becomes a new emerging area. Due to the characteristics of runtime verification technique and limitations of the robotics systems, so far, very few research and project are located in the runtime verification on the firmware of embedded systems, which appear in most of robotics systems. Robotics systems are programmed on the firmware and only observed on device. In this paper, the authors first discussed the current runtime verifications on the embedded systems with limitations. After that, a layered runtime verification framework will be presented for the firmware verification. The case study is applied on the commonly recognized educational toolkit – LEGO Mindstorm robotics systems.

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Cunning, Steve J., Stephan Schulz et Jerzy W. Rozenblit. « An Embedded System's Design Verification Using Object-Oriented Simulation ». SIMULATION 72, n^o 4 (avril 1999) : 238–49. http://dx.doi.org/10.1177/003754979907200403.

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Cheddadi, Youssef, Fatima Errahimi et Najia Es-sbai. « Design and verification of photovoltaic MPPT algorithm as an automotive-based embedded software ». Solar Energy 171 (septembre 2018) : 414–25. http://dx.doi.org/10.1016/j.solener.2018.06.085.

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Júnior, José, Alisson Brito et Tiago Nascimento. « Verification of Embedded System Designs through Hardware-Software Co-Simulation ». International Journal of Information and Electronics Engineering 5, n^o 1 (2015) : 68–73. http://dx.doi.org/10.7763/ijiee.2015.v5.504.

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Pao-Ann Hsiung, Shang-Wei Lin, Chih-Hao Tseng, Trong-Yen Lee, Jin-Ming Fu et Win-Bin See. « VERTAF : an application framework for the design and verification of embedded real-time software ». IEEE Transactions on Software Engineering 30, n^o 10 (octobre 2004) : 656–74. http://dx.doi.org/10.1109/tse.2004.68.

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Xiong, Zhi Wen, Wen Feng Wang et Hong Zeng. « Design of FPGA-Based Fault-Tolerant Embedded System ». Advanced Materials Research 546-547 (juillet 2012) : 1574–79. http://dx.doi.org/10.4028/www.scientific.net/amr.546-547.1574.

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Fault tolerant is one of major requirements for embedded systems. As the embedded systems become more and more complex, more chances for various fault. When design embedded system developer has to handle these faults. Before handling faults designer has to identify and understand the types and nature of faults.Faults is the sources for low dependability, faults can be hardware and software. Hardware faults can be distinguished from systematic faults like software or design errors. The Fault can be deleted, such as extensive testing or formal verification and tolerated by fault tolerance techniques. We restrict ourselves to the problem of fault tolerance and refer to other methods for troubleshooting.This paper discusses a new design method about the fault tolerant system of embedded system. We designed a fault tolerant system of data acquisition system in dynamically re-configurable FPGA. The experiment results show that the system not only be able to higher self-adaptive ability and reliability, but also can Through the FGPA to complete a specific algorithm.

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Fogarty, Padraig, Ciaran MacNamee et Donal Heffernan. « On‐chip support for software verification and debug in multi‐core embedded systems ». IET Software 7, n^o 1 (février 2013) : 56–64. http://dx.doi.org/10.1049/iet-sen.2011.0212.

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Trost, Andrej, Andrej Zemva et Matjaz Verderber. « Prototyping Hardware and Software Environment for Teaching Digital Circuit Design ». International Journal of Electrical Engineering & ; Education 38, n^o 4 (octobre 2001) : 368–78. http://dx.doi.org/10.7227/ijeee.38.4.9.

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In the paper, we present our latest achievements and experience in undergraduate teaching of digital circuits, integrated circuits and embedded systems by exploiting our prototyping hardware and software environment. The hardware environment is based on Field Programmable Gate Array (FPGA) modules that provide sufficient flexibility and support a broad scope of digital design applications. In addition, the designed software environment supports user-friendly hardware verification of the logic circuits implemented on the hardware system. We describe some typical applications and student projects implemented on the programmable prototyping system.

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Anwar, Muhammad Waseem, Muhammad Rashid, Farooque Azam, Muhammad Kashif et Wasi Haider Butt. « A model-driven framework for design and verification of embedded systems through SystemVerilog ». Design Automation for Embedded Systems 23, n^o 3-4 (8 novembre 2019) : 179–223. http://dx.doi.org/10.1007/s10617-019-09229-y.

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Di Guglielmo, Giuseppe, Luigi Di Guglielmo, Andreas Foltinek, Masahiro Fujita, Franco Fummi, Cristina Marconcini et Graziano Pravadelli. « On the integration of model-driven design and dynamic assertion-based verification for embedded software ». Journal of Systems and Software 86, n^o 8 (août 2013) : 2013–33. http://dx.doi.org/10.1016/j.jss.2012.08.061.

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Venugopal, Manokar, Manju Nanda, G. Anand et Hari Chandana Voora. « An integrated Hardware/Software Verification and Validation methodology for Signal Processing Systems ». ITM Web of Conferences 50 (2022) : 02001. http://dx.doi.org/10.1051/itmconf/20225002001.

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The testing and validation services team assesses project deliverables at various stages of development using innovative and effective verification and validation, to ensure that the deliverables are compliance with the customer specifications and requirements. Whenever new products and devices are released, completely integrated verification and validation services are delivered to accurate and complete records usability, performance, and quality assurance services. Throughout the product development and testing process, the testing and validation services team employs verification and validation techniques. Code reviews, walk through, inspections, desk-checking, and code execution are all examples of verification and validation techniques. Services for verification and validation are used to assess whether or not the software or application provided complies with the requirements and serves the intended purpose. A procedure used to ensure that the software created is of good quality and consistently operates as expected is independent testing and validation services. Unit testing (also known as “White Box Testing”), hardware-software integration testing (HSIT), and system testing are the three primary independent verification and validation approaches (Black Box Testing). The teams responsible for the verification and validation services actively participate in each stage of the project and design the services according to the project’s needs (e.g., prototype, spiral, iterative, V Model, and Agile). Our expertise in the embedded domain, tried-and-true verification and validation techniques, and a thorough methodology provide a quick turnaround and excellent results for the targeted solution. Independent Verification and validation services covering Source code, design, and requirements White box testing, or unit testing Testing for hardware-software integration Black box testing, or system testing To reduce test cycle-time significantly on test Automation solutions. Verification and validation techniques can be used to effectively and efficiently carry out stress and performance tests, and to detect defects early in the life cycle. Documentation of test process. Liaison and Certification

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Li, Junquan, Mark Post, Thomas Wright et Regina Lee. « Design of Attitude Control Systems for CubeSat-Class Nanosatellite ». Journal of Control Science and Engineering 2013 (2013) : 1–15. http://dx.doi.org/10.1155/2013/657182.

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We present a satellite attitude control system design using low-cost hardware and software for a 1U CubeSat. The attitude control system architecture is a crucial subsystem for any satellite mission since precise pointing is often required to meet mission objectives. The accuracy and precision requirements are even more challenging for small satellites where limited volume, mass, and power are available for the attitude control system hardware. In this proposed embedded attitude control system design for a 1U CubeSat, pointing is obtained through a two-stage approach involving coarse and fine control modes. Fine control is achieved through the use of three reaction wheels or three magnetorquers and one reaction wheel along the pitch axis. Significant design work has been conducted to realize the proposed architecture. In this paper, we present an overview of the embedded attitude control system design; the verification results from numerical simulation studies to demonstrate the performance of a CubeSat-class nanosatellite; and a series of air-bearing verification tests on nanosatellite attitude control system hardware that compares the performance of the proposed nonlinear controller with a proportional-integral-derivative controller.

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MOHAMMADZADEH, NASER, SHAAHIN HESSABI, MAZIAR GOUDARZI et MAHDI MALAKI. « A FRAMEWORK FOR OBJECT-ORIENTED EMBEDDED SYSTEM DEVELOPMENT BASED ON OO-ASIPS ». Journal of Circuits, Systems and Computers 17, n^o 06 (décembre 2008) : 973–93. http://dx.doi.org/10.1142/s0218126608004812.

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The growing complexity of today's embedded systems demands new methodologies and tools to manage the problems of analysis, design, implementation, and validation of complex-embedded systems. Focusing on this issue, this paper describes a design and implementation toolset using our ODYSSEY methodology, which advocates object-oriented (OO) modeling of embedded systems and its ASIP-based implementation. The proposed approach promotes a smooth transition from high-level object-oriented specification to the final embedded system, which is composed of hardware and software components. The transition from higher to lower abstraction levels is facilitated by the use of our GUI, which supports the intermediate steps of the design and implementation process. In order to illustrate the proposed approach and related toolset, we apply this top-down design and implementation framework to real-world embedded systems, namely JPEG codec and Motion JPEG codec. Experimental results show that the developed tool remarkably decreases the design and verification time with modest performance penalty.

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ENGELL, SEBASTIAN, SVEN LOHMANN et OLAF STURSBERG. « VERIFICATION OF EMBEDDED SUPERVISORY CONTROLLERS CONSIDERING HYBRID PLANT DYNAMICS ». International Journal of Software Engineering and Knowledge Engineering 15, n^o 02 (avril 2005) : 307–12. http://dx.doi.org/10.1142/s021819400500204x.

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This contribution proposes a link between the specification of supervisory controllers by Sequential Function Charts (SFC) and the verification of embedded systems with hybrid dynamics. The SFC are transformed into modular timed automata using a procedure based on graph grammars. The resulting controller model is composed with a hybrid automaton (with possibly nonlinear continuous dynamics) that models the plant behavior. In order to verify safety properties of the composed system algorithmically, a tool implementing the recently proposed approach of counterexample guided model checking is employed. The procedure is illustrated for a processing system example.

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Fukano, Ryo, et Masato Ishikawa. « Human-Error Prevention for Autonomous Edge Software Using Minimalistic Modern C++ ». Big Data and Cognitive Computing 3, n^o 4 (4 novembre 2019) : 52. http://dx.doi.org/10.3390/bdcc3040052.

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In science and engineering using edge-embedded software, it is necessary to demonstrate the validity of results; therefore, the software responsible for operating an edge system is required to guarantee its own validity. The aim of this study is to guarantee the validity of the sampled-time filter and time domain as fundamental elements of autonomous edge software. This requires the update law of a sampled-time filter to be invoked once per every control cycle, which we guaranteed by using the proposed domain specific language implemented by a metaprogramming design pattern in modern C++ (C++11 and later). The time-domain elements were extracted from the software, after which they were able to be injected into the extracted software independent from the execution environment of the software. The proposed approach was shown to be superior to conventional approaches that only rely on the attention of programmers to detect design defects. This shows that it is possible to guarantee the validity of edge software by using only a general embedded programming language such as modern C++ without auxiliary verification and validation toolchains.

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Zhao, Yan Ling, et Shi Hai Zhang. « Study on GPRS Mobile Terminal System for Rural Informatization ». Advanced Materials Research 1078 (décembre 2014) : 262–65. http://dx.doi.org/10.4028/www.scientific.net/amr.1078.262.

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In this paper, GPRS module, including the design and implementation of the telephone terminal interface circuit design TV interface circuit, interface GPRS module and starting circuit are designed based on ARM embedded platform. Software is also designed primarily Bootloader and Linux kernel porting, system part of the driver, the results of the design through experimental verification, the results show that the system can communicate data, you can use AT commands to achieve messaging and voice capabilities.

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El-MALAKI, M. H., M. WATHEQ El-KHARASHI, S. HAMMAD, A. SALEM et A. WAHDAN. « A PLATFORM APPROACH FOR HARDWARE/SOFTWARE CO-DESIGN WITH SUPPORT FOR RTOS-BASED SYSTEMS ». Journal of Circuits, Systems and Computers 16, n^o 06 (décembre 2007) : 961–79. http://dx.doi.org/10.1142/s0218126607004015.

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We propose a new flow for hardware/software co-design, based on the platform-based design, which forms a base for further automation attempts of the co-design process. We prove the applicability of the proposed flow on co-designing generic systems as well as RTOS-based systems. Our proposed flow starts with a software-only solution in which all system functionality is described as embedded software targeting a selected platform. Then, the flow iterates through co-verification, profiling, partitioning, and co-synthesis until the design criteria are met. We present four test cases to show the effectiveness of our proposed methodology. The main contribution added by the proposed methodology is incorporating the target application platform at the first stage of the flow then applying our iterative co-design algorithm without altering the main platform. This opposes other co-design methodologies that let the platform details be synthesized at later stages, widening the exploration space to be unrealistic and producing platforms that may vary to a large extent compared to the pre-verified application platform. The other contribution is the study provided on the effect of co-design on the behavior of RTOS-based platforms, which brings the flow closer to real-case problems, where most embedded systems utilize RTOS in their software stack.

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Prekop, Lubomir. « Modeling of Load Test of Piles ». Applied Mechanics and Materials 837 (juin 2016) : 175–78. http://dx.doi.org/10.4028/www.scientific.net/amm.837.175.

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The paper deals with design of model and verification of a pile loaded by pressure. The pile is embedded in the layered ground mass. Its model has been created using the ANSYS software system. The obtained results have been compared with results of the pile loading test performed during the construction of a multifunctional building. In the conclusion the results have been presented in graphs.

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Wang, Tun, et Yu Tian. « Design of Embedded Ai Engine Based on the Microkernel Operating System ». Wireless Communications and Mobile Computing 2022 (21 avril 2022) : 1–9. http://dx.doi.org/10.1155/2022/9304019.

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At present, the application of the embedded microkernel operating system in military and civil fields has begun to take shape, but it has not yet formed a unified method and standard. Due to its high performance, low frequency, and high reliability, dual-core embedded processors are getting the attention of many chip manufacturers. Compatibility has been favored by many telecom equipment manufacturers and embedded high-end application integrators, but the dual-core embedded processor needs a new real-time operating system to support it, so that it can give full play to the high performance of the dual-core. It paves the way for the application of its processor in the embedded field, but the design of embedded AI engine is not transparent to it; so, it needs the support of operating system. The user code is used to be in the operating system processor environment; so, it can be used on dual core processor first. In the real-time operating system that supports dual-core processors, the part that needs to be modified is mainly concentrated in the kernel part; so, the core design is the key point to support dual-core processors. This article is to seize this key point to carry out in-depth research. The difference and influence of hardware architecture between dual-core processor and single-core processor are the primary content of the study. Through the research of the dual-core processor architecture, the general abstraction of the dual-core processor architecture is obtained, which is the starting point of the follow-up research. This paper mainly studies the design of embedded AI engine based on the microkernel operating system, extracts the security requirements of the operating system, designs and implements the operating system from the perspective of formal verification, and considers the verification problem under the background of RTOS development, so as to avoid using too many complex data structures and algorithms in the system design and reduce the difficulty of experimental verification. In this paper, we use the spatiotemporal data model, data sharing security in the cloud environment, symmetric encryption scheme, and Paillier homomorphic encryption method to study the design of embedded AI engine based on the microkernel operating system. According to the idea of microkernel architecture, the kernel is divided into four main modules: task processing, semaphore, message queue, interrupt, and exception processing, and the lock mechanism to prevent reentrancy in software is analyzed separately. Three core function modules, initialization, process grinding, and interrupt processing, are extracted from the microkernel operating system to form the formal verification area of the operating system. At the same time, the system syntax and semantics of related rights are separated, and the main rationalization rules are described. The results show that the core of the microkernel operating system in five states adopts the microkernel architecture in the dual core environment. The microkernel architecture is a compact system kernel with good adjustability. Based on the analysis of the microkernel operating system, the internal structure of each module in the kernel is summarized, and the modules are modified according to the machine characteristics of the dual core processor; it corresponds to adding modules to meet the characteristics of dual core architecture. Kernel design is a systematic theoretical research process. This paper only uncovers the tip of the iceberg of real-time operating system kernel design on dual-core embedded processors. It is necessary to understand the kernel more deeply and master the kernel in the future work and study.

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Wang, Tao, Li Wang, Pengfei Yan, Renu Popli, Poonam Rani et Rajeev Kumar. « Application of embedded Linux in the design of Internet of Things gateway ». Journal of Intelligent Systems 31, n^o 1 (1 janvier 2022) : 1014–23. http://dx.doi.org/10.1515/jisys-2021-0208.

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Abstract To study the development trend of embedded platforms in home appliances Internet of Things (IoT), an application of embedded Linux in the design of IoT gateway is designed. ARM microprocessor S3C2410, EM310 radio frequency (RF) module, and Ethernet DM9000A module are used to realize the home network information-processing platform. The platform utilizes existing network facilities, RF modules, and network interface modules to realize the interconnection of the home perception network through wireless or wired links. For experimental analysis, Ping the central server (gateway) from the IoT node B is set to twice: The first time ttl = 255 time = 1.9 ms, the second time: ttl = 255 time = 2.4 ms. After application verification, the system has the characteristics of low cost, small size, low power consumption, and vital ease of use. It can not only integrate the home Internet and the IoT gateway but also directly run application-layer communication protocols such as HTTP/MQTT between IoT nodes and Internet terminals. The design supports multi-hop communication and significantly increases the deployment range of IoT nodes without signal relay equipment, hence reducing the cost of IoT networking and the complexity of the network architecture.

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Jeong, Eunjin, Dowhan Jeong et Soonhoi Ha. « Dataflow Model–based Software Synthesis Framework for Parallel and Distributed Embedded Systems ». ACM Transactions on Design Automation of Electronic Systems 26, n^o 5 (5 juin 2021) : 1–38. http://dx.doi.org/10.1145/3447680.

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Existing software development methodologies mostly assume that an application runs on a single device without concern about the non-functional requirements of an embedded system such as latency and resource consumption. Besides, embedded software is usually developed after the hardware platform is determined, since a non-negligible portion of the code depends on the hardware platform. In this article, we present a novel model-based software synthesis framework for parallel and distributed embedded systems. An application is specified as a set of tasks with the given rules for execution and communication. Having such rules enables us to perform static analysis to check some software errors at compile-time to reduce the verification difficulty. Platform-specific programs are synthesized automatically after the mapping of tasks onto processing elements is determined. The proposed framework is expandable to support new hardware platforms easily. The proposed communication code synthesis method is extensible and flexible to support various communication methods between devices. In addition, the fault-tolerant feature can be added by modifying the task graph automatically according to the selected fault-tolerance configurations by the user. The viability of the proposed software development methodology is evaluated with a real-life surveillance application that runs on six processing elements.

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Safar, Mona, Magdy A. El-Moursy, Mohamed Abdelsalam, Ayman Bakr, Keroles Khalil et Ashraf Salem. « Virtual Verification and Validation of Automotive System ». Journal of Circuits, Systems and Computers 28, n^o 04 (31 mars 2019) : 1950071. http://dx.doi.org/10.1142/s0218126619500713.

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An integrated framework for Virtual Verification and Validation (VVV) for a complete automotive system is proposed. The framework can simulate/emulate the system on three levels: System on Chip (SoC), Electronic control unit (ECU) and system level. The framework emulates the real system including hardware (HW) and software (SW). It enhances the automotive V-cycle and allows co-development of the automotive system SW and HW. The procedure for debugging AUTOSAR application on the virtual platform (VP) is shown. SW and HW profiling is feasible with the presented methodology. Verification and validation of automotive embedded SW is also presented. The proposed methodology is efficient as the system complexity increases which shortens the development cycle of automotive system. It also provides fault injection capability. With HW emulation, co-debugging mechanism is demonstrated. A case study covering the framework capability is presented. The case study demonstrates the proposed framework and methodology to design, simulate, trace, profile and debug AUTOSAR SW using VPs.

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Li, Mutong, Fujun Zhou, Tianyu Li et Yuan Wei. « Optimization Design and Simulation for Pricking Mechanism of Off-Centre Embedded Seed Metering Device ». Journal of Agricultural Science 9, n^o 6 (15 mai 2017) : 221. http://dx.doi.org/10.5539/jas.v9n6p221.

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In order to improve the quality of pricking hole and reduce throwing soil as merering the field, this paper presents a method of off-centre embedded pricking mechanism operation. Established a mathematical model of pricking hole mechanism, preparation of computer aided analysis platform by using VB software, and the simulation effects are buried and the effects of the eccentricity, rocker arm length, pricking hole connected with the handle, the swing rod length, length the pricking hole angle and swing arm and the connecting rod handle parameters related to the initial position. One group of optimization parameters: radial eccentricity 50mm, pricking hole arm length 220 mm, connecting handle length 135 mm, pendulum length 120 mm, pricking hole arm and the connecting handle 55 degree angle, pendulum hinge rotation center end and rocker wire length 130 mm, connecting with the horizontal angle of 5 degrees. Through the verification, pricking hole mechanism after optimization has been a significant improvement in reducing throwed soil problems and improve the pricking quality.

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She, Chen Hua, et Tsung Hua Yang. « Design of a Cutting Point Control Algorithm for Five-Axis Machining ». Applied Mechanics and Materials 249-250 (décembre 2012) : 702–6. http://dx.doi.org/10.4028/www.scientific.net/amm.249-250.702.

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Five-axis machine tool with two additional rotary axes has been widely used in defense, aerospace and the consumer industries, and is an important process of precision manufacturing. Traditional five-axis program depends on the machine tool’s configuration and machining setting. This leads to inconvenience of reprogramming five-axis NC code for the end users. This paper proposes a cutting point control algorithm for five-axis machining. Although the commercial advanced controllers provide this function, they are very expensive and restricted to export. The developed algorithm can be embedded to the PC-based controller so that the specific cutter location data can be transformed and employed easily for different cutting tools. Verification using VERICUT solid cutting simulation software demonstrated the correctness of the generated cutter location data.

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Liu, Jiangchao, Liqian Chen et Xavier Rival. « Automatic Verification of Embedded System Code Manipulating Dynamic Structures Stored in Contiguous Regions ». IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, n^o 11 (novembre 2018) : 2311–22. http://dx.doi.org/10.1109/tcad.2018.2858462.

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Feng, Xia, Qun Zhang Tu, Ming Pan, Xiao Chen Zhang et Wei Jie Zheng. « Design and Debugging of PMSM Control Algorithm for Electric Drive Tracked Vehicle ». Applied Mechanics and Materials 697 (novembre 2014) : 249–53. http://dx.doi.org/10.4028/www.scientific.net/amm.697.249.

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The design and debugging of motor control algorithm for electric drive tracked vehicle as the research object, this paper proposed a graphical model programming method of the code directly generated based on vector control algorithm model of the permanent magnet synchronous motor created in Matlab/Simulink. After simulation analysis and verification, this paper using real time toolbox automatically generated the embedded C code and implemented a processor in the loop test. The test results show that the longest running time of the control algorithm was 7.1633μs, between code and algorithm model, had high functional equivalence .This programming method is simple and intuitive, easy debugging, stable operation, and provides an effective way for motor drive system software development of electric drive tracked vehicle.

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Wang, Yihua, Qing Zhou, Yu Zhang, Xian Zhang et Jiahao Du. « A Formal Modeling and Verification Scheme with an RNN-Based Attacker for CAN Communication System Authenticity ». Electronics 11, n^o 11 (2 juin 2022) : 1773. http://dx.doi.org/10.3390/electronics11111773.

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To enhance the attack resistance of the Controller Area Network (CAN) system and optimize the communication software design, a comprehensive model that combines a variable attacker with the CAN bus (VACB) is proposed to evaluate the bus communication risk. The VACB model consists of a variable attacker and the CAN bus model. A variable attacker is a visualized generation of the attack traffic based on a recurrent neural network (RNN), which is used to evaluate the anti-attack performance of the CAN bus; the CAN bus model combines the data link layer and the application layer to analyze the anomalies in CAN bus data transmission after the attack message. The simulation results indicate that the transmission accuracy and successful response rate decreased by 1.8% and 4.3% under the constructed variable attacker. The CAN bus’s authenticity was promoted after the developers adopted this model to analyze and optimize the software design. The transmission accuracy and the successful response rate were improved by 2.5% and 5.1%, respectively. Moreover, the model can quantify the risk of potential attacks on the CAN bus, prompting developers to avoid it in early development to reduce the loss caused by system crashes. The comprehensive model can provide theoretical guidance for the timing design of embedded software.

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Martin, Grant. « A career in system-level design research [review of "Embedded System Design : Modeling, Synthesis, and Verification (Gajski, D.D. et al ; 2009) ». IEEE Design & ; Test of Computers 27, n^o 2 (mars 2010) : 82–83. http://dx.doi.org/10.1109/mdt.2010.33.

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Lopac, Nikola, Gordan Šegon et Neven Bulić. « Application of model-based design tool X2C in induction machine vector control ». Engineering review 39, n^o 1 (2019) : 90–104. http://dx.doi.org/10.30765/er.39.1.10.

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Open source software tools for model-based design of embedded control systems represent a new method for rapid development and testing of advanced control structures in modern electric drives. The new concept of one of those tools, X2C, is presented in this paper, and in order to evaluate its performance in the development of complex control systems, it is applied to implement induction machine vector control. Based on the simulation model of the drive developed in PLECS, the parameters of the controllers were determined. The algorithm for the vector control of the induction machine was developed in X2C, implemented on the digital signal processor and applied to the real system. The system was tested during the no-load acceleration, deceleration, and reversing of the motor, while measuring the electrical and mechanical variables. Finally, the quantitative comparison of the experimental results and the results obtained by the equivalent simulations, based on the Integral Squared Error criterion, revealed that these results were well matched. This finding suggested that the control system was successfully implemented, thereby confirming the effectiveness of X2C tool in this particular type of application. With this work it has been shown that a transition from simulation to actual environment is rapidly achieved, with a simple verification of implemented methods accompanying the process. Realization of this work is a step forward in the utilization of open source software packages for implementation of induction machine vector control with the purpose of rapid verification of simulation models.

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Alekhin, V. A. « Designing Electronic Systems Using SystemC and SystemC–AMS ». Russian Technological Journal 8, n^o 4 (6 août 2020) : 79–95. http://dx.doi.org/10.32362/2500-316x-2020-8-4-79-95.

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Current trends in the design of electronic systems is the use of embedded systems based on systems on a chip (System-on-Chip (SoC)) or (VLSI SoC). The paper discusses the design features of electronic systems on a chip using the SystemC design and verification language. For the joint design and simulation of digital systems hardware and software, seven modeling levels are presented and discussed: executable specification, disabled functional model, temporary functional model, transaction-level model, behavioral hardware model, accurate hardware model, register transfer model. The SystemC design methodology with functional verification is presented, which reduces development time.The architecture of the SystemC language and its main components are shown. The expansion of SystemC–AMS for analog and mixed analog-digital signals and its use cases in the design of electronic systems are considered. Computing models are discussed: temporary data stream (TDF), linear signal stream (LSF) and electric linear networks (ELN). The architecture of the SystemC–AMS language standard is shown and examples of its application are given. It is shown that the design languages SystemC and SystemC–AMS are widely used by leading developers of computer-aided design systems for electronic devices.

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Yu, Huafeng, Abdoulaye Gamatié, Éric Rutten et Jean-Luc Dekeyser. « Adaptivity in high-performance embedded systems : a reactive control model for reliable and flexible design ». Knowledge Engineering Review 29, n^o 4 (septembre 2014) : 433–51. http://dx.doi.org/10.1017/s0269888914000150.

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AbstractSystem adaptivity is increasingly demanded in high-performance embedded systems, particularly in multimedia system-on-chip (SoC), owing to growing quality-of-service requirements. This paper presents a reactive control model that has been introduced in Gaspard, our framework dedicated to SoC hardware/software co-design. This model aims at expressing adaptivity as well as reconfigurability in systems performing data-intensive computations. It is generic enough to be used for description in the different parts of an embedded system, for example, specification of how different data-intensive algorithms can be chosen according to some computation modes at the functional level; and expression of how hardware components can be selected via the usage of a library of intellectual properties according to execution performances. The transformation of this model toward synchronous languages is also presented, in order to allow an automatic code generation usable for formal verification, based on techniques such as model checking and controller synthesis, as illustrated in the paper. This work, based on Model-Driven Engineering and the standard UML MARTE profile, has been implemented in Gaspard.

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Allender, Laurel, Troy D. Kelley, Lucia Salvi, John Lockett, Donald B. Headley, David Promisel, Diane Mitchell, Celine Richer et Theo Feng. « Verification, Validation, and Accreditation of a Soldier-System Modeling Tool ». Proceedings of the Human Factors and Ergonomics Society Annual Meeting 39, n^o 18 (octobre 1995) : 1219–23. http://dx.doi.org/10.1177/154193129503901815.

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Increasingly, system developers are relying on modeling and simulation to support early design decisions. In turn, to support effective, timely use of models and simulations, verification, validation, and, in some cases, accreditation (VV&A) are required. The soldier-system analysis tools collectively known as Hardware vs. Manpower (HARDMAN) III underwent a formal VV&A process, the first of its type in the Army. The first phase comprised the core task network modeling capability and the effects implemented as additions to or modifications of the task data–mental workload estimation and environmental degradation, personnel characteristics, and training. A review board of representative users, policy-makers, technical experts, and soldier proponents evaluated the findings against eight criteria–configuration management, software verification, documentation, data input requirements, model granularity, validity of modeling techniques and embedded algorithms, output, and analysis timelines. All criteria were satisfied and formal accreditation was granted with only limited caveats.

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STANCU, Florin-Adrian, Víctor Manuel MORENO VILLA, Carlos DOMÍNGUEZ SÁNCHEZ, Andrei Valentin PLAMADEALA et Daniel OVEJERO PROVENCIO. « Visual based GNC system from prototype to flight software ». INCAS BULLETIN 15, n^o 1 (7 mars 2023) : 97–106. http://dx.doi.org/10.13111/2066-8201.2023.15.1.9.

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Juventas is a 6U CubeSat which is part of HERA planetary defense mission and takes advantage of an innovative visual based guidance, navigation and control (GNC) system to perform autonomous navigation in the proximity of the Didymain system. The GNC system is designed to ensure safe navigation in the harsh and unpredictable environment of deep space and finally to take more risks by landing on the surface of Dimorphos. To achieve a qualitative software (SW) product, a dedicated procedure of SW lifecycle is developed by starting with GNC and image processing design, which concludes with the final embedded system that will perform the visual navigation task. A Design, Development, Verification and Validation (DDVV) approach is developed to achieve the flight software: model in the loop (MIL), auto-coding, software in the loop (SIL), processor in the loop (PIL) and finally hardware in the loop (HIL). The DDVV is developed by having as guideline the ECSS standards for SW. The flight software reaches maturity by performing dynamic/static code analysis and code coverage. To ensure an optimal process, a waterfall life-cycle is considered, where dedicated MIL, SIL, PIL and HIL test benches are developed to fully support the activity and to reduce to minimum the development costs.[7]

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Xiao, Yanjun, Linhan Shi, Wei Zhou, Feng Wan et Weiling Liu. « Application of embedded soft PLC in the control system of rapier loom ». PLOS ONE 16, n^o 9 (23 septembre 2021) : e0257629. http://dx.doi.org/10.1371/journal.pone.0257629.

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At present, the rapier loom has gradually become the mainstream equipment in the manufacturing industry. In order to make the rapier loom realize automated production and further improve the production efficiency of the rapier loom, improve the programmability of the system, and reduce the cost of system maintenance. The thesis developed a rapier loom control system based on embedded soft PLC, and carried out experiments and applications in the field. The contribution and innovation of this paper is to develop a complete low-cost control system, and through a genetic algorithm optimized PID algorithm to complete the more effective control of the loom tension system. The embedded soft PLC system proposed in this paper reduces the overall maintenance cost of the system and improves the programmability of the system. This text carries on the systematic scheme design to the embedded soft PLC from the hardware system and the software system respectively. First, according to the actual requirements, this article designs the overall scheme of the embedded software PLC hardware system with STM32F407ZGT6 as the core. Then this article is based on the embedded soft PLC hardware platform, according to the international standard of industrial control programming, writes the embedded soft PLC low-level driver software. Secondly, this article analyzes the factors that affect the warp tension during the operation of the rapier loom, and proposes the use of genetic algorithm to optimize the warp tension control method of the traditional PID algorithm. Finally, we conducted verification tests and on-site application debugging for the entire set of rapier loom embedded soft PLC control system. We controlled the warp tension as the main experimental object. The results show that this control system effectively improves the control accuracy of the warp tension of the rapier loom and meets the actual needs of industrial applications. The whole system has a good application prospect in the warp tension control of rapier looms.

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ILLARRAMENDI REZABAL, MIREN, ASIER IRIARTE, AITOR ARRIETA AGUERRI,, GOIURIA SAGARDUI MENDIETA et FELIX LARRINAGA BARRENECHEA. « DIGITAL SAFETY MANAGER : IOT SERVICE TO ASSURE THE SAFE BEHAVIOUR OF MACHINES AND CONTROLS IN THE DIGITAL INDUSTRY ». DYNA 97, n^o 1 (1 janvier 2022) : 18–22. http://dx.doi.org/10.6036/10243.

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The digital industry requires increasingly complex and reliable software systems. They need to control and make critical decisions at runtime. As a consequence, the verification and validation of these systems has become a major research challenge. At design and development time, model testing techniques are used while run-time verification aims at verifying that a system satisfies a given property. The latter technique complements the former. The solution presented in this paper targets embedded systems whose software components are designed by state machines defined by Unified Modelling Language (UML). The CRESCO (C++ REflective State-Machines based observable software COmponents) platform generates software components that provide internal information at runtime and the verifier uses this information to check system-level reliability/safety contracts. The verifier detects when a system contract is violated and initiates a safeState process to prevent dangerous scenarios. These contracts are defined by internal information from the software components that make up the system. Thus, as demonstrated in the tested experiment, the robustness of the system is increased. All software components (controllers), such as the verifier, have been deployed as services (producers/consumers) of the Arrowhead IoT platform: the controllers are deployed on local Arrowhead platforms (Edge) and the verifier (Safety Manager) is deployed on an Arrowhead platform (Cloud) that will consume controllers on the Edge and ensure the proper functioning of the plant controllers. Keywords: run-time monitoring, robustness, software components, contracts, software models, state machines

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Todorov, Vassil, Safouan Taha, Frederic Boulanger et Armando Hernandez. « Proving Properties of Discrete-Valued Functions Using Deductive Proof : Application to the Square Root ». Modeling and Analysis of Information Systems 26, n^o 4 (27 décembre 2019) : 520–33. http://dx.doi.org/10.18255/1818-1015-2019-4-520-533.

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For many years, automotive embedded systems have been validated only by testing. In the near future, Advanced Driver Assistance Systems (ADAS) will take a greater part in the car’s software design and development. Furthermore, their increasing critical level may lead authorities to require a certification for those systems. We think that bringing formal proof in their development can help establishing safety properties and get an efficient certification process. Other industries (e.g. aerospace, railway, nuclear) that produce critical systems requiring certification also took the path of formal verification techniques. One of these techniques is deductive proof. It can give a higher level of confidence in proving critical safety properties and even avoid unit testing.In this paper, we chose a production use case: a function calculating a square root by linear interpolation. We use deductive proof to prove its correctness and show the limitations we encountered with the off-the-shelf tools. We propose approaches to overcome some limitations of these tools and succeed with the proof. These approaches can be applied to similar problems, which are frequent in the automotive embedded software.

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MO, YUCHANG, et XINMIN YANG. « A NEW APPROACH TO VERIFY STATECHART SPECIFICATIONS FOR REACTIVE SYSTEMS ». International Journal of Software Engineering and Knowledge Engineering 18, n^o 06 (septembre 2008) : 785–802. http://dx.doi.org/10.1142/s0218194008003908.

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The application domain, such as communication networks and embedded controllers for telephony, automobiles, trains and avionics systems, requires very high quality reactive systems, so an important phase in the development of reactive systems is the verification of their conceptual models before implementation. Normally in the requirement analysis phase, system property can be represented as an input and output labeled transition system (IOLTS), which is a transition system labeled by inputs and outputs between the system and the environment. This paper describes an attempt to propose an approach to verify Statechart specifications for reactive systems given IOLTS property specifications. We develop a suitable semantics model — observable semantics, an abstract semantics model only which describes outside observable behavior and suffers from less state explosion problem by reducing infinite or large state spaces to small ones. Then we propose two methods to verify the conformance between a given IOLTS property specification and a Statechart specification: two-phase verification and on-the-fly verification. Compared with two-phase verification, on-the-fly verification needs less storage and computation-time, especially when the target Statechart specification is very large or likely to have many errors.

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Dubey, Awanish Chandra, et Anantha V. Subramanian. « Hardware in the Loop Simulation and Control Design for Autonomous Free Running Ship Models ». Defence Science Journal 70, n^o 4 (13 juillet 2020) : 469–76. http://dx.doi.org/10.14429/dsj.70.14926.

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This paper presents an hardware-in-the-loop (HIL) simulation system tool to test and validate an autonomous free running model system for ship hydrodynamic studies with a view to verification of the code, the control logic and system peripherals. The computer simulation of the plant model in real-time computer does not require the actual physical system and reduces the development cost and time for control design and testing purposes. The HIL system includes: the actual programmable embedded controller along with peripherals and a plant model virtually simulated in a real-time computer. With regard to ship controller design for ship model testing, this study describes a plant model for surge and a Nomoto first order steering dynamics, both implemented using Simulink software suit. The surge model captures a quasi-steady state relationship between surge speed and the propeller rpms, obtained from simple forward speed towing tank tests or derived analytically. The Nomoto first order steering dynamics is obtained by performing the standard turning circle test at model scale. The control logic obtained is embedded in a NI-cRIO based controller. The surge and steering dynamics models are used to design a proportional-derivative controller and an LQR controller. The controller runs a Linux based real-time operating system programmed using LabVIEW software. The HIL simulation tool allows for the emulation of standard ship hydrodynamic tests consisting of straight line, turning circle and zigzag to validate the combined system performance, prior to actual for use in the autonomous free-running tests.

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Tomičić, Branko, Antonija Šumiga, Josip Nađ et Dunja Srpak. « Verification Methodology for Simulation Models of the Synchronous Generator on Transients Analysis ». Applied Sciences 11, n^o 24 (10 décembre 2021) : 11734. http://dx.doi.org/10.3390/app112411734.

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During transients that occur in an electric network, large currents can flow and large electromagnetic torques can be developed in electric generators. Accurate calculation of currents and magnetic fields during transients is an important element in the optimal design of generators and network parts, as well as mechanical parts of machines and other torque transmission parts. This paper describes the modeling of a sudden three-phase short-circuit on a synchronous generator using the finite element method (FEM) and the dynamic model. The model for simulations that use the FEM was built in the MagNet software package, and the dynamic model is embedded in the MATLAB/Simulink software package. The dynamic simulation model of a part of a network with two identical generators, represented by equivalent parameters, was developed. The results obtained after the simulation of a sudden three-phase fault in the generators by both methods are presented, including three-phase voltages, three-phase currents, machine speeds, excitation voltages, and mechanical power. In particular, the short-circuit current in the phase with the highest peak value was analyzed to determine the accuracy of the equivalent parameters used in the dynamic model. Finally, the results of these two calculation methods are compared, and recommendations are presented for the application of different modeling methods.

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Osman, Nafisa, et Abd-Elkader Sahraoui. « Modeling and Verification of ERP Functional Requirements based on Colored Petri Net ». International Journal of Software Engineering & ; Applications 12, n^o 3 (31 mai 2021) : 27–43. http://dx.doi.org/10.5121/ijsea.2021.12303.

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The rise of enterprise resource planning (ERP) systems has been a major event in the software industry and it became a solution for most enterprises to manage their data and business processes. Successful ERP implementations can reduce costs by improving efficiency then lead to improved company performance and better competitive edge. Despite these benefits and the age of ERP existing for several decades still high percentage of implementation failures are documented. ERP is packaged software designed by following the best practice from the specific industry to support typical business processes in the entire industrial field, it was designed by ERP vendors and used by the organization which implement it. Since the designer and user are two independent entity misalignments between user’s needs and the software design are often happen. The misalignment define new specific requirements must be embedded into selected ERP. Requirement engineering (RE) is a main part and initial activity of software engineering concern about defines stakeholder requirements, needs and desire. Requirements engineering is the basis for efficient software implementation and quality management. Tools and theories which support RE in general are numerous nowadays; however, the task of providing a tools and theories that specializes in Requirements engineering for Enterprise resource planning systems has been addressed rarely. For that; this paper discusses modelling and verification of ERP functional requirements based on colored Petri nets (CPN) after evaluation of different Business process modelling techniques by using analytical hierarchy process (AHP). CPN considered one of powerful business process modelling techniques and using it help in stakeholder involvement and appropriate organization’s business process representation. The nature of colored Petri nets that help in verification of internal completeness and consistency of ERP functional requirements model.

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Wu, Yu En, et Kuo Chan Huang. « Design and Implementation of Dual-Axis Solar Tracking System with GSM Fault Reporting Capability ». Advanced Materials Research 724-725 (août 2013) : 43–51. http://dx.doi.org/10.4028/www.scientific.net/amr.724-725.43.

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This paper presents a smart dual-axis solar tracking system, its architecture includes sensors, embedded controllers, AC motors, Integrated electric putter design biaxial institutions, and the GSM automatic report of fault notification, to achieve autonomous tracking solar track system and adjust the solar panels to reach the maximum smooth by tracking the solar azimuth angle and elevation angle, and ensure that the solar panels with the sun to maintain the vertical in any time and any place, thus achieving the best power efficiency. This system proposed a dual-axis design, and an embedded controller used as the main system controller to detect voltage difference and determine the solar azimuth angle with four groups of CDS as a sensing element. To lock the sun, the solar panels be perpendicular via the moving of AC motor (EW) and motorized faders (north-south). The control system software using C language can be extremely fast and accurate tracking of the solar angle, and dual-axis operation with recovery mode to save the power loss. Finally, we have the actual analysis and verification of benefit of power generation in this paper, from this experimental results, we can verify the integration of build dual-axis solar tracking system and solar power system have promoted 30% generating power capacity more than fixed solar power system and has low failure rate. It can improve the problem of traditional tracking system reliability and greatly enhance the usefulness of this system.

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STUART, DOUGLAS A., ALOYSIUS K. MOK et FARNAM JAHANIAN. « A METHODOLOGY AND SUPPORT TOOLS FOR ANALYSIS OF REAL-TIME SPECIFICATIONS ». International Journal of Software Engineering and Knowledge Engineering 06, n^o 03 (septembre 1996) : 401–26. http://dx.doi.org/10.1142/s021819409600017x.

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As software control of time-critical functions in embedded systems becomes more common, a means for the precise specification of their behavior and formal methods for analyzing system requirements become increasingly important. Modechart is a graphical specification language introduced to meet this need. The main focus of this paper is on methods and supporting tools for representing and reasoning about properties of time-critical systems specified in Modechart. The paper describes a verification methodology which takes advantage of the structuring inherent in a Modechart specification to determine whether a system specification satisfies the required properties. The paper also describes the implementation of a mechanical verifier, based on the proposed approach, which has been recently integrated as part of the Modechart Toolset prototype development environment from the Naval Research Lab [7].

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Wu, Jun Hui, Quan Zhou, Jie Chen, Hui Ping Si et Chi Bin Zhang. « Structural Design for Dynamic Roller Device in Transporting Unit of Biomass Pyrolytic System ». Applied Mechanics and Materials 157-158 (février 2012) : 361–66. http://dx.doi.org/10.4028/www.scientific.net/amm.157-158.361.

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With the full study of industrial process control technology for thermal, chemical industry, the application process, the FCS system of biomass pyrolysis unit was development combined with the actual. Feeding system uses the weighing system of dynamic belt with an advanced embedded technology. The computing speed and accuracy, data processing compared with traditional electronic belt scale, information exchange, integration, reliability and stability will be greatly improved. The technology shall be constantly upgraded and vigorously promoted. The frame structures of dynamic roller were various in forms. Different systems can be used to the frame with different scale structures. The suspension of multi-scale frame of the roller was used widely currently. The modeling and structural optimization of the frames in reasonable scale were designed with reducing the use of metal materials, optimizing the overall performance of mechanical systems and improving the weighing accuracy. The analysis of dynamic roller in scale weighing and speed principle, the establishment of a multi-roller single floating frame structure of the scale model and the analysis of the roller of the force were built. The verification in final design through the ANSYS software is reasonable.

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Dupont, Guillaume, Yamine Ait-Ameur, Neeraj Kumar Singh et Marc Pantel. « Event-B Hybridation ». ACM Transactions on Embedded Computing Systems 20, n^o 4 (juin 2021) : 1–37. http://dx.doi.org/10.1145/3448270.

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Hybrid systems are complex systems where a software controller interacts with a physical environment, usually named a plant, through sensors and actuators. The specification and design of such systems usually rely on the description of both continuous and discrete behaviours. From complex embedded systems to autonomous vehicles, these systems became quite common, including in safety critical domains. However, their formal verification and validation as a whole is still a challenge. To address this challenge, this article contributes to the definition of a reusable and tool supported formal framework handling the design and verification of hybrid system models that integrate both discrete (the controller part) and continuous (the plant part) behaviours. This framework includes the development of a process for defining a class of basic theories and developing domain theories and then the use of these theories to develop a generic model and system-specific models. To realise this framework, we present a formal proof tool chain, based on the Event-B correct-by-construction method and its integrated development environment Rodin, to develop a set of theories, a generic model, proof processes, and the required properties for designing hybrid systems in Event-B. Our approach relies on hybrid automata as basic models for such systems. Discrete and continuous variables model system states and behaviours are given using discrete state changes and continuous evolution following a differential equation. The proposed approach is based on refinement and proof using the Event-B method and the Rodin toolset. Two case studies borrowed from the literature are used to illustrate our approach. An assessment of the proposed approach is provided for evaluating its extensibility, effectiveness, scalability, and usability.

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