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Thèses sur le sujet « Efficient implementation for HBVM »

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Publié le 10 mars 2023

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1

King, Myron Decker. "An efficient sequential BTRS implementation." Thesis, Massachusetts Institute of Technology, 2009. http://hdl.handle.net/1721.1/46603.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.<br>Includes bibliographical references (leaves 73-74).<br>This thesis describes the implementation of BTRS, a language based on guarded atomic actions (GAA). The input language to the compiler which forms the basis of this work is a hierarchical tree of modules containing state, interface methods, and rules which fire atomically to cause state transitions. Since a schedule need not be specified, the program description is inherently nondeterministic, though the BTRS language does a

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Patel, Nirav B. "Voronoi diagrams robust and efficient implementation /." Diss., Online access via UMI:, 2005.

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Stenman, Erik. "Efficient Implementation of Concurrent Programming Languages." Doctoral thesis, Uppsala University, Department of Information Technology, 2002. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-2688.

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<p>Dissertation in Computer Science to be publicly examined in Häggsalen, Ångströmlaboratoriet, Uppsala University, on Friday, November 1, 2002 at 1:00 pm for the degree of doctor of philosophy. The examination will be conducted in English. </p><p>This thesis proposes and experimentally evaluates techniques for efficient implementation of languages designed for high availability concurrent systems. This experimental evaluation has been done while developing the High Performance Erlang (HiPE) system, a native code compiler for SPARC and x86. The two main goals of the HiPE system are to provide

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ALVES, ROGERIO GUEDES. "EFFICIENT MULTI-RATE SYSTEM IMPLEMENTATION FORMS." PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO, 1993. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=8692@1.

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COORDENAÇÃO DE APERFEIÇOAMENTO DO PESSOAL DE ENSINO SUPERIOR<br>Inicialmente apresenta-se a estrutura de um sistema Multi- taxa, faz-se uma revisão teórica do mesmo, e descreve-se seu funcionamento. Posteriormente são apresentadas várias formas de implementar este sistema, como realizá-lo no domínio do tempo, parte no domínio do tempo e parte no domínio da freqüência e realizá-lo no domínio da freqüência. Nestas formas de implementação são considerados fatores como: emprego da técnica de overlap- save ou overlap-add para realização da convolução a ser implementada no sistema, e utiliz

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Mahdi, Abdul-Hussain Ebrahim. "Efficient generalized transform algorithms for digital implementation." Thesis, Bangor University, 1990. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.277612.

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Wojtczak, Dominik. "Recursive probabilistic models : efficient analysis and implementation." Thesis, University of Edinburgh, 2009. http://hdl.handle.net/1842/3217.

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This thesis examines Recursive Markov Chains (RMCs), their natural extensions and connection to other models. RMCs can model in a natural way probabilistic procedural programs and other systems that involve recursion and probability. An RMC is a set of ordinary finite state Markov Chains that are allowed to call each other recursively and it describes a potentially infinite, but countable, state ordinary Markov Chain. RMCs generalize in a precise sense several well studied probabilistic models in other domains such as natural language processing (Stochastic Context-Free Grammars), population d

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Taylor, David Eirik. "Efficient Implementation of Cross-Correlation in Hardware." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2014. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-25839.

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Low-area matched filter and correlator designs are explored in this thesis, for ADC resolutions of 1- and 2-bits. Correlators are used extensively in spread-spectrum communication technologies, where they serve as a means of detecting a known pseudo-random sequence (PN code). The correlator designs presented here are intended for direct-sequence spread spectrum (DSSS) radio, where the data to be sent is expanded using either the PN code, or the inverse of the PN code. The correlator or matched filter will then respond with a positive or negative peak when a data bit is detected.To test various

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Abdoel-Gawad, Farag Saleh. "Efficient hardware implementation of the CORDIC algorithm." Thesis, Liverpool John Moores University, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299066.

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Fan, Yanan. "Efficient implementation of Markov chain Monte Carlo." Thesis, University of Bristol, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.343307.

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Jerez, Juan Luis. "Custom optimization algorithms for efficient hardware implementation." Thesis, Imperial College London, 2013. http://hdl.handle.net/10044/1/12791.

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The focus is on real-time optimal decision making with application in advanced control systems. These computationally intensive schemes, which involve the repeated solution of (convex) optimization problems within a sampling interval, require more efficient computational methods than currently available for extending their application to highly dynamical systems and setups with resource-constrained embedded computing platforms. A range of techniques are proposed to exploit synergies between digital hardware, numerical analysis and algorithm design. These techniques build on top of parameterisa

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Sustarsic, Alissa Michele. "An Efficient Implementation of the Transportation Problem." UNF Digital Commons, 1999. http://digitalcommons.unf.edu/etd/81.

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The transportation problem is a special type of linear program in which the objective is to minimize the total cost of shipping a single commodity from a number of sources (m) to a number of destinations or sinks (n). Because of the special structure of the transportation problem, a special algorithm can be designed to find an optimal solution efficiently. Due to the large amount of information in the problem, judicious storage and management of the data are essential requirements of any viable implementation of the transportation algorithm. Using sparse matrix techniques to store the solution

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Nau, Lee J. "A Scalable, Memory Efficient Multicore TEIRESIAS Implementation." Ohio University / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1306856233.

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Ulis, Bradley J. "Stereo image correspondence methods for efficient hardware implementation." Thesis, Monterey, California : Naval Postgraduate School, 2010. http://edocs.nps.edu/npspubs/scholarly/theses/2010/Jun/10Jun%5FUlis.pdf.

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Thesis (M.S. in Electrical Engineering)--Naval Postgraduate School, June 2010.<br>Thesis Advisor(s): Cristi, Roberto ; Second Reader: Fargues, Monique P. "June 2010." Description based on title screen as viewed on July 14, 2010. Author(s) subject terms: Stereo Correspondence, Ordinal Measures, 3D Reconstruction, Dynamic Programming. Includes bibliographical references (p. 75-77). Also available in print.

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Johansson, John. "Efficient implementation of the Particle Level Set method." Thesis, Linköping University, Media and Information Technology, 2010. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-59579.

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<p>The Particle Level set method is a successful extension to Level set methods to improve thevolume preservation in fluid simulations. This thesis will analyze how sparse volume data structures can be used to store both the signed distance function and the particles in order to improve access speed and memory efficiency. This Particle Level set implementation will be evaluated against Digital Domains current Particle Level set implementation. Different degrees of quantization will be used to implement particle representations with varying accuracy. These particles will be tested and both visu

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Sims, Oliver. "Efficient implementation of video processing algorithms on FPGA." Thesis, University of Glasgow, 2007. http://theses.gla.ac.uk/4119/.

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The work contained in this portfolio thesis was carried out as part of an Engineering Doctorate (Eng.D) programme from the Institute for System Level Integration. The work was sponsored by Thales Optronics, and focuses on issues surrounding the implementation of video processing algorithms on field programmable gate arrays (FPGA). A description is given of FPGA technology and the currently dominant methods of designing and verifying firmware. The problems of translating a description of behaviour into one of structure are discussed, and some of the latest methodologies for tackling this proble

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Wei, Dennis. "Design of discrete-time filters for efficient implementation." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/66470.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 325-333).<br>The cost of implementation of discrete-time filters is often strongly dependent on the number of non-zero filter coefficients or the precision with which the coefficients are represented. This thesis addresses the design of sparse and bit-efficient filters under different constraints on filter performance in the context of frequency response approximation, signal estimation, and signa

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Honorato, Mauro Jacob. "Wam based space efficient Prolog implementation in Lisp." Universidade Federal de Uberlândia, 2015. https://repositorio.ufu.br/handle/123456789/17800.

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Esse trabalho propõe a implementação de um sistema Prolog eficiente no espaço, o mesmo é baseado nos trabalhos de David H. D. Warren e Hassan Aït-Kaci. A Common Lisp é a estrutura usada para a construção do sistema Prolog, ela foi escolhida tanto por fornecer um ambiente eficiente no espaço quando por ser uma linguagem de programação rica no sentido de que fornece ao usuário abstrações e novas maneiras de pensar. O sistema resultante consiste em uma nova sintaxe aplicada à linguagem inicial que funciona sobre a implementanção Common Lisp chamada SBCL e é capaz de abstrair ou explorar o sistema

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Shuvo, Md Kamruzzaman. "Hardware Efficient Deep Neural Network Implementation on FPGA." OpenSIUC, 2020. https://opensiuc.lib.siu.edu/theses/2792.

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In recent years, there has been a significant push to implement Deep Neural Networks (DNNs) on edge devices, which requires power and hardware efficient circuits to carry out the intensive matrix-vector multiplication (MVM) operations. This work presents hardware efficient MVM implementation techniques using bit-serial arithmetic and a novel MSB first computation circuit. The proposed designs take advantage of the pre-trained network weight parameters, which are already known in the design stage. Thus, the partial computation results can be pre-computed and stored into look-up tables. Then the

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Addluri, Ramya Krishna. "An Efficient Implementation of the Blowfish Encryption Algorithm." University of Cincinnati / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1406820252.

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Smith, Craig M. "Efficient software implementation of the JBIG compression standard /." Online version of thesis, 1993. http://hdl.handle.net/1850/11713.

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Turkyilmaz, Ogun. "Emerging 3D technologies for efficient implementation of FPGAs." Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENT091/document.

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La complexité croissante des systèmes numériques amène les architectures reconfigurable telles que les Field Programmable Gate Arrays (FPGA) à être très fortement demandés en raison de leur facilité de (re)programmabilité et de leurs faibles coûts non récurrents (NRE). La re-configurabilité est réalisée grâce à de nombreux point mémoires de configuration. Cette re-configurabilité se traduit par une extrême flexibilité des applications implémentées et dans le même temps par une perte en surface, en performances et en puissance par rapport à des circuits intégrés spécifiques (ASIC) pour la même

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Lewis, Gregory Paul. "Repeated Reading: Testing Alternative Models for Efficient Implementation." DigitalCommons@USU, 2012. https://digitalcommons.usu.edu/etd/1171.

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Repeated reading has been used for over 30 years. In the publication of the National Reading Panel Report, repeated reading was listed as an effective strategy for developing fluency. Yet, repeated reading’s efficacy has been recently questioned. Understanding the “how-to” of efficiently using evidence-based practices would allow teachers to deliver successful, time-sensitive instruction and intervention to students. This study was based on two research questions. First was a gain score (increase between a student’s first read and their final repeated reading), a better model and therefore a b

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Axell, Christian, and Mikael Brogsten. "Efficient WiMAX Receiver Implementation on a Programmable Baseband Processor." Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7684.

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<p>WiMAX provides broadband wireless access and uses OFDM as the underlying modulation technique. In an OFDM based wireless communication system, the channel will distort the transmitted signal and the performance is seriously degraded by synchronization mismatches between the transmitter and receiver. Therefore such systems require extensive digital signal processing of the received signal for retrieval of the transmitted information.</p><p>In this master thesis, parts of an IEEE 802.16d (WiMAX) receiver have been implemented on a programmable baseband processor. The implemented parts constit

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Olgun, Muhammet Ertug. "Design And Fpga Implementation Of An Efficient Deinterleaving Algorithm." Master's thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/3/12609816/index.pdf.

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In this work, a new deinterleaving algorithm that can be used as a part of an ESM system and its implementation by using an FPGA is studied. The function of the implemented algorithm is interpreting the complex electromagnetic military field in order to detect and determine different RADARs and their types by using incoming RADAR pulses and their PDWs. It is assumed that RADAR signals in the space are received clearly and PDW of each pulse is generated as an input to the implemented algorithm system. Clustering analysis and a new interpreting process is used to deinterleave the RADAR pulses. I

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Gunay, Hazan. "Efficient Fpga Implementation Of Image Enhancement Using Video Streams." Master's thesis, METU, 2010. http://etd.lib.metu.edu.tr/upload/12611448/index.pdf.

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This thesis is composed of three main parts<br>displaying an analog composite video input by via converting to digital VGA format, license plate localization on a video image and image enhancement on FPGA. Analog composite video input, either PAL or NTSC is decoded on a video decoder board<br>then on FPGA, video data is converted from 4:2:2 YCbCr format to RGB. To display RGB data on the screen, line doubling de-interlacing algorithm is used since it is efficient considering computational complexity and timing. When taking timing efficiency into account, image enhancement is applied only to be

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Li, Zhipeng Ph D. Massachusetts Institute of Technology. "Efficient baseband design and implementation for high-throughput transmitters." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/101465.

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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.<br>This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.<br>Cataloged from student-submitted PDF version of thesis.<br>Includes bibliographical references (pages 139-145).<br>Wireless communications are accelerating into the realm of higher data rates from hundreds of megabits to tens of gigabits per second. Increase in data rate requires higher throughput and higher utilization of sp

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Alam, Syed Asad. "Techniques for Efficient Implementation of FIR and Particle Filtering." Doctoral thesis, Linköpings universitet, Datorteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-124195.

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FIR filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to IIR filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large

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Hosseini, Ehsan, and Gino Rea. "Hardware-Efficient Implementation of the SOVA for SOQPSK-TG." International Foundation for Telemetering, 2010. http://hdl.handle.net/10150/605932.

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ITC/USA 2010 Conference Proceedings / The Forty-Sixth Annual International Telemetering Conference and Technical Exhibition / October 25-28, 2010 / Town and Country Resort & Convention Center, San Diego, California<br>In this paper, we present a hardware-efficient architecture of a demodulator for shaped offset quadrature phase shift keying, telemetry group version (SOQPSK-TG). The demodulation is done using the soft-output Viterbi algorithm (SOVA), which is implemented by the two-step traceback method. In this method, two traceback operations are employed to find the maximum-likelihood (ML) p

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Maze, Sheldon. "Efficient implementation of the Heston-Hull & White model." Master's thesis, University of Cape Town, 2014. http://hdl.handle.net/11427/8521.

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Includes bibliographical references.<br>A model with a stochastic interest rate process correlated to a stochastic volatility process is needed to accurately price long- dated contingent claims. Such a model should also price claims efficiently in order to allow for fast calibration. This dissertation explores the approximations for the characteristic function of the Heston-Hull&White model introduced by Grzelak and Oost- erlee (2011). Fourier-Cosine expansion pricing, due to Fang and Oosterlee (2008), is then used to price contingent claims under this model, which is implemented in MATLAB. We

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Lien, E.-Jen. "EFFICIENT IMPLEMENTATION OF ELLIPTIC CURVE CRYPTOGRAPHY IN RECONFIGURABLE HARDWARE." Case Western Reserve University School of Graduate Studies / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=case1333761904.

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Christman, Jordan Louis. "Efficient Digital Spotlighting Phase History Re-Centering Hardware Implementation." University of Dayton / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1480934083897465.

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Heyne, Benjamin. "Efficient CORDIC based implementation of selected signal processing algorithms." Aachen Shaker, 2008. http://d-nb.info/991790073/04.

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Alexander, Steven Wilson. "Efficient arithmetic for high speed DSP implementation on FPGAs." Thesis, Connect to e-thesis, 2007. http://theses.gla.ac.uk/856/.

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Thesis (Eng.D.) - University of Glasgow, 2007.<br>Eng.D. thesis submitted to the Faculty of Engineering, Department of Civil Engineering, University of Glasgow, 2007. Includes bibliographical references. Print version also available.

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Bak, Christopher. "GP 2 : efficient implementation of a graph programming language." Thesis, University of York, 2015. http://etheses.whiterose.ac.uk/12586/.

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The graph programming language GP (Graph Programs) 2 and its implementation is the subject of this thesis. The language allows programmers to write visual graph programs at a high level of abstraction, bringing the task of solving graph-based problems to an environment in which the user feels comfortable and secure. Implementing graph programs presents two main challenges. The first challenge is translating programs from a high-level source code representation to executable code, which involves bridging the gap from a non-deterministic program to deterministic machine code. The second challeng

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Katreepalli, Raghava. "Efficient VLSI Implementation of Arithmetic Units and Logic Circuits." OpenSIUC, 2017. https://opensiuc.lib.siu.edu/dissertations/1471.

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Arithmetic units and logic circuits are critical components of any VLSI system. Thus realizing efficient arithmetic units and logic circuits is required for better performance of a data path unit and therefore microprocessor or digital signal processor (DSP). Adders are basic building blocks of any processor or data path application. For the design of high performance processing units, high-speed adders with low power consumption is a requirement. Carry Select Adder (CSA) is known to be one of the fastest adders used in many data processing applications. This first contribution of the disser

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Nurrito, Eugenio. "Scattering networks: efficient 2D implementation and application to melanoma classification." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2016. http://amslaurea.unibo.it/12261/.

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Machine learning is an approach to solving complex tasks. Its adoption is growing steadily and the several research works active on the field are publishing new interesting results regularly. In this work, the scattering network representation is used to transform raw images in a set of features convenient to be used in an image classification task, a fundamental machine learning application. This representation is invariant to translations and stable to small deformations. Moreover, it does not need any sort of training, since its parameters are fixed and only some hyper-parameters must be d

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Larsson, Fredrik. "Efficient implementation of model-checkers for networks of timed automata." Licentiate thesis, Uppsala universitet, Avdelningen för datorteknik, 2000. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-226511.

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Since real-time systems often operate in safety-critical environments it is extremely important that they function correctly. UPPAAL is a tool that can be used for validation and verification of real-time systems. The user models the system using networks of timed automata and uses a simple logic to express safety requirements that the modelled system must satisfy to guarantee its correct behaviour. UPPAAL then performs reachability analysis using constraint solving techniques to check if the model satisfies the given requirements. In addition, the tool is also able to provide the user with a

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Bengtsson, Johan. "Efficient symbolic state exploration of timed systems : Theory and implementation." Licentiate thesis, Uppsala universitet, Avdelningen för datorteknik, 2001. http://urn.kb.se/resolve?urn=urn:nbn:se:uu:diva-86016.

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Timing aspects are important for the correctness of safety-critical systems. It is crucial that these aspects are carefully analysed in designing such systems. UPPAAL is a tool designed to automate the analysis process. In UPPAAL, a system under construction is described as a network of timed automata and the desired properties of the system can be specified using a query language. Then UPPAAL can be used to explore the state space of the system description to search for states violating (or satisfying) the properties. If such states are found, the tool provides diagnostic information, in form

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Kwok, Hok-sum, and 郭學深. "The implementation of energy efficient strategies in Hong Kong buildings." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2001. http://hub.hku.hk/bib/B31254925.

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Intrachooto, Singh. "Technological innovation in architecture : effective practices for energy efficient implementation." Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/8513.

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Thesis (Ph.D.)--Massachusetts Institute of Technology, Dept. of Architecture, 2002.<br>Some ill. printed as leaves, numbered as pages, and folded.<br>Includes bibliographical references (p. 241-248).<br>The objective of this research is to simultaneously address the environmental concerns in building design and the urgency in the architectural, engineering, and construction industry (AEC) to advance technologically by providing specific responses to the following questions. What are the barriers that a design team faces when introducing environmental strategies and innovations into building pr

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Li, Tiancheng. "Efficient particle implementation of Bayesian and probability hypothesis density filtering." Thesis, London South Bank University, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.631738.

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Using a set of samples that are associated with weights (namely the particle method) to represent the distribution of interest for filtering under very general hypotheses (often referred to as the sequential Monte Carlo, SMC approaches or particle filters) has gained high attention in the last two decades. However, the particle method suffers from problems such as sample depletion, huge computational time and challenges raised in multi-target tracking (MTT). Aiming to address these problems and challenges, this thesis investigates efficient particle filtering from two perspectives that deal wi

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FRASCA, CACCIA GIANLUCA. "A new efficient implementation for HBVMs and their application to the semilinear wave equation." Doctoral thesis, 2015. http://hdl.handle.net/2158/992629.

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In this thesis we have provided a detailed description of the low-rank Runge-Kutta family of Hamiltonian Boundary Value Methods (HBVMs) for the numerical solution of Hamiltonian problems. In particular, we have studied in detail their main property: the conservation of polynomial Hamiltonians, which results into a practical conservation for generic suitably regular Hamiltonians. This property turns out to play a fundamental role in some problems where the error on the Hamiltonian, usually obtained even when using a symplectic method, would be not negligible to the point of affecting the dynami

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Li, Yu-Lun, and 李有倫. "Efficient implementation of MP3 decoder." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/65766481241115154755.

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碩士<br>國立中正大學<br>資訊工程研究所<br>90<br>The Moving Picture Experts Group-1 / Layer3（MP3）algorithm on software application becomes more and more great. Therefore, to use hardware to implement MP3 obviously become a new field of course. In decoder section, because it needs to match the standard of real-time which makes it even better to present it by hardware. The objective for this thesis is to implement MP3 decoder by using hardware. Moreover, we decide to use Field Programmable Gate Array〈FPGA〉as for our design environment. We use software to do MP3 decode, because it is easier on calculation. Ther

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Wang, Guo-Ting, and 王國婷. "Efficient Implementation of FIDO UAF Client." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/22680485274516945129.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>104<br>With the popularity of mobile phones and tablets, more and more people surf the Internet with mobile devices. When users log in a website, in contrast to using traditional PCs, typing the password is very troublesome on mobile phones. However, the most commonly used authentication is still password-based. Thus, users usually record their password on browsers or apps after the first login. These security issues become apparent on mobile devices. Apart from using ”password”, there are several authentication solutions with higher security. For example, adding on

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Lu, Yi-shan, and 呂易珊. "Efficient Implementation of the Weil Pairing." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/q6664b.

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碩士<br>國立中山大學<br>資訊工程學系研究所<br>97<br>The most efficient algorithm for solving the elliptic curve discrete logarithm problem can only be done in exponential time. Hence, we can use it in many cryptographic applications. Weil pairing is a mapping which maps a pair of points on elliptic curves to a multiplicative group of a finite field with nondegeneracy and bilinearity. Pairing was found to reduce the elliptic curve discrete logarithm problem into the discrete logarithm problem of a finite field, and became an important issue since then. In 1986, Miller proposed an efficient algorithm for computi

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Pahlevaninezhad, Hamid. "Design and implementation of efficient terahertz waveguides." Thesis, 2012. http://hdl.handle.net/1828/3977.

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In this thesis, novel broadband waveguides capable of operating at terahertz (THz) frequencies are introduced. We explore in detail the two-wire waveguide showing that it can have absorption as low as 0.01 cm-1, fairly good coupling efficiency, and is free from group-velocity dispersion (GVD). We also propose two low loss, planar slot-line structures for guiding THz waves. Rigorous theoretical analyses, numerical simulations, and experimental results are presented to evaluate and verify the performance of the waveguides at THz frequencies. We also present a tapered structure to couple effectiv

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Gonçalves, Hélder José Alves. "Towards an efficient lattice basis reduction implementation." Master's thesis, 2016. http://hdl.handle.net/1822/47824.

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Dissertação de mestrado em Engenharia Informática (área de especialização em Computação Paralela e Distribuída)<br>The security of most digital systems is under serious threats due to major technology breakthroughs we are experienced in nowadays. Lattice-based cryptosystems are one of the most promising post-quantum types of cryptography, since it is believed to be secure against quantum computer attacks. Their security is based on the hardness of the Shortest Vector Problem and Closest Vector Problem. Lattice basis reduction algorithms are used in several fields, such as lattice-based cr

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Wang, Te-Chuan, and 王得權. "Efficient FFT Implementation Using CORDIC-Based Arithmetic." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/43260882553028239700.

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碩士<br>國立中正大學<br>資訊工程研究所<br>90<br>This thesis presents an efficient implementation of the pipeline FFT processor based on radix-4 decimation-in-time algorithm with the use of CORDIC-based arithmetic units. By recombining the sequential input samples to parallel data streams, the proposed architecture can’t only achieve nearly fully hardware utilization, but also require much less memory compared with the previous FFT processor. In addition, in FFT processors, several modules of ROM are required for the storage of twiddle factors. Exploiting the redundancy of the factors and using the CORDIC con

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Chen, Jian-Yu, and 陳建宇. "Efficient LDPC Decoder Implementation for IEEE 802.16e." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/23zfhb.

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碩士<br>國立中正大學<br>通訊工程研究所<br>100<br>Since the performance of Low-Density Parity Check (LDPC)codes is very close to Shannon limit, the related work has been widely discussed in the field of channel codes. LDPC codes are suitable for parallel decoding to achieve the high throughput due to the feature of highly parallelizable decoding architecture. Therefore, LDPC codes are preferable in many digital communication standards, such as the WiMax (802.16e) and Wi-Fi (802.11n). However, memory access conflict frequently occurred in the sub-matrices with same offsets when the fast decoding of Quasi-Cycli

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Wan-TingWeng and 翁琬婷. "High Efficient VLSI Implementation of Canny Edge Detection." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/6898t2.

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