Littérature scientifique sur le sujet « DV/dt control »

<p class="JESAbstract">This paper presents an active LC clamped dv/dt filter to mitigate the over voltages appearing across the motor terminals. The over voltages at motor terminal is due to voltage reflection effect of long motor cable connected between high frequency PWM inverter having high dv/dt switching waveforms and ac motor drives. The voltage reflection due to fast switching transients can be reduced by increasing the rise time and fall time of inverter output voltage pulses. The most commonly available mitigating technique is a passive dv/dt filter between inverter and cable. Since, size, cost and losses of passive LC dv/dt filter is more, an active dv/dt filtering technique is used to reduce over voltage at motor terminals. Active LC clamp filtering technique used here consists of a small LC filter designed for a single motor cable length which can be used for any lengths of cable up to 1000m only by changing the active control of the PWM pulses to achieve the desired voltage slope during voltage transition period. The basic principle of active dv/dt filer used here is to charge and discharge the capacitor in the filter with modified PWM pulses to increase the rise time and fall time of output voltage pulses without any extra devices to handle the transient response of the LC filter. Detailed investigation is carried out by simulation using MATLAB-Simulink software with active control of common LC clamp dv/dt filter suitable for various cable lengths ranging from 100 m to 1000 m. Comparative analysis is done with active dv/dt filter designed with a common LC clamp filter and active LC clamp dv/dt filter designed for various cable lengths and also with diode clamped passive dv/dt filter. The results proves the effectiveness of the active common LC dv/dt filter to mitigate the over voltages at motor terminal for cable lengths up to 1000m.</p>

<p class="JESAbstract">This paper presents an active LC clamped dv/dt filter to mitigate the over voltages appearing across the motor terminals. The over voltages at motor terminal is due to voltage reflection effect of long motor cable connected between high frequency PWM inverter having high dv/dt switching waveforms and ac motor drives. The voltage reflection due to fast switching transients can be reduced by increasing the rise time and fall time of inverter output voltage pulses. The most commonly available mitigating technique is a passive dv/dt filter between inverter and cable. Since, size, cost and losses of passive LC dv/dt filter is more, an active dv/dt filtering technique is used to reduce over voltage at motor terminals. Active LC clamp filtering technique used here consists of a small LC filter designed for a single motor cable length which can be used for any lengths of cable up to 1000m only by changing the active control of the PWM pulses to achieve the desired voltage slope during voltage transition period. The basic principle of active dv/dt filer used here is to charge and discharge the capacitor in the filter with modified PWM pulses to increase the rise time and fall time of output voltage pulses without any extra devices to handle the transient response of the LC filter. Detailed investigation is carried out by simulation using MATLAB-Simulink software with active control of common LC clamp dv/dt filter suitable for various cable lengths ranging from 100 m to 1000 m. Comparative analysis is done with active dv/dt filter designed with a common LC clamp filter and active LC clamp dv/dt filter designed for various cable lengths and also with diode clamped passive dv/dt filter. The results proves the effectiveness of the active common LC dv/dt filter to mitigate the over voltages at motor terminal for cable lengths up to 1000m.</p>

Abstract Aiming to the switching characteristics of SiC optically controlled transistor, SiC NPN optically controlled transistor was investigated through Silvaco TCAD. The results show that under 4500V bias voltage, the turn-on and turn-off dV/dt of the SiC transistor are 428.5V/ns and 23.9V/ns, respectively. And the tailing problem in the turn-off process is obvious. In order to improve the switching characteristics of SiC optically controlled transistor, the minority carrier lifetime in base layer is regional controlled. The simulation results indicate that, by using minority carrier lifetime control technology, the turn-off time and turn-off dV/dt are improved by about 28.2% and 39.3%, respectively. Meanwhile, turn-on time and turn-on dV/dt are only degenerated by about 3.6% and 3.4%, respectively. The overall level of switching characteristics of SiC optically controlled transistor are improved.

Wide-bandgap technology evolution compels the advancement of efficient pulse-width gate-driver devices. Integrated enhanced gate-driver planar transformers are a source of electromagnetic disturbances due to inter-winding capacitances, which serve as a route to common-mode(CM) currents. This paper will simulate, via ANSYS Q3D Extractor, the unforeseen parasitic effects of a pulse planar transformer integrated in a SiC MOSFET gate-driver card. Moreover, the pulse transformer will be ameliorated by adding distinctive shielding layers aiming to suppress CM noise effects and endure high dv/dt occurrences intending to validate experimental tests. The correlation between stray capacitance and dv/dt immunity results after shielding insertion will be reported.

Al giorno d'oggi il consumo mondiale di energia elettrica è in continuo aumento e più della metà dell'elettricità prodotta è consumata dai motori elettrici. Per far fronte a questo aumento, l'uso di motori a velocità variabile è fortemente incentivato nella gran parte dei paesi dalle normative sull'efficienza energetica. Questi motori sono in grado di consumare solo la quantità di elettricità necessaria. Questo è possibile grazie all’inverterizzazione: i motori a velocità variabile sono pilotati da switch di potenza collegati nella configurazione inverter-leg. Per fornire la corrente richiesta dal motore, gli switch di potenza vengono accesi e spenti alternativamente dal gate driver per generare un segnale modulato ad ampiezza di impulso nei nodi di fase del motore. I gate driver sono generalmente progettati per avere un singolo livello di corrente di uscita che viene utilizzato per caricare/scaricare le capacità parassite sulla gate dei power switch per accenderli/spegnerli. Un sistema di questo genere è molto efficiente, ma la dissipazione, anche se piccola, è sempre da considerare. Negli ultimi anni, la tecnologia superjunction (SJ) ha rivoluzionato l'industria dei dispositivi di potenza ad alta tensione migliorando il rapporto prestazioni/costi della conversione di potenza. I dispositivi SJ sono in grado di superare il Silicon Limit: il tradeoff tra tensione di breakdown e resistenza di stato on. Tuttavia, sono caratterizzati da una capacità di Miller non lineare, che fa sì che l'evento di switching inizi con dV/dt molto elevati e termini con un lunga slow-tail nelle ultime decine di volt. In un gate driver standard, il valore della corrente di gate io+ viene scelto come compromesso tra due vincoli opposti: limitare la dissipazione di potenza con un dV/dt veloce e soddisfare i vincoli di emissione condotta e radiata con un dV/dt lento. Con i dispositivi SJ non è quindi possibile usare un valore fisso di io+. Per usare i power switch in modo efficiente, viene presentato un sistema di controllo in grado di autoregolare la pendenza dV/dt, e di eliminare la slow-tail finale. Lo scopo di questo progetto di dottorato è quello di proporre una soluzione semplice ad anello chiuso dove non sia richiesta una grande larghezza di banda nè siano coinvolti elementi discreti e le non linearità dei power switch siano compensate. Si può ottenere in questo modo un dV/dt controllato che riduca la dissipazione e rispetti i vincoli di emissione condotta e radiata. Per fare ciò, come elemento di sensing viene utilizzata una capacità lineare integrata ad alta tensione collegata tra il low side e l'high side del gate driver. La corrente richiesta dalla carica e scarica di questa capacità durante l'evento di commutazione è proporzionale alla pendenza dV/dt. La corrente di gate viene quindi modificata di ciclo in ciclo in base alla pendenza rilevata per raggiungere il valore target di io+ richiesto dall'applicazione e viene forzata in tempo reale a un valore molto alto per eliminare la slow-tail negli ultimi volt. Sono stati prodotti due prototipi. Un primo chip di prova per convalidare il circuito di sensing e dimostrare l'efficacia dell'idea alla base. I risultati di misura si sono rivelati promettenti: la maggior parte del circuito ha funzionato come previsto. Per questo motivo è stato prodotto un secondo chip integrando il sensore in un gate driver con alcune piccole modifiche per migliorarne le prestazioni e per correggere alcuni difetti minori rilevati con la valutazione a banco del primo silicio. I risultati di misura relativi a questo secondo silicio hanno confermato l'efficacia della soluzione ad anello chiuso proposta, anche se prima di poter essere ampiamente utilizzato, il dispositivo necessiterà di ulteriori sviluppi e validazioni. I dettagli del progetto del circuito e la valutazione completa della misura di entrambi i prototipi saranno ampiamente discussi nel corso di questa tesi di dottorato.
Nowadays the world consumption of electrical energy is continuously increasing. More than an half of the produced electricity is consumed by electric motors. In order to cope with the increase in electricity consumption, the use of variable speed motor drives is promoted by energy efficiency regulations in most countries. These motors are able to consume only as much electricity as the application actually needs. They can do this by exploiting inverterization: variable speed drive motors are driven by power semiconductor switches connected in the inverter-leg configuration. They are alternatively switched on and off by the gate driver to generate a pulse width modulated signal on motor phase nodes used to provide the required current to the load. High voltage gate drivers are usually designed to have one single output current level used to charge/discharge the parasitic gate of external power switches to turn them on and off. Driving with a switching system is very efficient, but the dissipation, even if small, is always present and must be taken into account. In recent years, superjunction (SJ) technology has revolutionized the industry of high voltage power devices significantly improving the overall performance/cost ratio of power conversion. SJ devices are able to overcome the trade-off between breakdown voltage and on resistance, better known as the Silicon Limit. However, they are characterized by a non linear Miller capacitance, which causes the switching speed transient to start with very high dV/dt and to finish with a long slow-tail in the last few volts. In standard gate driver, the io+ driving capability is selected to find the best compromise between two opposite constraints: limiting the power dissipation with a fast dV/dt while satisfying conducted and radiated emission constraints with a slow dV/dt. With SJ devices it is not possible to meet this trade-off by simply selecting a fixed io+ value. To drive power switches with high efficiency a new driving strategy to make the whole system working in the optimum self-adjusting operating point for the fast dV/dt portion and to avoid the final slow-tail is presented. The aim of this PhD project is to propose a simple closed-loop solution where no large bandwidth neither discrete elements are required and the non-linearities of the power switching devices are compensated. In this way a controlled dV/dt transient can be achieved optimizing the trade-off between switching losses and conducted and radiated emission constraints. To do so, a linear integrated HV capacitor connected between the low side and the floating high side of the gate driver is used as sensing element. The current required by the charging and discharging of this capacitor during the active switching event is proportional to the dV/dt slope. The gate current is then changed cycle-by-cycle accordingly to the slope detected to reach the target io+ value needed by the power switches and forced in real-time to a very high value to cancel the slow-tail effect. Two silicon were taped-out. A first test chip to validate the sensing circuit and to prove the effectiveness of the core idea. The measurements were very promising: most of the circuit worked as expected. For this reason, a second tape-out was made integrating the sensor in a gate driver environment with some minor modifications to improve the performance and to fix some minor bugs detected with the bench evaluation of the first silicon. The measurements related to the second silicon confirmed the effectiveness of the proposed driving technique for hard-switching inverters stages, even though the device needs further development and validation before it can be widely employed. The details of the circuit design and the complete measurement evaluation of both the two test chips will be deeply discussed in the PhD thesis.

This work investigates the voltage scaling feasibility of several low voltage SiC MOSFET modules operated as a single series-connected switch using active gate control. Both multilevel and two-level topologies are capable of achieving higher blocking voltages in high-power converter applications. Compared to multilevel topologies, two-level switching topologies are of interest due to less complex circuitry, higher density, and simpler control techniques. In this work, to balance the voltage between series-connected MOSFETs, device turn-off speeds are dynamically controlled on active gate-drivers using active gate control. The implementation of the active gate control technique (specifically, turn-off dv/dt control) is described in this thesis. Experimental results of the voltage balancing behavior across eight 1.7 kV rated SiC MOSFET devices in series (6 kV total dc bus voltage) with the selected active dv/dt control scheme are demonstrated. Finally, the voltage balancing performance and switching behavior of series-connected SiC MOSFET devices are discussed.
Master of Science
According to ABB, 40% of the world's power demand is supplied by electrical energy. Specifically, in 2018, the world's electrical demand has grown by 4% since 2010. The growing need for electric energy makes it increasingly essential for systems that can efficiently and reliably convert and control energy levels for various end applications, such as electric motors, electric vehicles, data centers, and renewable energy systems. Power electronics are systems by which electrical energy is converted to different levels of power (voltage and current) depending on the end application. The use of power electronics systems is critical for controlling the flow of electrical energy in all applications of electric energy generation, transmission, and distribution. Advances in power electronics technologies, such as new control techniques and manufacturability of power semiconductor devices, are enabling improvements to the overall performance of electrical energy conversion systems. Power semiconductor devices, which are used as switches or rectifiers in various power electronic converters, are a critical building block of power electronic systems. In order to enable higher output power capability for converter systems, power semiconductor switches are required to sustain higher levels of voltage and current. Wide bandgap semiconductor devices are a particular new category of power semiconductors that have superior material properties compared to traditional devices such as Silicon (Si) Insulated-Gate Bipolar Junction Transistors (IGBTs). In particular, wide bandgap devices such as Silicon Carbide (SiC) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have better ruggedness and thermal capabilities. These properties provide wide bandgap semiconductor devices to operate at higher temperatures and switching frequencies, which is beneficial for maximizing the overall efficiency and volume of power electronic converters. This work investigates a method of scaling up voltage in particular for medium-voltage power conversion, which can be applied for a variety of application areas. SiC MOSFET devices are becoming more attractive for utilization in medium-voltage high-power converter systems due to the need to further improve the efficiency and density of these systems. Rather than using individual high voltage rated semiconductor devices, this thesis demonstrates the effectiveness of using several low voltage rated semiconductor devices connected in series in order to operate them as a single switch. Using low voltage devices as a single series-connected switch rather than a using single high voltage switch can lead to achieving a lower total on-state resistance, expectedly maximizing the overall efficiency of converter systems for which the series-connected semiconductor switches would be applied. In particular, this thesis focuses on the implementation of a newer approach of compensating for the natural unbalance in voltage between series-connected devices. An active gate control method is used for monitoring and regulating the switching speed of several devices operated in series in this work. The objective of this thesis is to investigate the feasibility of this method in order to achieve up to 6 kV total dc bus voltage using eight series-connected SiC MOSFET devices.