Thèses sur le sujet « Dégradation type porteurs chauds »
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Bénard, Christelle. « Etudes phénomènes de dégradation des transistos MOS de type porteurs chauds et Negative Bias Temperature Instability (NBTI) ». Aix-Marseille 1, 2008. http://theses.univ-amu.fr.lama.univ-amu.fr/2008AIX11028.pdf.
Texte intégralThis thesis work focuses on the different degradation phenomena that can affect a MOSFET. Two degradation modes have been specifically investigated: the Hot Carrier degradation and the NBTI degradation. In the first part, we fully study the relaxation phenomena specific of the defects generated by NBTI. This allows us to further understand the instabilities responsible for the characterization difficulty of the NBTI reliability. We examine in a second part the different existing NBTI characterization methods. It is made clear that, today, the only reliable method is the very fast Vt measurement which avoids any relaxation effect. Thanks to these studies, we have further interpreted the NBTI degradations. We have described a physical model of the NBTI degradation valid for all the studied transistors (Tox=23Å until Tox=200Å). According to this model, a double phenomenon of defect generation is responsible of the parameter shifts: the Si-H bond break which generates an interface state and a hole trap in the near oxide and the trapping on pre-existing defects (higher in thin oxides Tox<32Å). In parallel, we have studied the HC degradation on various transistors. This study has highlighted current degradation phenomena, still not well understood, as the abnormal temperature behavior of the degradation of low voltage transistors, or as the existing of two hot spots and its consequences in specific LDD structures. In the last part, we present the relation between static and dynamic degradations, more representative of the transistor normal conditions of use. This part proves, for example, that the HC contribution is not negligible in the degradation of an inverter gate, despite the fact that the NBTI period is much longer than the HC one
Ndiaye, Cheikh. « Etude de la fiabilité de type negative bias temperature instability (NBTI) et par porteurs chauds (HC) dans les filières CMOS 28nm et 14nm FDSOI ». Thesis, Aix-Marseille, 2017. http://www.theses.fr/2017AIXM0182/document.
Texte intégralThe subject of this thesis developed on four chapters, aims the development of advanced CMOS technology nodes fabricated by STMicroelectronics in terms of speed performance and reliability. The main reliability issues as Bias Temperature Instability (BTI) and Hot-Carriers (HC) degradation mechanisms have been studied in the most recent 28nm and 14nm FDSOI technologies nodes. In the first chapter, we presents the evolution of transistor architecture from the low-power 130-40nm CMOS nodes on silicon substrate to the recent FDSOI technology for 28nm and 14nm CMOS nodes. The second chapter presents the specificity of BTI and HCI degradation mechanisms involved in 28nm and 14nm FDSOI technology nodes. In the third chapter, we have studied the impact of layout effects on device performance and reliability comparing symmetrical and asymmetrical geometries. Finally the trade-off between performance and reliability is studied in the fourth chapter using elementary circuits. The benefit of using double gate configuration with the use of back bias VB in FDSOI devices to digital cells, allows to compensate partially or totally the aging in ring oscillators (ROs) observed by the frequency reduction. This new compensation technique allows to extend device and circuit lifetime offering a new way to guaranty high frequency performance and long-term reliability
Ndiaye, Cheikh. « Etude de la fiabilité de type negative bias temperature instability (NBTI) et par porteurs chauds (HC) dans les filières CMOS 28nm et 14nm FDSOI ». Electronic Thesis or Diss., Aix-Marseille, 2017. http://www.theses.fr/2017AIXM0182.
Texte intégralThe subject of this thesis developed on four chapters, aims the development of advanced CMOS technology nodes fabricated by STMicroelectronics in terms of speed performance and reliability. The main reliability issues as Bias Temperature Instability (BTI) and Hot-Carriers (HC) degradation mechanisms have been studied in the most recent 28nm and 14nm FDSOI technologies nodes. In the first chapter, we presents the evolution of transistor architecture from the low-power 130-40nm CMOS nodes on silicon substrate to the recent FDSOI technology for 28nm and 14nm CMOS nodes. The second chapter presents the specificity of BTI and HCI degradation mechanisms involved in 28nm and 14nm FDSOI technology nodes. In the third chapter, we have studied the impact of layout effects on device performance and reliability comparing symmetrical and asymmetrical geometries. Finally the trade-off between performance and reliability is studied in the fourth chapter using elementary circuits. The benefit of using double gate configuration with the use of back bias VB in FDSOI devices to digital cells, allows to compensate partially or totally the aging in ring oscillators (ROs) observed by the frequency reduction. This new compensation technique allows to extend device and circuit lifetime offering a new way to guaranty high frequency performance and long-term reliability
Toufik, Nezha. « Dégradation, par polarisation en avalanche, des paramètres d'une homojonction en silicium, durant l'émission de lumière ». Perpignan, 2002. http://www.theses.fr/2002PERP0452.
Texte intégralThis work proposed in specifying the processes of bipolar transistors degradation subjected to an electrical stress via avalanche breakdown of the reverse biased emitter-base junction. The finality is to determined the stability conditions of the light emission of the silicon junction in order to consider optoelectronics applications of silicon components. The method of characterization consists to determining, as function of stress time, the evolution of the parameters of the junction (recombination current, ideality factor and series resistances), obtained starting from the description of the current-tension characteristics with a two exponential models. The processes of degradation as their effects as well on the structure of the component as on the phenomena of transport of the carriers were specified. The analysis of the results showed that there is two periods existence of parameters degradation during the electrical stress, characterized by two different rates. The origin of these periods was related to the phenomena of release and of mobility of hydrogen ions to the interface of the emitter-base junction. These two intervals introduced by the differentiation of the evolution of junction parameters during stress correspond to the changes of the light emission observed all along the entire junction before it concentrated into localised junction sites
Guérin, Chloé. « Etude de la dégradation par porteurs chauds des technologies CMOS avancées en fonctionnement statique et dynamique ». Aix-Marseille 1, 2008. http://www.theses.fr/2008AIX11041.
Texte intégralIn the last technologies, dimension reduction is performed at constant bias which means an increase of the MOSFET lateral electrical field. Reliability risks in term of hot carriers are coming back. It is very important to understand the hot carrier degradation physical root causes to insure the best compromise between performance and reliability. After studying numerous stress biases, temperatures, oxide thicknesses and lengths, we established a new physical formalism based on both carrier energy and number. This double effect translates in a three degradation mode competition dominated by each of the modes depending on the energy range. At high energy, the degradation is due to a single carrier interaction with Si-H bonds (mode 1). But when the energy decreases, carrier number begins to dominate first trough Electron-Electron interactions (mode 2) and particularly at very low energy where we put forward that degradation increases due to bond multiple vibrational excitation with cold carriers (mode 3). This new modelling allows a better lifetime extrapolation at nominal biases. Applied to degradation under digital signals, it also enables a rigorous estimation of the degradation ratio between alternative and continuous current (AC-DC). Then new design guidelines concerning frequency, fanOut and rise time have been evidenced. Finally, this new modelling is now included in Design-in Reliability simulators to know precisely circuit bloc hot carrier degradation
Chapelon, Olivier. « Transport en régime de porteurs chauds dans le silicium de type n ». Montpellier 2, 1993. http://www.theses.fr/1993MON20066.
Texte intégralRevil, Narcisse. « Caractérisation et analyse de la dégradation induite par porteurs chauds dans les transistors MOS submicroniques et mésoscopiques ». Grenoble INPG, 1993. http://www.theses.fr/1993INPG0098.
Texte intégralNemar, Noureddine. « Génération-recombinaison en régime de porteurs chauds dans le silicium de type P ». Montpellier 2, 1990. http://www.theses.fr/1990MON20151.
Texte intégralArfaoui, Wafa. « Fiabilité Porteurs Chauds (HCI) des transistors FDSOI 28nm High-K grille métal ». Thesis, Aix-Marseille, 2015. http://www.theses.fr/2015AIXM4335.
Texte intégralAs the race towards miniaturization drives the industrial requirements to more performances on less area, MOSFETs reliability has become an increasingly complex topic. To maintain a continuous miniaturization pace, conventional transistors on bulk technologies were replaced by new MOS architectures allowing a better electrostatic integrity such as the FDSOI technology with high-K dielectrics and metal gate. Despite all the architecture innovations, degradation mechanisms remains increasingly pronounced with technological developments. One of the most critical issues of advanced technologies is the hot carrier degradation mechanism (HCI) and Bias Temperature Instability (BTI) effects. To ensure a good performance reliability trade off, it is necessary to characterize and model the different failure mechanisms at device level and the interaction with Bias Temperature Instability (BTI) that represents a strong limitation of scaled CMOS nodes. This work concern hot carrier degradation mechanisms on 28nm transistors of the FDSOI technology. Based on carrier’s energy, the energy driven model proposed in this manuscript can predict HC degradation taking account of substrate bias dependence (VB) including the channel length effects (L), gate oxide thickness (TOX) , back oxide BOX (TBox) and silicon film thickness (TSI ). This thesis opens up new perspectives of the model Integration into a circuit simulator, to anticipate the reliability of future technology nodes and check out circuit before moving on to feature design steps
Mamy, Randriamihaja Yoann. « Etude de la fiabilité des technologies CMOS avancées, depuis la création des défauts jusqu'à la dégradation des transistors ». Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4781/document.
Texte intégralReliability study is a milestone of microelectronic industry technology qualification. It is usually studied by following the degradation of transistors parameters with time, used to build physical models explaining transistors aging. We decided in this work to study transistors reliability at a microscopic scale, by focusing on atomic-bond-breaking mechanisms, responsible of defects creation into the gate-oxide. First, we identified defects nature and modeled their charge capture dynamics in order to reproduce their impact on complex electrical measurements degradation. This has allowed us developing a new methodology of defects localization, along the Si/SiO2 interface, and in the volume of the gate-oxide. Defects creation dynamics measurement, for Hot Carrier stress and stress conditions leading to the gate-oxide breakdown, has allowed us developing gate-oxide degradation models, predicting generated defect profiles at the interface and into the volume of the gate-oxide. Finally, we established an accurate link between a transistor degradation impact on circuit functionality loss.Reliability study and modeling at a microscopic scale allows having more physical models, granting a better confidence in transistors and products lifetime extrapolation
Maanane, Hichame. « Etude de la fiabilité des transistors hyperfréquences de puissance dans une application RADAR en bande S ». Rouen, 2005. http://www.theses.fr/2005ROUES061.
Texte intégralSicre, Mathieu. « Study of the noise aging mechanisms in single-photon avalanche photodiode for time-of-flight imaging ». Electronic Thesis or Diss., Lyon, INSA, 2023. http://www.theses.fr/2023ISAL0104.
Texte intégralSingle-Photon Avalanche Diode (SPAD) are used for Time-of-Flight (ToF) sensors to determine distance from a target by measuring the travel time of an emitted pulsed signal. These photodetectors work by triggering an avalanche of charge carriers upon photon absorption, resulting in a substantial amplification which can be detected. However, they are subject to spurious triggering by parasitic generated charge carriers, quantified as Dark Count Rate (DCR), which can compromise the accuracy of the measured distance. Therefore, it is crucial to identify and eliminate the potential source of DCR. To tackle this issue, a simulation methodology has been implemented to assess the DCR. This is achieved by simulating the avalanche breakdown probability, integrated with the carrier generation rate from defects. The breakdown probability can be simulated either in a deterministically, based on electric-field streamlines, or stochastically, by means of drift-diffusion simulation of the random carrier path. This methodology allows for the identification of the potential sources of pre-stress DCR by comparing simulation results to experimental data over a wide range of voltage and temperature. To ensure the accuracy of distance range measurements over time, it is necessary to predict the DCR level under various operating conditions. The aforementioned simulation methodology is used to identify the potential sources of post-stress DCR by comparing simulation results to stress experiments that evaluate the principal stress factors, namely temperature, voltage and irradiance. Furthermore, a Monte-Carlo study has been conducted to examine the device-to-device variation along stress duration. For an accurate Hot-Carrier Degradation (HCD) kinetics model, it is essential to consider not only the carrier energy distribution function but also the distribution of Si−H bond dissociation energy distribution at the Si/SiO2 interface. The number of available hot carriers is estimated from the carrier current density according to the carrier energy distribution simulated by means of a full-band Monte-Carlo method. The impact-ionization dissociation probability is employed to model the defect creation process, which exhibits sub-linear time dependence due to the gradual exhaustion of defect precursors. Accurate distance ranging requires distinguishing the signal from ambient noise and the DCR floor, and ensuring the target’s accumulated photon signal dominates over other random noise sources. An analytical formula allows to estimate the maximum distance ranging using the maximum signal strength, ambient noise level, and confidence levels. The impact of DCR can be estimated by considering the target’s reflectance and the ambient light conditions. In a nutshell, this work makes use of a in-depth characterization and simulation methodology to predict DCR in SPAD devices along stress duration, thereby allowing the assessment of its impact on distance range measurements
Zaka, Alban. « Carrier injection and degradation mechanisms in advanced NOR Flash memories ». Thesis, Grenoble, 2012. http://www.theses.fr/2012GRENT118/document.
Texte intégralZander, Damien. « Contribution à l'étude de la dégradation des couches d'oxyde de silicium ultra-minces, sous contraintes électriques ». Reims, 2002. http://www.theses.fr/2002REIMS015.
Texte intégralNouguier, Damien. « Etude statistique et modélisation de la dégradation NBTI pour les technologies CMOS FDSOI et BULK ». Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT068/document.
Texte intégralThe microelectronics industry is able to design transistors reaching dimensions of the order of ten nanometers. And doing this, we reaching the limits in terms of size reduction of CMOS transistors. At these dimensions, the reliability and variability of the devices is critical in terms of lifetime prediction and component warranty. Among the critical aspects, NBTI (Negative Bias Temperature Instability) degradation represents one of the biggest challenges in terms of reliability. This degradation coming from a charge trapping in the gate oxide is responsible for a large part of the degradation of the transistors. Performing a huge experimental work based on the characterization of the kinetic of degradation and relaxation of the NBTI degradation with rapid measurements, allowing us to work on the modeling of the stress and relaxation phases of NBTI degradation. We have successfully create a model for stress and relaxation of the NBTI degradation. These models were then tested on several technological nodes from 14nm FDSOI to 180nm Bulk. We also study the impact of some process changes on NBTI degradation. Finally, we propose a detailed study of the variability induced by the NBTI and the DCM model (Defect centric Model) allowing to model this variability. We also propose a mathematical correction of this model but also another mathematical expression of this model allowing to use it for a large number of defects. Enfin, nous prouvons que DCM est défectueux dans sa prédiction du nombre de défauts et nous proposons un nouveau modèle sous la forme d'un DCM avec deux défauts ou DDCM (Dual Defect Centric Model)
Qiao, Bo. « Une approche du vieillissement électrique des isolants polymères par mesure d'électroluminescence et de cathodoluminescence ». Thesis, Toulouse 3, 2015. http://www.theses.fr/2015TOU30116/document.
Texte intégralElectroluminescence (EL) of insulating polymers is a subject of great interest because it is associated with electrical ageing and could provide the signature of excited species under electric field. Electrical ageing and breakdown in insulating polymers is of fundamental interest to the researchers, the design engineers, the manufacturers and the customers of electrical apparatus. In this respect, Partial Discharge (PD) is a harmful process leading to ageing and failure of insulating polymers. However, with the development of the materials and apparatus, PDs can be weakened or avoided in some situations, e.g. extra high voltage cables, capacitors, etc. Therefore, there is urgent demand for understanding electrical degradation mechanisms under high electric field, which can be triggered by energetic charge carriers. In this work, Electroluminescence, EL, and cathodoluminescence, CL, excited under electron beam, along with other luminescence-family techniques are carried out for probing polyolefins and other insulating polymers. In order to uncover the excitons formation in Polypropylene (PP) and Polyethylene (PE) thin films, the field dependence of EL and current under DC stress and field dependence of EL and phase-resolved EL under AC stress, are investigated. The EL spectra of both PP and PE have the same main peak at approximately 570 nm, pointing towards similar chemical structures and defects in both polyolefins, and same route to degradation. This main peak can be complemented by an emission at approximately 750 nm dominating at low field. Electrode effect on the EL of Polyethylene Naphthalte (PEN) was investigated to understand the origin of the red emission at 750 nm. Through field dependence of EL and phase-resolved EL of Au or ITO electrodes, we proved the red component is due to the nature of electrode, more precisely Surface Plasmons and/or interface states. Further thorough study was carried out on cathodoluminescence of insulating polymers. Thin films of PP, PE, along with Polyethylene Naphthalate (PEN) and Polyether Ether Ketone (PEEK) were irradiated under electron beam up to 5 keV to be excited. We could reconstruct EL and CL spectra of both PE and PP using four elementary components: i.e. Fluorescence, Chemiluminescence, Recombination-induced Luminescence, and main component of the EL spectrum at 570 nm reported above and constituting an ageing marker. For the first time the nature of both EL and CL in polyolefins is uncovered, containing four basic components with different relative contributions. Identification of these spectral components is helpful to interpret the nature of light emission from polyolefins and other insulating polymers and to bridge the gap between space charge distribution and electrical ageing or breakdown. Through researches on EL and CL in several insulating polymers, i.e. polyolefins and a polyester, excitons formation and relaxation processes under electric stress and kinetic electrons are evidenced. More importantly, the spectral components analyses and reconstruction uncovers the nature of luminescence and its correlation to electrical ageing. In the future, luminescence measurement can be developed to be a standard method to probe and analyze insulating polymers
Ladret, Romain. « Nano-mélangeurs bolométriques supraconducteurs à électrons chauds en Y-Ba-Cu-O pour récepteur térahertz en mode passif ». Thesis, Paris 6, 2016. http://www.theses.fr/2016PA066245/document.
Texte intégralWe report on the development of a terahertz (THz) wave mixer made from high critical temperature superconducting YBaCuO ultrathin films (10 to 50 nm). The work is part of the MASTHER ANR project aiming at a portable demonstrator for passive terahertz heterodyne detection, implementing simplified cryogenics (60 to 80 kelvin). The detection principle is that of the hot electron bolometer (HEB) so far mainly developed with low critical temperature superconductors. The HEB effect is implemented in an YBaCuO constriction (a few hundred nm in lateral dimensions). This structure can lead to a sensitive and fast THz detector (theoretical instantaneous bandwidth of 100 GHz). The THz radiation is coupled to the YBaCuO constriction by means of a wideband planar antenna. The new aspects first concern the modeling of heat exchange between electrons and phonons reservoirs (YBaCuO and its substrate). Our results establish the optimum operating conditions in terms of dimensions of the constriction and the local oscillator power required for high performance THz mixing (conversion gain and noise temperature). We are introducing in particular a new "hot spot" modeling approach, which takes into account the influence of the terahertz frequency in the YBaCuO material and the impedance matching between the antenna and the constriction. Second, we have developed and optimized the HEB micro-fabrication process in clean room, especially the electronic and optical lithography steps, to obtain constrictions of 300 nm lateral size. Our first devices have been tested by direct detection in the infrared. The performance between YBaCuO ultrathin films prepared using various techniques are compared
Jacquet, Thomas. « Reliability of SiGe, C HBTs operating at 500 GHz : characterization and modeling ». Thesis, Bordeaux, 2016. http://www.theses.fr/2016BORD0354/document.
Texte intégralThe SiGe:C HBT reliability is an important issue in present and future practical applications. To reduce the designtime and increase the robustness of circuit applications, a compact model taking into account aging mechanismactivation has been developed in this thesis. After an aging test campaign and physical TCAD simulations, onemain damage mechanism has been identified. Depending on the bias conditions, hot carriers can be generatedby impact ionization in the base-collector junction and injected into the interfaces of the device where trapdensity can be created, leading to device degradation. This degradation mechanism impacting the EB/spacerinterface has been implemented in the HICUM compact model. This compact model has been used to performreliability studies of a LNA circuit. The CPU simulation time is not impacted by the activation of the degradationcompact model with an increase in computation time lower than 1%. This compact model allows performing areliability analysis with conventional circuit simulators and can be used to assist the design of more robustcircuits, which could help in reducing the design time cycle
L’affidabilità dei transistori a eterogiunzione SiGe:C è un aspetto molto importante nella progettazione circuitale,sia per le tecnologie attuali che per quelle in fase di sviluppo. In questo lavoro di tesi è stato sviluppato un modellocompatto in grado di descrivere i principali meccanismi di degrado, in modo da contribuire alla progettazione dicircuiti relativamente più robusti rispetto a tali fenomeni, ciò che potrebbe favorire una riduzione dei tempi diprogetto. A seguito di una campagna sperimentale e di un’analisi con tecniche TCAD, è stato identificato unmeccanismo principale di degrado. In particolari condizioni di polarizzazione, i portatori ad elevata energiagenerati per ionizzazione a impatto nella regione di carica spaziale, possono raggiungere alcune interfacce deldispositivo e ivi provocare la formazione di trappole. Solo la generazione di trappole relativa allo spaceremettitore-base è stata considerata nella formulazione del modello, essendo il fenomeno più rilevante. Ilmodello è stato utilizzato per effettuare alcuni studi di affidabilità di un amplificatore a basso rumore. Il tempocomputazionale non è significativamente influenzato dall’attivazione del modello di degrado, aumentando solodell’1%. Il modello sviluppato è compatibile con i comuni programmi di simulazione circuitale, e può essereimpiegato nella progettazione di circuiti con una migliore immunità rispetto ai fenomeni di degrado,contribuendo così a un riduzione dei tempi di progetto