Littérature scientifique sur le sujet « Dégradation type porteurs chauds »
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Thèses sur le sujet "Dégradation type porteurs chauds"
Bénard, Christelle. « Etudes phénomènes de dégradation des transistos MOS de type porteurs chauds et Negative Bias Temperature Instability (NBTI) ». Aix-Marseille 1, 2008. http://theses.univ-amu.fr.lama.univ-amu.fr/2008AIX11028.pdf.
Texte intégralThis thesis work focuses on the different degradation phenomena that can affect a MOSFET. Two degradation modes have been specifically investigated: the Hot Carrier degradation and the NBTI degradation. In the first part, we fully study the relaxation phenomena specific of the defects generated by NBTI. This allows us to further understand the instabilities responsible for the characterization difficulty of the NBTI reliability. We examine in a second part the different existing NBTI characterization methods. It is made clear that, today, the only reliable method is the very fast Vt measurement which avoids any relaxation effect. Thanks to these studies, we have further interpreted the NBTI degradations. We have described a physical model of the NBTI degradation valid for all the studied transistors (Tox=23Å until Tox=200Å). According to this model, a double phenomenon of defect generation is responsible of the parameter shifts: the Si-H bond break which generates an interface state and a hole trap in the near oxide and the trapping on pre-existing defects (higher in thin oxides Tox<32Å). In parallel, we have studied the HC degradation on various transistors. This study has highlighted current degradation phenomena, still not well understood, as the abnormal temperature behavior of the degradation of low voltage transistors, or as the existing of two hot spots and its consequences in specific LDD structures. In the last part, we present the relation between static and dynamic degradations, more representative of the transistor normal conditions of use. This part proves, for example, that the HC contribution is not negligible in the degradation of an inverter gate, despite the fact that the NBTI period is much longer than the HC one
Ndiaye, Cheikh. « Etude de la fiabilité de type negative bias temperature instability (NBTI) et par porteurs chauds (HC) dans les filières CMOS 28nm et 14nm FDSOI ». Thesis, Aix-Marseille, 2017. http://www.theses.fr/2017AIXM0182/document.
Texte intégralThe subject of this thesis developed on four chapters, aims the development of advanced CMOS technology nodes fabricated by STMicroelectronics in terms of speed performance and reliability. The main reliability issues as Bias Temperature Instability (BTI) and Hot-Carriers (HC) degradation mechanisms have been studied in the most recent 28nm and 14nm FDSOI technologies nodes. In the first chapter, we presents the evolution of transistor architecture from the low-power 130-40nm CMOS nodes on silicon substrate to the recent FDSOI technology for 28nm and 14nm CMOS nodes. The second chapter presents the specificity of BTI and HCI degradation mechanisms involved in 28nm and 14nm FDSOI technology nodes. In the third chapter, we have studied the impact of layout effects on device performance and reliability comparing symmetrical and asymmetrical geometries. Finally the trade-off between performance and reliability is studied in the fourth chapter using elementary circuits. The benefit of using double gate configuration with the use of back bias VB in FDSOI devices to digital cells, allows to compensate partially or totally the aging in ring oscillators (ROs) observed by the frequency reduction. This new compensation technique allows to extend device and circuit lifetime offering a new way to guaranty high frequency performance and long-term reliability
Ndiaye, Cheikh. « Etude de la fiabilité de type negative bias temperature instability (NBTI) et par porteurs chauds (HC) dans les filières CMOS 28nm et 14nm FDSOI ». Electronic Thesis or Diss., Aix-Marseille, 2017. http://www.theses.fr/2017AIXM0182.
Texte intégralThe subject of this thesis developed on four chapters, aims the development of advanced CMOS technology nodes fabricated by STMicroelectronics in terms of speed performance and reliability. The main reliability issues as Bias Temperature Instability (BTI) and Hot-Carriers (HC) degradation mechanisms have been studied in the most recent 28nm and 14nm FDSOI technologies nodes. In the first chapter, we presents the evolution of transistor architecture from the low-power 130-40nm CMOS nodes on silicon substrate to the recent FDSOI technology for 28nm and 14nm CMOS nodes. The second chapter presents the specificity of BTI and HCI degradation mechanisms involved in 28nm and 14nm FDSOI technology nodes. In the third chapter, we have studied the impact of layout effects on device performance and reliability comparing symmetrical and asymmetrical geometries. Finally the trade-off between performance and reliability is studied in the fourth chapter using elementary circuits. The benefit of using double gate configuration with the use of back bias VB in FDSOI devices to digital cells, allows to compensate partially or totally the aging in ring oscillators (ROs) observed by the frequency reduction. This new compensation technique allows to extend device and circuit lifetime offering a new way to guaranty high frequency performance and long-term reliability
Toufik, Nezha. « Dégradation, par polarisation en avalanche, des paramètres d'une homojonction en silicium, durant l'émission de lumière ». Perpignan, 2002. http://www.theses.fr/2002PERP0452.
Texte intégralThis work proposed in specifying the processes of bipolar transistors degradation subjected to an electrical stress via avalanche breakdown of the reverse biased emitter-base junction. The finality is to determined the stability conditions of the light emission of the silicon junction in order to consider optoelectronics applications of silicon components. The method of characterization consists to determining, as function of stress time, the evolution of the parameters of the junction (recombination current, ideality factor and series resistances), obtained starting from the description of the current-tension characteristics with a two exponential models. The processes of degradation as their effects as well on the structure of the component as on the phenomena of transport of the carriers were specified. The analysis of the results showed that there is two periods existence of parameters degradation during the electrical stress, characterized by two different rates. The origin of these periods was related to the phenomena of release and of mobility of hydrogen ions to the interface of the emitter-base junction. These two intervals introduced by the differentiation of the evolution of junction parameters during stress correspond to the changes of the light emission observed all along the entire junction before it concentrated into localised junction sites
Guérin, Chloé. « Etude de la dégradation par porteurs chauds des technologies CMOS avancées en fonctionnement statique et dynamique ». Aix-Marseille 1, 2008. http://www.theses.fr/2008AIX11041.
Texte intégralIn the last technologies, dimension reduction is performed at constant bias which means an increase of the MOSFET lateral electrical field. Reliability risks in term of hot carriers are coming back. It is very important to understand the hot carrier degradation physical root causes to insure the best compromise between performance and reliability. After studying numerous stress biases, temperatures, oxide thicknesses and lengths, we established a new physical formalism based on both carrier energy and number. This double effect translates in a three degradation mode competition dominated by each of the modes depending on the energy range. At high energy, the degradation is due to a single carrier interaction with Si-H bonds (mode 1). But when the energy decreases, carrier number begins to dominate first trough Electron-Electron interactions (mode 2) and particularly at very low energy where we put forward that degradation increases due to bond multiple vibrational excitation with cold carriers (mode 3). This new modelling allows a better lifetime extrapolation at nominal biases. Applied to degradation under digital signals, it also enables a rigorous estimation of the degradation ratio between alternative and continuous current (AC-DC). Then new design guidelines concerning frequency, fanOut and rise time have been evidenced. Finally, this new modelling is now included in Design-in Reliability simulators to know precisely circuit bloc hot carrier degradation
Chapelon, Olivier. « Transport en régime de porteurs chauds dans le silicium de type n ». Montpellier 2, 1993. http://www.theses.fr/1993MON20066.
Texte intégralRevil, Narcisse. « Caractérisation et analyse de la dégradation induite par porteurs chauds dans les transistors MOS submicroniques et mésoscopiques ». Grenoble INPG, 1993. http://www.theses.fr/1993INPG0098.
Texte intégralNemar, Noureddine. « Génération-recombinaison en régime de porteurs chauds dans le silicium de type P ». Montpellier 2, 1990. http://www.theses.fr/1990MON20151.
Texte intégralArfaoui, Wafa. « Fiabilité Porteurs Chauds (HCI) des transistors FDSOI 28nm High-K grille métal ». Thesis, Aix-Marseille, 2015. http://www.theses.fr/2015AIXM4335.
Texte intégralAs the race towards miniaturization drives the industrial requirements to more performances on less area, MOSFETs reliability has become an increasingly complex topic. To maintain a continuous miniaturization pace, conventional transistors on bulk technologies were replaced by new MOS architectures allowing a better electrostatic integrity such as the FDSOI technology with high-K dielectrics and metal gate. Despite all the architecture innovations, degradation mechanisms remains increasingly pronounced with technological developments. One of the most critical issues of advanced technologies is the hot carrier degradation mechanism (HCI) and Bias Temperature Instability (BTI) effects. To ensure a good performance reliability trade off, it is necessary to characterize and model the different failure mechanisms at device level and the interaction with Bias Temperature Instability (BTI) that represents a strong limitation of scaled CMOS nodes. This work concern hot carrier degradation mechanisms on 28nm transistors of the FDSOI technology. Based on carrier’s energy, the energy driven model proposed in this manuscript can predict HC degradation taking account of substrate bias dependence (VB) including the channel length effects (L), gate oxide thickness (TOX) , back oxide BOX (TBox) and silicon film thickness (TSI ). This thesis opens up new perspectives of the model Integration into a circuit simulator, to anticipate the reliability of future technology nodes and check out circuit before moving on to feature design steps
Mamy, Randriamihaja Yoann. « Etude de la fiabilité des technologies CMOS avancées, depuis la création des défauts jusqu'à la dégradation des transistors ». Thesis, Aix-Marseille, 2012. http://www.theses.fr/2012AIXM4781/document.
Texte intégralReliability study is a milestone of microelectronic industry technology qualification. It is usually studied by following the degradation of transistors parameters with time, used to build physical models explaining transistors aging. We decided in this work to study transistors reliability at a microscopic scale, by focusing on atomic-bond-breaking mechanisms, responsible of defects creation into the gate-oxide. First, we identified defects nature and modeled their charge capture dynamics in order to reproduce their impact on complex electrical measurements degradation. This has allowed us developing a new methodology of defects localization, along the Si/SiO2 interface, and in the volume of the gate-oxide. Defects creation dynamics measurement, for Hot Carrier stress and stress conditions leading to the gate-oxide breakdown, has allowed us developing gate-oxide degradation models, predicting generated defect profiles at the interface and into the volume of the gate-oxide. Finally, we established an accurate link between a transistor degradation impact on circuit functionality loss.Reliability study and modeling at a microscopic scale allows having more physical models, granting a better confidence in transistors and products lifetime extrapolation