Littérature scientifique sur le sujet « Core Reconfiguration »
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Articles de revues sur le sujet "Core Reconfiguration"
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Wanta, Damian, Waldemar T. Smolik, Jacek Kryszyn, Przemysław Wróblewski et Mateusz Midura. « A Run-Time Reconfiguration Method for an FPGA-Based Electrical Capacitance Tomography System ». Electronics 11, no 4 (11 février 2022) : 545. http://dx.doi.org/10.3390/electronics11040545.
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A desirable feature of an electrical capacitance tomography system is the adaptation possibility to any sensor configuration and measurement mode. A run-time reconfiguration of a system for electrical capacitance tomography is presented. An original mechanism is elaborated to reconfigure, on the fly, a modular EVT4 system with multiple FPGAs installed. The outlined system architecture is based on FPGA programmable logic devices (Xilinx Spartan) and PicoBlaze soft-core processors. Soft-core processors are used for communication, measurement control and data preprocessing. A novel method of FPGA partial reconfiguration is described, in which a PicoBlaze soft-core processor is used as a reconfiguration controller. Behavioral reconfiguration of the system is obtained by providing run-time access to the program code of a soft-core control processor. The tests using EVT4 hardware and different algorithms for tomographic scanning were performed. A test object was measured using 2D and 3D sensors. The time and resources required for the examined reconfiguration procedure are evaluated.
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Abdelrahman, T., C. Thomas, A. Iorwerth, MJ Pollitt, M. Holt et WG Lewis. « Core surgical training outcome in Wales ». Bulletin of the Royal College of Surgeons of England 98, no 10 (novembre 2016) : 456–59. http://dx.doi.org/10.1308/rcsbull.2016.457.
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Li, Ji, Huagang Xiong, Qiao Li, Feng Xiong et Jiaying Feng. « Run-Time Reconfiguration Strategy and Implementation of Time-Triggered Networks ». Electronics 11, no 9 (5 mai 2022) : 1477. http://dx.doi.org/10.3390/electronics11091477.
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Time-triggered networks are deployed in avionics and astronautics because they provide deterministic and low-latency communications. Remapping of partitions and the applications that reside in them that are executing on the failed core and the resulting re-routing and re-scheduling are conducted when a permanent end-system core failure occurs and local resources are insufficient. We present a network-wide reconfiguration strategy as well as an implementation scheme, and propose an Integer Linear Programming based joint mapping, routing, and scheduling reconfiguration method (JILP) for global reconfiguration. Based on scheduling compatibility, a novel heuristic algorithm (SCA) for mapping and routing is proposed to reduce the reconfiguration time. Experimentally, JILP achieved a higher success rate compared to mapping-then-routing-and-scheduling algorithms. In addition, relative to JILP, SCA/ILP was 50-fold faster and with a minimal impact on reconfiguration success rate. SCA achieved a higher reconfiguration success rate compared to shortest path routing and load-balanced routing. In addition, scheduling compatibility plays a guiding role in ILP-based optimization objectives and ‘reconfigurable depth’, which is a metric proposed in this paper for the determination of the reconfiguration potential of a TT network.
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Suri, Tameesh, et Aneesh Aggarwal. « Improving Adaptability and Per-Core Performance of Many-Core Processors Through Reconfiguration ». International Journal of Parallel Programming 38, no 3-4 (23 janvier 2010) : 203–24. http://dx.doi.org/10.1007/s10766-010-0128-3.
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Prabhu, Gayathri R., Bibin Johnson et J. Sheeba Rani. « Scalable Fixed Point QRD Core Using Dynamic Partial Reconfiguration ». International Journal of Reconfigurable Computing 2014 (2014) : 1–9. http://dx.doi.org/10.1155/2014/243835.
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A Givens rotation based scalable QRD core which utilizes an efficient pipelined and unfolded 2D multiply and accumulate (MAC) based systolic array architecture with dynamic partial reconfiguration (DPR) capability is proposed. The square root and inverse square root operations in the Givens rotation algorithm are handled using a modified look-up table (LUT) based Newton-Raphson method, thereby reducing the area by 71% and latency by 50% while operating at a frequency 49% higher than the existing boundary cell architectures. The proposed architecture is implemented on Xilinx Virtex-6 FPGA for any real matrices of sizem×n, where4≤n≤8andm≥nby dynamically inserting or removing the partial modules. The evaluation results demonstrate a significant reduction in latency, area, and power as compared to other existing architectures. The functionality of the proposed core is evaluated for a variable length adaptive equalizer.
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Zuo, Nianming, Zhengyi Yang, Yong Liu, Jin Li et Tianzi Jiang. « Core networks and their reconfiguration patterns across cognitive loads ». Human Brain Mapping 39, no 9 (20 avril 2018) : 3546–57. http://dx.doi.org/10.1002/hbm.24193.
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Yi, Lim, Anh Vu Le, Balakrishnan Ramalingam, Abdullah Aamir Hayat, Mohan Rajesh Elara, Tran Hoang Quang Minh, Braulio Félix Gómez et Lum Kai Wen. « Locomotion with Pedestrian Aware from Perception Sensor by Pavement Sweeping Reconfigurable Robot ». Sensors 21, no 5 (3 mars 2021) : 1745. http://dx.doi.org/10.3390/s21051745.
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Regular washing of public pavements is necessary to ensure that the public environment is sanitary for social activities. This is a challenge for autonomous cleaning robots, as they must adapt to the environment with varying pavement widths while avoiding pedestrians. A self-reconfigurable pavement sweeping robot, named Panthera, has the mechanisms to perform reconfiguration in width to enable smooth cleaning operations, and it changes its behavior based on environment dynamics of moving pedestrians and changing pavement widths. Reconfiguration in the robot’s width is possible, due to the scissor mechanism at the core of the robot’s body, which is driven by a lead screw motor. Panthera will perform locomotion and reconfiguration based on perception sensors feedback control proposed while using an Red Green Blue-D (RGB-D) camera. The proposed control scheme involves publishing robot kinematic parameters for reconfiguration during locomotion. Experiments were conducted in outdoor pavements to demonstrate the autonomous reconfiguration during locomotion to avoid pedestrians while complying with varying pavements widths in a real-world scenario.
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Lyric, Zoairia Idris, Mohammad Sayem Mahmood et Mohammad Abdul Motalab. « A study on TRIGA core reconfiguration with new irradiation channels ». Annals of Nuclear Energy 43 (mai 2012) : 183–86. http://dx.doi.org/10.1016/j.anucene.2011.12.034.
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Prasad Acharya, G., et M. Asha Rani. « Online Self-testable Multi-core System using Dynamic Partial Reconfiguration of FPGA ». International Journal of Reconfigurable and Embedded Systems (IJRES) 6, no 3 (28 mai 2018) : 160. http://dx.doi.org/10.11591/ijres.v6.i3.pp160-168.
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<span>This paper presents a novel and efficient method of designing an online self-testable multi-core system. Testing of a Core Under Test (CoUT) in a massively multi-core system can be carried out while the system is operational, by assigning the functionality of the CoUT to one of the non-functioning/idle and pre-tested core. The methodology presented in this paper has been implemented taking a test setup by demonstrating the Dynamic Partial Reconfiguration (DPR) feature of latest FPGAs on Zynq-7 XC702 evaluation board. The simulation results obtained from the experimental setup show that the utilization of a multi-core system can be significantly improved by effectively utilizing the idle core(s) to back up CoUT(s) for on-line test without a significant hardware overhead and test latency.</span>
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OKLOPCIC, ZORAN. « Beyond Empty, Conservative, and Ethereal : Pluralist Self-Determination and a Peripheral Political Imaginary ». Leiden Journal of International Law 26, no 3 (31 juillet 2013) : 509–29. http://dx.doi.org/10.1017/s0922156513000216.
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AbstractOver the last couple of years, a stream of pluralist theories of international legal order has developed at the intersection of international law and political theory, having immediate implications for conceptualizing self-determination. The understanding of self-determination under the framework ofbounded,constitutional, andradicalpluralism markedly departs from the previous wave of normative theories in the 1990s: self-determination is now evacuated from the field of national pluralism and struggles over territory.This article does not question the thrust of pluralists’ recent work, but complements their critical attunement to global disparities of power, and complicates their neglect of nationalism and rejection of territorial reconfigurations as self-determination's core meaning. In doing so, it unearths two visions that come from the (semi-)periphery of the international political order. The first belongs to Edvard Kardelj, pre-eminent Yugoslav theorist of socialist self-management and the Non-Aligned Movement. The second belongs to Leopold Sédar Senghor, the poet and politician, advocate ofnégritude, a proponent of French West African integration, and a constitutional advocate for the reconfiguration – not abolition – of the French Union, the heir to the French Empire. While they are suspicious of extensive territorial reconstruction, like contemporary pluralists, unlike them they have seen a role for territorial reconfigurations in the name of national plurality.
Thèses sur le sujet "Core Reconfiguration"
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Ballagh, Jonathan Bartlett. « An FPGA-based Run-time Reconfigurable 2-D Discrete Wavelet Transform Core ». Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/33649.
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FPGAs provide an ideal template for run-time reconfigurable (RTR) designs. Only recently have RTR enabling design tools that bypass the traditional synthesis and bitstream
generation process for FPGAs become available. The JBits tool suite is an environment that provides support for RTR designs on Xilinx Virtex and 4K devices. This research
provides a comprehensive design process description of a two-dimensional discrete wavelet transform (DWT) core using the JBits run-time reconfigurable FPGA design tool
suite. Several aspects of the design process are discussed, including implementation, simulation, debugging, and hardware interfacing to a reconfigurable computing platform.
The DWT lends itself to a straightforward implementation in hardware, requiring relatively simple logic for control and address generation circuitry. Through the application
of RTR techniques to the DWT, this research attempts to exploit certain advantages that are unobtainable with static implementations. Performance results of the DWT core are
presented, including speed of operation, resource consumption, and reconfiguration overhead times.Master of Science
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BALBONI, Marco. « NoC-Centric Partitionin and Reconfiguration Technology for the Efficient Sharing of General-Purose Prorammable Many-core Accelerators ». Doctoral thesis, Università degli studi di Ferrara, 2016. http://hdl.handle.net/11392/2403510.
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Negli ultimi decenni si sta assistendo ad una crescita tecnologica senza precedenti al centro dell’affermazione dei sistemi embedded, con la Legge di Moore come fattore dominante nel sostenere questo trend. Al giorno d’oggi, infatti, un sempre maggiore numero di cores può essere integrato nello stesso die, segnando il passaggio dallo Stato dell’Arte rappresentato dai chips multi-core ai nuovi paradigmi di design di chips manycore. Proprio questi chips many-core presentano un duplice scopo: fornire alte performance computazionalieaumentarel’efficienzadell’hardwareinterminidiOPS/Watt. Nonostante la potenza computazionale estremamente elevata, la complessità di questi nuovi chips sta dando vita a numerose sfide che i progettisti stanno fronteggiando sia per quanto riguarda l’hardware che per il software, focalizzate soprattutto sulla gestione a runtime dell’intelaiatura di computazione. La sfida affrontata in questa tesi è duplice e incentrata sullo sfruttare a pieno il potenziale di queste architetture many-core eterogenee. Da un lato il parallelismo software non scala con la stessa entità di quello hardware, perciò un problema è rappresentato da come condividere le risorse computazionali tra un batch di applicazioni concorrenti. Dall’altro lato, i tasks per la gestione del sistema many-core diventano fondamentali operazioni a runtime, che necessitano di essere eseguite trasparentemente e allo stesso tempo senza sospendere la computazione in corso sul sistema. Questa tesi fornisce un completo set di metodi di design volti dominare la complessità del runtime di acceleratori many-core ricchi di funzionalità, affidandosi a estensioni hardware della rete di interconnessione on-chip (Network-on-Chip, NoC). L’idea chiave, al centro del lavoro di questa tesi, è quella di sfruttare una strategia di Space-Division Multiplexing per schedulare l’esecuzione di applicazioni che richiedono di essere accelerate contemporaneamente sullo stesso array di tiles omogenei di computazione, così abilitando lo sfruttamento efficiente delle potenzialità delle risorse hardware presenti. L’applicazione più avanzata di questa idea consiste nella virtualizzazione del sistema embedded controllando le architetture di computazione eterogenee, scenario in cui molteplici macchine virtuali attive sullo stesso processore host potrebbero voler assegnare parte della computazione ad un acceleratore many-core programmabile. In questo contesto, una vir
tualizzazione efficiente implica un partizionamento flessibile delle risorse computazionali e delle memorie, un isolamento tra applicazioni concorrenti per motivi di sicurezza e la capacità di riconfigurarsi per adattarsi a runtime a diversi workloads. Mentre la gestione delle risorse dovrebbe essere un compito di una "torre di controllo" in software (hypervisor), il partizionamento, l’isolamento e la riconfigurazione necessitano di essere assistite in hardware, specialmente nell’infrastruttura di integrazione della piattaforma, che consiste nell’architettura di comunicazione. Il primo contributo di questa tesi consiste nel validare il nuovo paradigma di condivisione delle risorse basato sull’approccio SDM. Quindi, per prima cosa, si vuole comparare un approccio di tipo SDM con quello tradizionalmente usato e basato sul Time-Division Multiplexing. Per valutare le differenti strategie, in questa tesi si fa uso di benchmarks parallelizzati di Image Processing, la cui esecuzione è gestita da una versione ottimizzata del Runtime Environment OpenMP, necessario per abilitarne l’esecuzione parallelizzata. I benchmarks sono eseguiti su diversi ambienti di simulazione (VirtualSoC e gem5), che hanno richiesto entrambi una customizzazione per abilitare nuove funzionalità necessarie a simulare un acceleratore programmabile general-purpose (General-Purpose Programmable Accelerator, GPPA). Come risultato, questa tesi ha lo scopo di catturare l’impatto sulle performance del parallelismo, della dimensione e forma delle partizioni (numero di cluster computazionali riservati all’applicazione e loro posizione sulla struttura del manycore) e diversi settaggi di configurazione delle memorie. Ilsecondocontributoprincipaledellatesiconsistenell’abilitareunagestionealtamente dinamica delle risorse dell’acceleratore manycore. Infatti, la flessibile strategia di condivisione del manycore dipende essenzialmente dalla capacità di rinconfigurare a runtime la funzione di routing (che determina l’instradamento dei pacchetti) di una NoC, quindi in questa tesi si punta ad implementare un meccanismo di rinconfigurazione del routing veloce e scalabile e con una perturbazione minima del traffico di background. Si fornisce prima una soluzione centralizzata del problema e alla fine una completamente distribuita, valutando le implicazioni in termini di area e performance attraverso un’avanzata prototipazione su FPGA. Questo contributo apre la strada ad un futuro sviluppo di sistemi con la possibilità di configurarsi in modo molto fine, adattandosi ai diversi carichi richiesti, nonché a strategie di testing selettivo online di componenti che risultino trasparenti alle applicazioni eseguite.
Inoltre, questa tesi si punta all’introduzione della strategia SDM sviluppata a sistemi più futuristici, caratterizzati dall’integrazione nella struttura del manycore di tecnologie emergenti. In particolare ci si focalizza sull’integrazione della tecnologia ottica (fotonica) e sul co-design di caratteristiche di riconfigurazione e partizionamento di acceleratori programmabili con il requisito principale di minimizzare l’overhead in potenza statica consumata delle NoCs ottiche. Questo risultato è ottenuto attraverso il riutilizzo delle stesse
sorgenti laser tra diverse partizioni di computazione. In ultimo questa tesi re-architetta la completa infrastruttura gerarchica di comunicazione promuovendo un template di un’architettura di computazione eterogenea e parallela con integrazione fotonica, e giungendo ad una struttura di interconnessione ibrida che apre la strada a ricerche future.During the last few decades an unprecedented technological growth has been at the center of the embedded systems design paramountcy, with Moore’s Law being the leading factor of this trend. Today, in fact, an ever increasing number of cores can be integrated on the same die, marking the transition from state-of-the-art multi-core chips to the new many-core design paradigm. Such manycore chips aim is twofold: provide high computing performance and increase the energy eciency of the hardware in terms of OPS/Watt. Despite the extraordinarily high computing power, the complexity of many-core chips opens the door to several challenges for designers that are today facing with the huge intricacy of both hardware and software, trying to unmask the best solutions to exploit the potential of these heterogeneous many-core architectures. This thesis provides a whole set of design methods to enable and manage the runtime heterogeneity of features-rich industry-ready Tile-Based Networks-on-Chip and it is focused on virtualization techniques with the goal to mitigate, and overtake when possible, some of the challenges introduced by the many-core design paradigm. The key idea is to exploit a Space-Division Multiplexing strategy to schedule the execution of applications that require to be accelerated or multiple active Virtual Machines, enabling an e↵ective virtualization by means of resources sharing, relying on both hardware and software support to this new highly dynamic environment, thus eciently exploiting the high parallel hardware of many-core chips. Virtualization implies flexible partitioning of resources and isolation for protection and requires a control tower in software (hypervisor) but it needs that the proper course of action, following the hypervisor, is taken by the on-chip network (NoC) that is the best on-chip communication infrastructure suitable for many-core architectures and that is becoming also the real system integration and control framework. The resources management concept depends mainly on the runtime reconfiguration capability of the NoC routing function so, the first contribution of this thesis indeed tackles this challenge with the final outcome of a distributed, fast reconfiguration and scalable mechanism with minimum perturbation on the background trac and finally it undergo FPGA prototyping, allowing to compare area overhead and critical path. Another main contribution of my work, related to the scheduling of execution of several applications on the manycore, is comparing a SDM approach to a TDM one. To evaluate the di↵erent strategies I rely on parallelized Image Processing benchmarks, whose execution is managed by an optimized version of an OpenMP Runtime, needed to enable their parallel execution. I run the benchmark on di↵erent simulation environments (VirtualSoC and gem5) customized and enhanced with new functionalities to emulate a General-Purpose Programmable Accelerator, thus studying the impact on performance of parallelism, dimensions and shapes of partitions (numbers of computational clusters reserved and their position) and memory configuration. Finally, I focus also on emerging technologies, in particular on Optical NoC and their partitioning strategy proposed to decrease the static power consumption, tearing-down unused laser sources and relying on re-use of the same wavelengths. I also re-architect the communication infrastructure in a template GPPA architecture, and coming up with a hybrid interconnect fabric, thus proposing the first assessment of optical interconnect technology in the context of these devices.
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Khuat, Quang Hai. « Definition and evaluation of spatio-temporal scheduling strategies for 3D multi-core heterogeneous architectures ». Thesis, Rennes 1, 2015. http://www.theses.fr/2015REN1S007/document.
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Empilant une couche multiprocesseur (MPSoC) et une couche de FPGA pour former un système sur puce reconfigurable en trois dimension (3DRSoC), est une solution prometteuse donnant un niveau de flexibilité élevé en adaptant l'architecture aux applications visées. Pour une application exécutée sur ce système, l'un des principaux défis vient de la gestion de haut niveau des tâches. Cette gestion est effectuée par le service d'ordonnancement du système d'exploitation et elle doit être en mesure de déterminer, lors de l'exécution de l'application, quelle tâche est exécutée logiciellement et/ou matériellement, quand (dimension temporelle) et sur quelles ressources (dimension spatiale, c'est à dire sur quel processeur ou quelle région du FPGA) pour atteindre la haute performance du système. Dans cette thèse, nous proposons des stratégies d'ordonnancement spatio-temporel pour les architectures 3DRSoCs. La première stratégie décide la nécessité de placer une tâche matérielle et une tâche logicielle en face-à-face afin que le coût de la communication entre tâches soit minimisé. La deuxième stratégie vise à minimiser le temps d'exécution globale de l'application. Cette stratégie exploits la présence de processeurs de la couche MPSoC afin d'anticiper, en temps-réel, l'exécution d'une tâche logicielle quand sa version matérielle ne peut pas être allouée sur le FPGA. Ensuite, un outil de simulation graphique a été développé pour vérifier le bon fonctionnement des stratégies développées et aussi nous permettre de produire des résultatsStacking a multiprocessor (MPSoC) layer and a FPGA layer to form a 3D Reconfigurable System-on- Chip (3DRSoC) is a promising solution giving a high flexibility level in adapting the architecture to the targeted application. For an application defined as a graph of parallel tasks running on the 3DRSoC system, one of the main challenges comes from the high-level management of tasks. This management is done by the scheduling service of the Operating System and it must be able to determine, on the fly, what task should be run in software and/or hardware, when (temporal dimension) and where (spatial dimension, i.e. on what processor or what area of the FPGA) in order to achieve high performance of the system. In this thesis, we propose online spatio-temporal scheduling strategies for 3DRSoCs. The first strategy decides, during the task scheduling, the need for a SW task and a HW task to communicate in face-to-face so that the communication cost between tasks is minimized. The second strategy aims at minimizing the overall execution time of the application. It exploits the presence of processors in the MPSoC layer in order to anticipate, at run-time, the SW execution of a task when its HW version cannot be allocated to the FPGA. Then, a graphical simulation tool has been developed to verify the proper functioning of the developed strategies and also enable us to produce results
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Gammoudi, Aymen. « Stratégie de placement et d'ordonnancement de taches logicielles pour architectures reconfigurables sous contrainte énergétique ». Thesis, Rennes 1, 2018. http://www.theses.fr/2018REN1S030/document.
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La conception de systèmes temps-réel embarqués se développe de plus en plus avec l’intégration croissante de fonctionnalités critiques pour les applications de surveillance, notamment dans le domaine biomédical, environnemental, domotique, etc. Le développement de ces systèmes doit relever divers défis en termes de minimisation de la consommation énergétique. Gérer de tels dispositifs embarqués, entièrement autonomes, nécessite cependant de résoudre différents problèmes liés à la quantité d’énergie disponible dans la batterie, à l’ordonnancement temps-réel des tâches qui doivent être exécutées avant leurs échéances, aux scénarios de reconfiguration, particulièrement dans le cas d’ajout de tâches, et à la contrainte de communication pour pouvoir assurer l’échange des messages entre les processeurs, de façon à assurer une autonomie durable jusqu’à la prochaine recharge et ce, tout en maintenant un niveau de qualité de service acceptable du système de traitement. Pour traiter cette problématique, nous proposons dans ces travaux une stratégie de placement et d’ordonnancement de tâches permettant d’exécuter des applications temps-réel sur une architecture contenant des cœurs hétérogènes. Dans cette thèse, nous avons choisi d’aborder cette problématique de façon incrémentale pour traiter progressivement les problèmes liés aux contraintes temps-réel, énergétique et de communications. Tout d’abord, nous nous intéressons particulièrement à l’ordonnancement des tâches sur une architecture mono-cœur. Nous proposons une stratégie d’ordonnancement basée sur le regroupement des tâches dans des packs pour pouvoir calculer facilement les nouveaux paramètres des tâches afin de réobtenir la faisabilité du système. Puis, nous l’avons étendu pour traiter le cas de l’ordonnancement sur une architecture multi-cœurs homogènes. Finalement, une extension de ce dernier sera réalisée afin d’arriver à l’objectif principal qui est l’ordonnancement des tâches pour les architectures hétérogènes. L’idée est de prendre progressivement en compte des contraintes d’exécution de plus en plus complexes. Nous formalisons tous les problèmes en utilisant la formulation ILP afin de pouvoir produire des résultats optimaux. L’idée est de pouvoir situer nos solutions proposées par rapport aux solutions optimales produites par un solveur et par rapport aux autres algorithmes de l’état de l’art. Par ailleurs, la validation par simulation des stratégies proposées montre qu’elles engendrent un gain appréciable vis-à-vis des critères considérés importants dans les systèmes embarqués, notamment le coût de la communication entre cœurs et le taux de rejet des tâchesThe design of embedded real-time systems is developing more and more with the increasing integration of critical functionalities for monitoring applications, particularly in the biomedical, environmental, home automation, etc. The developement of these systems faces various challenges particularly in terms of minimizing energy consumption. Managing such autonomous embedded devices, requires solving various problems related to the amount of energy available in the battery and the real-time scheduling of tasks that must be executed before their deadlines, to the reconfiguration scenarios, especially in the case of adding tasks, and to the communication constraint to be able to ensure messages exchange between cores, so as to ensure a lasting autonomy until the next recharge, while maintaining an acceptable level of quality of services for the processing system. To address this problem, we propose in this work a new strategy of placement and scheduling of tasks to execute real-time applications on an architecture containing heterogeneous cores. In this thesis, we have chosen to tackle this problem in an incremental manner in order to deal progressively with problems related to real-time, energy and communication constraints. First of all, we are particularly interested in the scheduling of tasks for single-core architecture. We propose a new scheduling strategy based on grouping tasks in packs to calculate the new task parameters in order to re-obtain the system feasibility. Then we have extended it to address the scheduling tasks on an homogeneous multi-core architecture. Finally, an extension of the latter will be achieved in order to realize the main objective, which is the scheduling of tasks for the heterogeneous architectures. The idea is to gradually take into account the constraints that are more and more complex. We formalize the proposed strategy as an optimization problem by using integer linear programming (ILP) and we compare the proposed solutions with the optimal results provided by the CPLEX solver. Inaddition, the validation by simulation of the proposed strategies shows that they generate a respectable gain compared with the criteria considered important in embedded systems, in particular the cost of communication between cores and the rate of new tasks rejection
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Fuguet, Tortolero César. « Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente ». Thesis, Paris 6, 2015. http://www.theses.fr/2015PA066462/document.
Texte intégralRésumé :
L'augmentation continue de la puissance de calcul requise par les applications telles que la cryptographie, la simulation, ou le traitement du signal a fait évoluer la structure interne des processeurs vers des architectures massivement parallèles (dites « many-core »). Ces architectures peuvent contenir des centaines, voire des milliers de cœurs afin de fournir une puissance de calcul importante avec une consommation énergétique raisonnable. Néanmoins, l'importante densité de transistors fait que ces architectures sont très susceptibles aux pannes matérielles. L'augmentation dans la variabilité du processus de fabrication, et dans les facteurs de stress des transistors, dégrade à la fois le rendement de fabrication, et leur durée de vie. Nous proposons donc un mécanisme complet de tolérance aux pannes franches, permettant les architectures « many-core » à mémoire partagée cohérente de fonctionner dans un mode dégradé. Ce mécanisme s'appuie sur un logiciel embarqué et distribué dans des mémoires sur puce (« firmware »), qui est exécuté par les cœurs à chaque démarrage du processeur. Ce logiciel implémente plusieurs algorithmes distribués permettant de localiser les composants défaillants (cœurs, bancs mémoires, et routeurs des réseaux sur puce), de reconfigurer l'architecture matérielle, et de fournir une cartographie de l'infrastructure matérielle fonctionnelle au système d'exploitation. Le mécanisme supporte aussi bien des défauts de fabrication, que des pannes de vieillissement après que la puce est en service dans l'équipement. Notre proposition est évaluée en utilisant un prototype virtuel précis au cycle d'une architecture « many-core » existanteThe always increasing performance demands of applications such as cryptography, scientific simulation, network packets dispatching, signal processing or even general-purpose computing has made of many-core architectures a necessary trend in the processor design. These architectures can have hundreds or thousands of processor cores, so as to provide important computational throughputs with a reasonable power consumption. However, their important transistor density makes many-core architectures more prone to hardware failures. There is an augmentation in the fabrication process variability, and in the stress factors of transistors, which impacts both the manufacturing yield and lifetime. A potential solution to this problem is the introduction of fault-tolerance mechanisms allowing the processor to function in a degraded mode despite the presence of defective internal components. We propose a complete in-the-field reconfiguration-based permanent failure recovery mechanism for shared-memory many-core processors. This mechanism is based on a firmware (stored in distributed on-chip read-only memories) executed at each hardware reset by the internal processor cores without any external intervention. It consists in distributed software procedures, which locate the faulty components (cores, memory banks, and network-on-chip routers), reconfigure the hardware architecture, and provide a description of the functional hardware infrastructure to the operating system. Our proposal is evaluated using a cycle-accurate SystemC virtual prototype of an existing many-core architecture. We evaluate both its latency, and its silicon cost
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Grand, Michaël. « Conception d’un crypto-système reconfigurable pour la radio logicielle sécurisée ». Thesis, Bordeaux 1, 2011. http://www.theses.fr/2011BOR14388/document.
Texte intégralRésumé :
Les travaux de recherche détaillés dans ce document portent sur la conception et l’implantation d’un composant matériel jouant le rôle du sous-système cryptographique d’une radio logicielle sécurisée.A partir du début des années 90, les systèmes radios ont peu à peu évolué de la radio classique vers la radio logicielle. Le développement de la radio logicielle a permis l’intégration d’un nombre toujours plus grand de standards de communication sur une même plateforme matérielle. La réalisation concrète d’une radio logicielle sécurisée amène son concepteur à faire face à de nombreuses problématiques qui peuvent se résumer par la question suivante : Comment implanter un maximum de standards de communication sur une même plateforme matérielle et logicielle ? Ce document s’intéresse plus particulièrement à l’implantation des standards cryptographiques destinés à protéger les radiocommunications.Idéalement, la solution apportée à ce problème repose exclusivement sur l’utilisation de processeurs numériques. Cependant, les algorithmes cryptographiques nécessitent le plus souvent une puissance de calcul telle que leur implantation sous forme logicielle n’est pas envisageable. Il s’ensuit qu’une radio logicielle doit parfois intégrer des composants matériels dédiés dont l'utilisation entre en conflit avec la propriété de flexibilité propre aux radios logicielles.Or depuis quelques années, le développement de la technologie FPGA a changé la donne. En effet, les derniers FPGA embarquent un nombre de ressources logiques suffisant à l’implantation des fonctions numériques complexes utilisées par la radio logicielle. Plus précisément, la possibilité offerte par les FPGA d'être reconfiguré dans leur totalité (voir même partiellement pour les derniers d’entre eux) fait d’eux des candidats idéaux à l’implantation de composants matériels flexibles et évolutifs dans le temps. À la suite de ces constatations, des travaux de recherche ont été menés au sein de l’équipe Conception des Systèmes Numériques du Laboratoire IMS. Ces travaux ont d’abord débouché sur la publication d’une architecture de sous-système cryptographique pour la radio logicielle sécurisée telle qu’elle est définie par la Software Communication Architecture. Puis, ils se sont poursuivis par la conception et l’implantation d’un cryptoprocesseur multi-cœur dynamiquement reconfigurable sur FPGAThe research detailed in this document deal with the design and implementation of a hardware integrated circuit intended to be used as a cryptographic sub-system in secure software defined radios.Since the early 90’s, radio systems have gradually evolved from traditional radio to software defined radio. Improvement of the software defined radio has enabled the integration of an increasing number of communication standards on a single radio device. The designer of a software defined radio faces many problems that can be summarized by the following question: How to implement a maximum of communication standards into a single radio device? Specifically, this work focuses on the implementation of cryptographic standards aimed to protect radio communications.Ideally, the solution to this problem is based exclusively on the use of digital processors. However, cryptographic algorithms usually require a large amount of computing power which makes their software implementation inefficient. Therefore, a secure software defined radio needs to incorporate dedicated hardware even if this usage is conflicting with the property of flexibility specific to software defined radios.Yet, in recent years, the improvement of FPGA circuits has changed the deal. Indeed, the latest FPGAs embed a number of logic gates which is sufficient to meet the needs of the complex digital functions used by software defined radios. The possibility offered by FPGAs to be reconfigured in their entirety (or even partially for the last of them) makes them ideal candidates for implementation of hardware components which have to be flexible and scalable over time.Following these observations, research was conducted within the Conception des Systèmes Numériques team of the IMS laboratory. These works led first to the publication of an architecture of cryptographic subsystem compliant with the security supplement of the Software Communication Architecture. Then, they continued with the design and implementation of a partially reconfigurable multi-core cryptoprocessor intended to be used in the latest FPGAs
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Das, Satyajit. « Architecture and Programming Model Support for Reconfigurable Accelerators in Multi-Core Embedded Systems ». Thesis, Lorient, 2018. http://www.theses.fr/2018LORIS490/document.
Texte intégralRésumé :
La complexité des systèmes embarqués et des applications impose des besoins croissants en puissance de calcul et de consommation énergétique. Couplé au rendement en baisse de la technologie, le monde académique et industriel est toujours en quête d'accélérateurs matériels efficaces en énergie. L'inconvénient d'un accélérateur matériel est qu'il est non programmable, le rendant ainsi dédié à une fonction particulière. La multiplication des accélérateurs dédiés dans les systèmes sur puce conduit à une faible efficacité en surface et pose des problèmes de passage à l'échelle et d'interconnexion. Les accélérateurs programmables fournissent le bon compromis efficacité et flexibilité. Les architectures reconfigurables à gros grains (CGRA) sont composées d'éléments de calcul au niveau mot et constituent un choix prometteur d'accélérateurs programmables. Cette thèse propose d'exploiter le potentiel des architectures reconfigurables à gros grains et de pousser le matériel aux limites énergétiques dans un flot de conception complet. Les contributions de cette thèse sont une architecture de type CGRA, appelé IPA pour Integrated Programmable Array, sa mise en œuvre et son intégration dans un système sur puce, avec le flot de compilation associé qui permet d'exploiter les caractéristiques uniques du nouveau composant, notamment sa capacité à supporter du flot de contrôle. L'efficacité de l'approche est éprouvée à travers le déploiement de plusieurs applications de traitement intensif. L'accélérateur proposé est enfin intégré à PULP, a Parallel Ultra-Low-Power Processing-Platform, pour explorer le bénéfice de ce genre de plate-forme hétérogène ultra basse consommationEmerging trends in embedded systems and applications need high throughput and low power consumption. Due to the increasing demand for low power computing and diminishing returns from technology scaling, industry and academia are turning with renewed interest toward energy efficient hardware accelerators. The main drawback of hardware accelerators is that they are not programmable. Therefore, their utilization can be low is they perform one specific function and increasing the number of the accelerators in a system on chip (SoC) causes scalability issues. Programmable accelerators provide flexibility and solve the scalability issues. Coarse-Grained Reconfigurable Array (CGRA) architecture consisting of several processing elements with word level granularity is a promising choice for programmable accelerator. Inspired by the promising characteristics of programmable accelerators, potentials of CGRAs in near threshold computing platforms are studied and an end-to-end CGRA research framework is developed in this thesis. The major contributions of this framework are: CGRA design, implementation, integration in a computing system, and compilation for CGRA. First, the design and implementation of a CGRA named Integrated Programmable Array (IPA) is presented. Next, the problem of mapping applications with control and data flow onto CGRA is formulated. From this formulation, several efficient algorithms are developed using internal resources of a CGRA, with a vision for low power acceleration. The algorithms are integrated into an automated compilation flow. Finally, the IPA accelerator is augmented in PULP - a Parallel Ultra-Low-Power Processing-Platform to explore heterogeneous computing
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Abdelrahman, Tarig. « Evaluation of Wales Postgraduate Medical and Dental Education Deanery outcomes at core and higher general surgery before and after national reconfiguration, enhanced selection, and Joint Committee on Surgical Training defined curricular standards ». Thesis, Cardiff University, 2017. http://orca.cf.ac.uk/100975/.
Texte intégralRésumé :
This thesis examines contemporary outcomes of surgical training in Wales and the UK. The hypotheses tested were: Core Surgical Training (CST) outcome is related to specific curricular defined goals, and themed focused CST rotations improve success at National Training Number (NTN)appointment; CST rotations including rural placements provide training comparable with non-rural placements; General Surgery (GS) Certificate of Completion of Training (CCT) curricular guidelines require focused appraisal and rotation planning; GS Higher Surgical Trainee (HST) indicative procedure targets are not in keeping with competence achievement determined by Procedural Based Assessment (PBA); Dedicated Emergency General Surgery (EGS) modules enhance HST training experience; H-Indices are a valid measure of GS consultant academic productivity and identify training research opportunity. Successful ST3 NTN appointment improved from 5.3 to 33.3% (p=0.005) following CST [OR 4.789 (1.666 - 13.763), p=0.004] and is independently associated with success. ST3 appointment was similar irrespective of rural or non-rural CST rotational placement (18.1 vs. 22.1%, p=0.695). Of the 155 UK GS HST CCTs awarded in 2013, global operative log book and academic achievements varied widely, with two-thirds of trainees achieving elective operative targets, but only half the requisite experience in EGS, and 5% nonoperative targets. Wales’ HSTs level 4 GS operative competencies varied 4- fold, ranging from 0.76 to 3.4 times national targets. EGS modular training introduction delivered a high volume of index EGS procedures and higher rates of PBA completion when compared with controls. H-indices were a robust measure of surgeons’ academic activity (p < 0.001).
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Krill, Benjamin. « A reconfigurable environment for IP cores implementation using dynamic partial reconfiguration ». Thesis, University of Ulster, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.556481.
Texte intégralRésumé :
Hardware acceleration is becoming increasingly important in high performance applications due to their computational complexity. Recently, field programmable gate arrays (FPGAs) have gained popularity as a suitable platform for many high performance applications. FPGAs offer low power, reconfigurability, high performance and low design- turnaround time which enable FPGAs to be used in a number of image and signal processing applications. Due to the increasing complexity of acceleration systems, abstraction of these technologies and power dissipation has become one of the most important challenges. Addressing these issues require awareness at all levels of the system and FPGA design flow. The key achievements of the work presented in this thesis are summarised as follows. Novel architectures based on different design approaches and abstraction techniques - virtual file systems (VFS), dynamic partial reconfiguration (DPR) mechanism, distributed arithmetic (DA) and parallel digital signal processing - are developed for a generic frame- work and for three-dimensional (3-D) algorithms. Furthermore, solutions to divide large algorithms into small modules that fit on smaller, less power consuming FPGAs are investigated. An abstraction layer using a VFS for different platforms is carried out, and as a result a partial reconfiguration design flow framework is developed. The ultimate aim of this dissertation is to examine an efficient reconfigurable architecture for generic 3-D cyclic convolution (3-DeC). This is achieved with the previously investigated abstraction layer and framework, to demonstrate the operation of the framework, allowing discussion and the evaluation of techniques that are only possible on new FPGA devices. Results obtained have shown the advantages offered by the DPR framework and abstraction layer, and lead to a processing solution for implementing computationally intensive applications. A key section of this work included the development of the complete integration of the dynamic partial reconfiguration design flow and application usage - using the proposed abstraction model. The technique used explores the logic space and power consumptions needed to divide the algorithm for optimal application runtime situations.
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GIULIANO, Fabrizio. « Supporting code mobility and dynamic reconfigurations over Wireless MAC Processor Prototype ». Doctoral thesis, Università degli Studi di Palermo, 2014. http://hdl.handle.net/10447/91036.
Texte intégralRésumé :
Mobile networks for Internet Access are a fundamental segment of Internet access net- works, where resource optimization are really critical because of the limited bandwidth availability. While traditionally resource optimizations have been focused on high effi- cient modulation and coding schemes, to be dynamically tuned according to the wireless channel and interference conditions, it has also been shown how medium access schemes can have a significant impact on the network performance according to the application and networking scenarios.
This thesis work proposes an architectural solution for supporting Medium Access Con- trol (MAC) reconfigurations in terms of dynamic programming and code mobility. Since the MAC protocol is usually implemented in firmware/hardware (being constrained to very strict reaction times and to the rules of a specific standard), our solution is based on a different wireless card architecture, called Wireless MAC Processor (WMP), where standard protocols are replaced by standard programming interfaces.
The control architecture developed in this thesis exploits this novel behavioral model of wireless cards for extending the network intelligence and enabling each node to be remotely reprogrammed by means a so called “MAC Program”, i.e. a software element that defines the description of a MAC protocol. This programmable protocol can be remotely injected and executed on running network devices allowing on-the-fly MAC reconfigurations.
This work aim to obtain a formal description of the a software defined wireless network requirements and define a mechanism for a reliable MAC program code mobility throw the network elements, transparently to the upper-level and supervised by a global con- trol logic that optimizes the radio resource usage; it extends a single protocol paradigm implementation to a programmable protocol abstraction and redefines the overall wire- less network view with support for cognitive adaptation mechanisms. The envisioned solutions have been supported by real experiments running on different WMP proto- types , showing the benefits given by a medium control infrastructure which is dynamic, message-oriented and reconfigurable.Mobile networks for Internet Access are a fundamental segment of Internet access net- works, where resource optimization are really critical because of the limited bandwidth availability. While traditionally resource optimizations have been focused on high effi- cient modulation and coding schemes, to be dynamically tuned according to the wireless channel and interference conditions, it has also been shown how medium access schemes can have a significant impact on the network performance according to the application and networking scenarios. This thesis work proposes an architectural solution for supporting Medium Access Con- trol (MAC) reconfigurations in terms of dynamic programming and code mobility. Since the MAC protocol is usually implemented in firmware/hardware (being constrained to very strict reaction times and to the rules of a specific standard), our solution is based on a different wireless card architecture, called Wireless MAC Processor (WMP), where standard protocols are replaced by standard programming interfaces. The control architecture developed in this thesis exploits this novel behavioral model of wireless cards for extending the network intelligence and enabling each node to be remotely reprogrammed by means a so called “MAC Program”, i.e. a software element that defines the description of a MAC protocol. This programmable protocol can be remotely injected and executed on running network devices allowing on-the-fly MAC reconfigurations. This work aim to obtain a formal description of the a software defined wireless network requirements and define a mechanism for a reliable MAC program code mobility throw the network elements, transparently to the upper-level and supervised by a global con- trol logic that optimizes the radio resource usage; it extends a single protocol paradigm implementation to a programmable protocol abstraction and redefines the overall wire- less network view with support for cognitive adaptation mechanisms. The envisioned solutions have been supported by real experiments running on different WMP proto- types , showing the benefits given by a medium control infrastructure which is dynamic, message-oriented and reconfigurable.
Livres sur le sujet "Core Reconfiguration"
1
Clark, Gordon L., et Ashby H. B. Monk. Reframing Finance. Oxford University Press, 2017. http://dx.doi.org/10.1093/oso/9780198793212.003.0011.
Texte intégralRésumé :
In the concluding chapter, Chapter 11, we summarize the various methods that asset-owning investors might consider applying when they are endeavouring to catalyse change and innovate prudently. They can achieve this by viewing the world through the lens of those institutional investors who search for organizational innovation and reconfiguration to meet their long-term objectives in a challenging world. The objectives of Chapter 11, and indeed of the whole book, have been to remind investors of their core functions and to show them how they can best take charge of their futures. This chapter lays down plans for how asset owners might mobilize their innovative ideas and, indeed, persuade their boards to resource them appropriately.
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Davie, Grace. Religion, Territory, and Choice. Oxford University Press, 2017. http://dx.doi.org/10.1093/oso/9780198798071.003.0017.
Texte intégralRésumé :
This core of this chapter describes and explains a paradox in the religious life of modern Europe: without doubt, Europe is more secular than it used to be, but in terms of public debate, religion is rising rather than falling in significance. The factors that lie behind this seeming contradiction are explored both singly and together. They include deeply embedded cultural factors, the shifts in the historic churches, new forms of religious life, new arrivals, and secular reactions. In each case, the comparison with the American case is carefully considered. The initial sections of the chapter set this comparison in a global context, noting key dates in the reconfiguration of the modern world order and the place of religion in these. The chapter concludes with a brief consideration of the British case—pulled structurally towards Europe and culturally towards the United States.
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Cassis, Youssef. Introduction. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780198817314.003.0001.
Texte intégralRésumé :
The introductory chapter provides a historical perspective to the discussion of international centres after the Global Financial Crisis and Brexit. It addresses three sets of questions. The first concerns the definition and ranking of international financial centres; the second concerns the effects, over the long run, of global financial crises on international financial centres, in terms of rise, decline, recovery, and reconfiguration; and the third concerns the ability of international financial centres to reinvent themselves in the face of new adverse conditions. The last set of questions is relevant to the likely effects of Brexit, and takes into account the fact that, historically, leading economic powers have always given rise to a major financial centre. The final part of the introduction is devoted to a presentation, against this historical background, of the eight core chapters of the book.
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Mulloy, Garren. Defenders of Japan. Oxford University Press, 2021. http://dx.doi.org/10.1093/oso/9780197606155.001.0001.
Texte intégralRésumé :
Japan's post-war armed forces are a paradox, both embarrassing remnants of the past and valuable repositories of experience. This book charts the development of the Japan Self-Defense Forces (JSDF) from 1954 as both unorthodox military institutions and servants of a civil society that decries militarism. Investigating JSDF contributions to Japanese and global security, the evolution of such contributions during and after the Cold War, and their possible reconfiguration for Japan's security needs ahead, Garren Mulloy offers insight into the Forces' past, present and future. He explores the characteristics and contradictions of Japanese policy, including novel approaches in response to an increasingly assertive China, the latent threat of North Korea and contributory pressure from the US. Though the American alliance remains the core of Japanese security, new partnerships and international overtures will also shape the Forces' place in Prime Minister Abe's new vision of 'proactive contributions to peace'. Defenders of Japan deconstructs how the JSDF have adapted and will continue to adapt within domestic norms, caught between unresolved legacies of Japan's imperial past and a dynamically shifting balance of future global power.
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de Guzman, Maria Rosario T., Jill Brown et Carolyn Pope Edwards, dir. Parenting From Afar and the Reconfiguration of Family Across Distance. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780190265076.001.0001.
Texte intégralRésumé :
The definition of family as a conjugal group consisting of parents and children living in the same household is in the process of a profound reworking, one that includes the constellation of family life that exists around the world. Increased migration and mobility have challenged traditional notions of what constitutes a family, yet much mainstream research relies on past notions of a cohesive unit under one domicile. Many families today are separated across distance and maintain ties in a multitude of ways. And although researchers have increasingly paid attention to this new picture of the family, much of this work has focused on transnational families separated in the context of overseas economic migration. In fact, family separation and long-distance parenting result from a multitude of reasons undertaken in various circumstances. This volume presents work from scholars who collectively show reasons that motivate parenting across distance, how families cope with separation and maintain ties, the impact of separation on family members, and how family is redefined and reconfigured in these various settings. By better understanding how we parent from a distance, this volume synthesizes ideas of kinship, relationships, and bonding and helps readers broaden their own ideas of parenting and family life.
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Sciuto, Jenna Grace. Policing Intimacy. University Press of Mississippi, 2021. http://dx.doi.org/10.14325/mississippi/9781496833440.001.0001.
Texte intégralRésumé :
Policing Intimacy analyzes literary depictions of sexual policing of the color line across multiple spaces with diverse colonial histories: Mississippi through William Faulkner’s work, Louisiana through Ernest Gaines’s novels, Haiti through the work of Marie Chauvet and Edwidge Danticat, and the Dominican Republic through writing by Julia Alvarez, Junot Díaz, and Nelly Rosario. This literature exposes the continuing coloniality that links depictions of U.S. democracy with Caribbean dictatorships in the twentieth century, revealing a set of interrelated features characterizing the transformation of colonial forms of racial and sexual control into neocolonial reconfigurations. Patterns are discernable, as a result of systemic inequality and large-scale historical events, revealing the ways in which private relations can reflect national occurrences and the intimate can be brought under public scrutiny. Acknowledging the widespread effects of racial and sexual policing that persist in current legal, economic, and political infrastructures across the circum-Caribbean can in turn bring to light permutations of resistance to the violent discriminations of the status quo. By drawing on colonial documents, such as early law systems like the 1685 French Code Noir instated in Haiti, the 1724 Code Noir in Louisiana, and the 1865 Black Code in Mississippi, in tandem with examples drawn from twentieth-century literature, Policing Intimacy humanizes the effects of legal histories and leaves space for local particularities. A focus on literary texts and the affordances enabled by the variances in form and aesthetics demonstrates the necessity of incorporating multiple stories, histories, and traumas into our accounts of the past.
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Champion, Michael W. Dorotheus of Gaza and Ascetic Education. Oxford University PressOxford, 2022. http://dx.doi.org/10.1093/oso/9780198869269.001.0001.
Texte intégralRésumé :
Abstract Dorotheus of Gaza and Ascetic Education approaches fundamental questions about the role and function of education in late antiquity through a detailed study of the thought of Dorotheus of Gaza, a sixth-century Palestinian monk. It illumines the thought of a significant figure in Palestinian monasticism, clarifies relationships between ascetic and classical education, and contributes to debates about how different educational projects related to late-antique cultural change. Dorotheus appropriates and reconfigures classical discourses of rhetoric, philosophy, and medicine and builds on earlier ascetic traditions. Education is a powerful site for the reconfiguration and reproduction of culture, and Dorotheus’ educational programme can be read as a microcosm of the wider culture he aims to construct partly through his adaptation and representation of classical and ascetic discourses. Key features of his educational programme include the role of the notion of godlikeness, the governing role of humility as an epistemic virtue intended to organize affective and ethical development, and his notion of education as life-long habituation. For Dorotheus, education is irreducibly affective and transformative, rather than merely informative, at the individual and communal scales. His epistemology and ethics are set within an account of the divine plan of salvation which is intended to provide a narrative framework through which his students come to understand the world and their place in it. His account of ways of knowing and ordering knowledge, ethics and moral development, emotions of education, and relationships between affect, cognition, and ethical action aims towards transformation of his students and their communities.
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White, Bretton. Staging Discomfort. University Press of Florida, 2020. http://dx.doi.org/10.5744/florida/9781683401544.001.0001.
Texte intégralRésumé :
Staging Discomfort examines how queer bodies are theatrically represented on the Cuban stage in order to re-evaluate the role of categorization as one of the state’s primary revolutionary tools. These performances concentrate on an aesthetics of fluidity, and thus upset traditional understandings of performer and spectator, and what constitutes the ideal Cuban citizenry. New affective modes are produced when performing bodies highlight—often in uncomfortably intimate, grotesque, or raw ways—the unavoidability of spectators’ bodies, and their capacity for queerness. Here the imagining of new continuities and subjectivities can lead to a reconfiguration of forms of Cuban citizenship. The affective responses from the closeness experienced in the performances in Staging Discomfort are challenges to the Cuban state’s self-designated role as primary provider for the needs of its citizens’ bodies. Through the lens of queer theory, the manuscript explores the body’s centrality to the state’s deployment of fear to successfully marginalize gay life, which this group of works seeks to defuse through an articulation of intimacies, shame, the death drive, cruising, and failure. These affective experiences shape Cuban subjectivities that emerge out of queerness, but whose focus on inclusivity necessarily involves all Cubans. Several of the central questions that guide Staging Discomfort are: How is Cuban theater agile in its critiques considering the state’s limitations on expression? How do queer performances allow for new understandings about the effects of the state’s failing socialist utopian contract with its citizens? And, can Cuban bodies that come together in queer ways re-imagine Cuban citizenship?
Chapitres de livres sur le sujet "Core Reconfiguration"
1
Xiao, Liangjun, et Limin Liu. « The SoC Reconfiguration with Single MPU Core ». Dans Advances in Intelligent and Soft Computing, 219–22. Berlin, Heidelberg : Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-29390-0_36.
Texte intégral
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Tambara, Lucas A., Jimmy Tarrillo, Fernanda L. Kastensmidt et Luca Sterpone. « Fault-Tolerant Manager Core for Dynamic Partial Reconfiguration in FPGAs ». Dans FPGAs and Parallel Architectures for Aerospace Applications, 121–33. Cham : Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-14352-1_9.
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Lakhdhar, Wafa, Rania Mzid, Mohamed Khalgui et Georg Frey. « Portable Synthesis of Multi-core Real-Time Systems with Reconfiguration Constraints ». Dans Communications in Computer and Information Science, 165–85. Cham : Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-22559-9_8.
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Waez, Md Tawhid Bin, Andrzej Wąsowski, Juergen Dingel et Karen Rudie. « Synthesis of a Reconfiguration Service for Mixed-Criticality Multi-Core Systems : An Experience Report ». Dans Formal Aspects of Component Software, 162–80. Cham : Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-15317-9_10.
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Bos, Herbert, et Bart Samwel. « The OKE Corral : Code Organisation and Reconfiguration at Runtime Using Active Linking ». Dans Active Networks, 32–47. Berlin, Heidelberg : Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-36199-5_3.
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Strohmaier, Alena. « On the Re-Configurations of Cinematic Media-Spaces : From Diaspora Film to Postdiaspora Film ». Dans Re-Configurations, 217–31. Wiesbaden : Springer Fachmedien Wiesbaden, 2020. http://dx.doi.org/10.1007/978-3-658-31160-5_14.
Texte intégralRésumé :
Zusammenfassung This chapter analyzes the formation of the (self-applied) designation “Iranian diaspora” and its cinematic representations. The Iranian diaspora and its filmmaking are suitable objects of investigation because they can be used to illustrate two transformations, both of diaspora into postdiaspora and diaspora film into postdiaspora film. This reconfiguration manifests itself spatially on three levels: the real space of the diaspora, which is subject to socio-political changes; the internal-diegetic spaces in the films themselves, which constantly bring new themes to the fore; and film as a space-creating instance in itself, which constantly updates its own mediality. In Iranian (post-)diaspora film, these different spatial dimensions come together, as illustrated by this chapter’s analysis of Ana Lily Amirpour’s A Girl Walks Home Alone at Night (USA, 2014).
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Clegg, Ben, et Mario Binder. « Managing the Dynamic Reconfiguration of Enterprises ». Dans IT Outsourcing, 387–97. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-60566-770-6.ch024.
Texte intégralRésumé :
Due to environmental changes and business trends such as globalisation, outsourcing and virtualisation, more and more companies get involved in business activities that are outside their direct control. This typically occurs by entering into collaborative relationships and joint ventures with specialised companies in order to fulfil the demands of customers quickly (DiMaggio, 2001). Organisational structures that results from such collaborative relationships and joint ventures are referred to in this paper as enterprises and the management of them known as enterprise management. The authors use the definition of the European Commission (2003) that defines an enterprise as “… an entity, regardless of its legal form … including partnerships or associations regularly engaged in economic activities.” Therefore in its most simple form an enterprise could be a single integrated company. However, findings from this research show that enterprises can also be made up of parts of different companies and the structure of the enterprise is contingent upon a variety of different factors. The success of the enterprise as a collaborative venture depends on the ability of companies to intermediate their internal core competencies into other participating companies’ value streams and simultaneously outsource their own peripheral activities to companies that can perform them quicker, cheaper, and more effectively (Lal et al., 1995). In other words, the peripheral activities of one member-company must be complemented by a core competence of another member-company within an overall enterprise.
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Busemeyer, Marius R., Achim Kemmerling, Paul Marx et Kees van Kersbergen. « Digitalization and the Welfare State ». Dans Digitalization and the Welfare State, 1–20. Oxford University Press, 2022. http://dx.doi.org/10.1093/oso/9780192848369.003.0001.
Texte intégralRésumé :
This chapter introduces the volume’s research questions, goal, and approach, as well as the various contributing chapters. The overarching research question of this volume is: to what extent and how will the politics and policies of welfare states respond to the new challenges of digitalization? The chapter outlines two constituent sub-questions. First, to what extent and under what conditions will digitalization trigger a (paradigmatic) reconfiguration of the welfare state’s policy space? Second, to what extent and under what conditions will digitalization generate a reconfiguration of the welfare state’s political space? Besides defining the core research questions of the volume, this chapter also provides definitions of core terms and discusses the various dimensions of technological change that are usually subsumed under the term digitalization.
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Cunha, Maria Manuela. « Environments for VE Integration ». Dans IT Outsourcing, 1020–29. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-60566-770-6.ch062.
Texte intégralRésumé :
Most definitions of virtual enterprise (VE) incorporate the idea of extended and collaborative outsourcing to suppliers and subcontractors in order to achieve a competitive response to market demands (Webster, Sugden, & Tayles, 2004). As suggested by several authors (Browne & Zhang, 1999; Byrne, 1993; Camarinha- Matos & Afsarmanesh, 1999; Cunha, Putnik, & Ávila, 2000; Davidow & Malone, 1992; Preiss, Goldman, & Nagel, 1996), a VE consists of a network of independent enterprises (resources providers) with reconfiguration capability in useful time, permanently aligned with the market requirements, created to take profit from a specific market opportunity, and where each participant contributes with her best practices and core competencies to the success and competitiveness of the structure as a whole. Even during the operation phase of the VE, the configuration can change to assure business alignment with the market demands, traduced by the identification of reconfiguration opportunities and constant readjustment or reconfiguration of the VE network to meet unexpected situations or to keep permanent competitiveness and maximum performance (Cunha & Putnik, 2002, 2005a, 2005b)
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Cunha, Maria Manuela, Goran D. Putnik et Paulo Silva Ávila. « Market of Resources for Virtual Enterprise Integration ». Dans Networking and Telecommunications, 220–26. IGI Global, 2010. http://dx.doi.org/10.4018/978-1-60566-986-1.ch017.
Texte intégralRésumé :
Most definitions of virtual enterprise (VE) incorporate the idea of extended and collaborative outsourcing to suppliers and subcontractors in order to achieve a competitive response to market demands (Webster, Sugden, & Tayles, 2004). As suggested by several authors (Browne & Zhang, 1999; Byrne, 1993; Camarinha-Matos & Afsarmanesh, 1999; Cunha, Putnik, & Ávila, 2000; Davidow & Malone, 1992; Preiss, Goldman, & Nagel, 1996), a VE consists of a network of independent enterprises (resources providers) with reconfiguration capability in useful time, permanently aligned with the market requirements, created to take profit from a specific market opportunity, and where each participant contributes with its best practices and core competencies to the success and competitiveness of the structure as a whole. Even during the operation phase of the VE, the configuration can change, to assure business alignment with the market demands, traduced by the identification of reconfiguration opportunities and continuous readjustment or reconfiguration of the VE network, to meet unexpected situations or to keep permanent competitiveness and maximum performance (Cunha & Putnik, 2002, 2005a, 2005b).
Actes de conférences sur le sujet "Core Reconfiguration"
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Huiban, Gurvan, et Pallab Datta. « Multi-metrics reconfiguration in core WDM networks ». Dans 2007 6th International Workshop on Design and Reliable Communication Networks (DRCN). IEEE, 2007. http://dx.doi.org/10.1109/drcn.2007.4762260.
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Dhar, Ashutosh, et Deming Chen. « Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration ». Dans 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2017. http://dx.doi.org/10.1109/fccm.2017.59.
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Heid, Kris, Jan Weber et Christian Hochberger. « μStreams : a tool for automated streaming pipeline generation on soft-core processors ». Dans 2016 International Conference on FPGA Reconfiguration for General-Purpose Computing (FPGA4GPC). IEEE, 2016. http://dx.doi.org/10.1109/fpga4gpc.2016.7518530.
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Chen, Deming. « Optimizations in GPU : Smart compilers and core-level reconfiguration ». Dans 2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP). IEEE, 2013. http://dx.doi.org/10.1109/slip.2013.6681686.
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Suri, T., et A. Aggarwal. « Improving scalability and per-core performance in multi-cores through resource sharing and reconfiguration ». Dans 2009 22nd International Conference on VLSI Design. IEEE, 2009. http://dx.doi.org/10.1109/vlsi.design.2009.58.
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Li, Zheng, Shuibing He et Li Wang. « Prediction Based Run-Time Reconfiguration on Many-Core Embedded Systems ». Dans 2017 IEEE International Conference on Computational Science and Engineering (CSE) and IEEE International Conference on Embedded and Ubiquitous Computing (EUC). IEEE, 2017. http://dx.doi.org/10.1109/cse-euc.2017.210.
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Murgida, Matteo, Alessandro Panella, Vincenzo Rana, Marco Santambrogio et Donatella Sciuto. « Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow ». Dans 2006 IFIP International Conference on Very Large Scale Integration. IEEE, 2006. http://dx.doi.org/10.1109/vlsisoc.2006.313207.
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Hsu, Po-Yang, et TingTing Hwang. « Thread-criticality aware dynamic cache reconfiguration in multi-core system ». Dans 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, 2013. http://dx.doi.org/10.1109/iccad.2013.6691151.
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Nithya, R., K. R. Sarath Chandran et V. Premanand Chandramani. « Run-time reconfiguration of Processing Elements through soft-core processor ». Dans 2014 International Conference on Communications and Signal Processing (ICCSP). IEEE, 2014. http://dx.doi.org/10.1109/iccsp.2014.6949956.
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Ohkawa, Takeshi, Ikuta Tanigawa, Mikiko Sato, Kenji Hisazumi, Nobuhiko Ogura et Harumi Watanabe. « Prototype of FPGA Dynamic Reconfiguration Based-on Context-Oriented Programming ». Dans 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC). IEEE, 2019. http://dx.doi.org/10.1109/mcsoc.2019.00024.
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