Littérature scientifique sur le sujet « Contrôleurs Mémoire »
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Articles de revues sur le sujet "Contrôleurs Mémoire"
Lavoie, Marc E., Julie Champagne, Emma Glaser et Adrianna Mendrek. « Mémoire émotionnelle et activités électrocorticales en schizophrénie ». Santé mentale au Québec 41, no 1 (5 juillet 2016) : 85–121. http://dx.doi.org/10.7202/1036967ar.
Texte intégralJewsiewicki, Bogumil. « Photographie, un objet du pouvoir ». Anthropologie et Sociétés 40, no 1 (18 mai 2016) : 219–50. http://dx.doi.org/10.7202/1036378ar.
Texte intégralWinn, Colette H., et Hélène Camille Martin. « Marie Stuart, Lettres de la dernière heure. Contribution à l’étude d’un « sous-genre » oublié ». Renaissance and Reformation 41, no 1 (19 avril 2018) : 55–88. http://dx.doi.org/10.33137/rr.v41i1.29521.
Texte intégralAllen, Maude, Rose Bourget, Alessa Luis-Lavertue, Celia Matte-Gagné et Jessyka Beauregard-Blouin. « Sensibilité paternelle et fonctions exécutives chez l’enfant : effet modérateur du sexe de l’enfant ». Psycause : revue scientifique étudiante de l'École de psychologie de l'Université Laval 12, no 2 (25 janvier 2023) : 6–8. http://dx.doi.org/10.51656/psycause.v12i2.51853.
Texte intégralOjoga, Ecaterina. « The Archives of Communism in the Republic of Moldova : Between Ideology and Political Memory ». Slovo Unlabeled volume, Archives et mémoires (23 mai 2023). http://dx.doi.org/10.46298/slovo.2023.11349.
Texte intégralMartig, Alexis. « Esclavage contemporain ». Anthropen, 2018. http://dx.doi.org/10.17184/eac.anthropen.085.
Texte intégralFresia, Marion. « Réfugiés ». Anthropen, 2017. http://dx.doi.org/10.17184/eac.anthropen.049.
Texte intégralThèses sur le sujet "Contrôleurs Mémoire"
Sarni, Toufik. « Vers une mémoire transactionnelle temps réel ». Phd thesis, Université de Nantes, 2012. http://tel.archives-ouvertes.fr/tel-00750637.
Texte intégralLisboa, malaquias Felipe. « CoqDRAM - A Foundation for Designing Formally Proven Memory Controllers ». Electronic Thesis or Diss., Institut polytechnique de Paris, 2024. http://www.theses.fr/2024IPPAT020.
Texte intégralRecently proposed real-time memorycontrollers tackle the performance-predictability tradeoffby trying to offer the best of both worlds. However,as a consequence, designs have become complexand often present mathematical developmentsthat are lengthy, hard to read and review, incomplete,and rely on unclear assumptions. Given thatsuch components are often designed as part microarchitecturesthat are used in safety-critical real-timesystems, a high degree of confidence that systemsbehave correctly is required in order to meet certificationgoals. To address that problem, we proposea new framework written in the Coq theorem provernamed CoqDRAM, in which we model DRAM devicesand controllers and their expected behaviour asa formal specification. The framework is intended toaid the design of correct-by-construction, trustworthyDRAM scheduling algorithms. The CoqDRAM specificationcaptures correctness criteria according to theJEDEC standards and states other high-level properties,such as fairness and sequential consistency. Followingsuch approach, paper-and-pencil mathematicaldevelopments are replaced by machine-checkedproofs, which increase confidence that the design isindeed correct.We showcase CoqDRAM’s usability bymodelling and proving two proof of concept schedulingalgorithms: one based on the First-in First-Out (FIFO) arbitration policy and the other on Time-Division Multiplexing (TDM). Moreover, using Coq-DRAM, we propose a new DRAM scheduling algorithmcalled TDMShelve, which extends and improvesprevious work on work-conserving dynamic TDM arbitration.More specifically, TDMShelve exploits informationabout the internal state of the memory at requestscheduling level, thus providing a good balancebetween predictability and average-case latency formixed-criticality real-time systems. Finally, we connectthe algorithms written in CoqDRAM to software andhardware simulation environments. These environmentsare used to perform simulation runs that furthervalidate the correctness of the CoqDRAM model
Gao, Yang. « Contrôleur de cache générique pour une architecture manycore massivement parallèle à mémoire partagée cohérente ». Paris 6, 2011. http://www.theses.fr/2011PA066296.
Texte intégralHassan, Khaldon. « Architecture De Contrôleur Mémoire Configurable et Continuité de Service Pour l'Accès à la Mémoire Externe Dans Les Systèmes Multiprocesseurs Intégrés à Base de Réseaux Sur Puce ». Phd thesis, Université de Grenoble, 2011. http://tel.archives-ouvertes.fr/tel-00656470.
Texte intégralKhaldon, Hassan. « Architecture de contrôleur mémoire configurable et continuité de service pour l'accès à la mémoire externe dans les systèmes multiprocesseurs intégrés à base de réseaux sur puce ». Thesis, Grenoble, 2011. http://www.theses.fr/2011GRENT051/document.
Texte intégralThe ongoing advancements in VLSI technology allow System-on-Chip (SoC) to integrate many heterogeneous functions into a single chip, but still demand, because of economical constraints, a single and shared main off-chip SDRAM. Consequently, main memory system design, and more specifically the architecture of the memory controller, has become an increasingly important factor in determining the overall system performance. Choosing a memory controller design that meets the needs of the whole system is a complex issue. This requires the exploration of the memory controller architecture, and then the validation of each configuration by simulation. Although the architecture exploration of the memory controller is a key to successful system design, state of the art memory controllers are not as flexible as necessary for this task. Even if some of them present a configurable architecture, the exploration is restricted to limited sets of parameters such as queue depth, data bus size, quality-of-service level, and bandwidth distribution. Several classes of traffic co-exist in real applications, e.g. best effort traffic and guaranteed service traffic, and access the main memory. Therefore, considering the interaction between the memory subsystem and the interconnection system has become vital in today's SoCs. Many on chip networks provide guaranteed services to traffic classes to satisfy the applications requirements. However, very few studies consider the SDRAM access within a system approach, and take into account the specificity of the SDRAM access as a target in NoC-based SoCs. This thesis addresses the topic of dynamic access to SDRAM in NoC-based SoCs. We introduce a totally customizable memory controller architecture based on fully configurable building components and design a high level cycle approximate model for it. This enables the exploration of the memory subsystem thanks to the ease of configuration of the memory controller architecture. Because of the discontinuity of services between the network and the memory controller, we also propose within the framework of this thesis an Extreme End to End flow control protocol to access the memory device through a multi-port memory controller. The simple yet novel idea is to exploit information about the memory controller status in the NoC. Experimental results show that by controlling the best effort traffic injection in the NoC, our protocol increases the performance of the guaranteed service traffic in terms of bandwidth and latency, while maintaining the average bandwidth of the best effort traffic
Vandenhove, Pierre. « Strategy complexity of zero-sum games on graphs ». Electronic Thesis or Diss., université Paris-Saclay, 2023. http://www.theses.fr/2023UPASG029.
Texte intégralWe study two-player zero-sum turn-based games on graphs, a framework of choice in theoretical computer science. Such games model the possibly infinite interaction between a computer system (often called reactive) and its environment. The system, seen as a player, wants to guarantee a specification (translated to a game objective) based on the interaction; its environment is seen as an antagonistic opponent. The aim is to automatically synthesize a controller for the system that guarantees the specification no matter what happens in the environment, that is, a winning strategy in the derived game.A crucial question in this synthesis quest is the complexity of strategies: when winning strategies exist for a game objective, how simple can they be, and how complex must they be? A standard measure of strategy complexity is the amount of memory needed to implement winning strategies for a given game objective. In other words, how much information should be remembered about the past to make optimal decisions about the future? Proving the existence of bounds on memory requirements has historically had a significant impact. Such bounds were, for instance, used to show the decidability of monadic second-order theories, and they are at the core of state-of-the-art synthesis algorithms. Particularly relevant are the finite-memory-determined objectives (for which winning strategies can be implemented with finite memory), as they allow for implementable controllers. In this thesis, we seek to further the understanding of finite-memory determinacy. We divide our contributions into two axes.First, we introduce arena-independent finite-memory determinacy, describing the objectives for which a single automatic memory structure suffices to implement winning strategies in all games. We characterize this property through language-theoretic and algebraic properties of objectives in multiple contexts (games played on finite or infinite graphs). We show in particular that understanding the memory requirements in one-player game graphs (i.e., the simpler situation of games where the same player controls all the actions) usually leads to bounds on memory requirements in two-player zero-sum games. We also show that if we consider games played on infinite game graphs, the arena-independent-finite-memory-determined objectives are exactly the omega-regular objectives, providing a converse to the landmark result on finite-memory determinacy of omega-regular objectives. These results generalize previous works about the class of objectives requiring no memory to implement winning strategies.Second, we identify natural classes of objectives for which precise memory requirements are surprisingly not fully understood. We introduce regular objectives (a subclass of the omega-regular objectives), which are simple objectives derived from regular languages. We effectively characterize their memory requirements for each player, and we study the computational complexity of deciding the existence of a small memory structure. We then move a step up in the complexity of the objectives and consider objectives definable with deterministic Büchi automata. We characterize the ones for which the first player needs no memory to implement winning strategies (a property called half-positionality). Thanks to this characterization, we show that half-positionality is decidable in polynomial time for this class of objectives. These results complement seminal results about memory requirements of classes of omega-regular objectives
Messaoudi, Kamel. « Traitement des signaux et images en temps réel : "implantation de H.264 sur MPSoC" ». Phd thesis, Université de Bourgogne, 2012. http://tel.archives-ouvertes.fr/tel-00905872.
Texte intégralLivres sur le sujet "Contrôleurs Mémoire"
Bréard, Jacques-Michel. Réponse du Sieur Bréard, ci-devant contrôleur de la marine à Québec aux mémoires de M. Bigot, & du Sieur Pean. [S.l.] : De l'imprimerie de Moreau ..., 1986.
Trouver le texte intégralSylvie J&A. Journal de Rêves : Carnet Tracker/interprétation/rêve Lucide/contrôler Ses Rêves/bien-être/mémoire. Independently Published, 2021.
Trouver le texte intégralM, Limon. Traitants et fraudes dans le recouvrement de l'impôt : Affaires réglées par Claude Le Peletier, Contrôleur général des finances (1683-1689). Mémoire pour ... d'études approfondies d'histoire du droit. LGDJ / Montchrestien, 1995.
Trouver le texte intégralChapitres de livres sur le sujet "Contrôleurs Mémoire"
ELIAHU, Adi, Rotem BEN HUR, Ameer HAJ ALI et Shahar KVATINSKY. « mMPU, une architecture polyvalente de calcul dans la mémoire basée sur memristor ». Dans Systèmes multiprocesseurs sur puce 1, 155–69. ISTE Group, 2023. http://dx.doi.org/10.51926/iste.9021.ch6.
Texte intégralKnight, David B. « L'État et les stratégies du territoire ». Dans Mémoires et documents de géographie, 27–32. CNRS Éditions, 1991. http://dx.doi.org/10.3917/cnrs.thery.1991.01.0027.
Texte intégralBERTUCCI, Marie-Madeleine, et Mounia ILLOURMANNE. « Transcrire un corpus audio dans la perspective de la préservation du patrimoine culturel immatériel. » Dans Corpus audiovisuels, 115–24. Editions des archives contemporaines, 2022. http://dx.doi.org/10.17184/eac.5704.
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