Bibliographies thématiques / CMOS VOLTAGE FOLLOWER

Littérature scientifique sur le sujet « CMOS VOLTAGE FOLLOWER »

Auteur : Grafiati
Publié le 11 septembre 2023

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Articles de revues sur le sujet "CMOS VOLTAGE FOLLOWER"

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Tanno, K., H. Matsumoto, O. Ishizuka et Zheng Tang. « Simple CMOS voltage follower with resistive-load drivability ». IEEE Transactions on Circuits and Systems II : Analog and Digital Signal Processing 46, no 2 (1999) : 172–77. http://dx.doi.org/10.1109/82.752947.

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Kasemsuwan, Varakorn, et Weerachai Nakhlo. « A simple rail‐to‐rail CMOS voltage follower ». Microelectronics International 26, no 1 (23 janvier 2009) : 17–21. http://dx.doi.org/10.1108/13565360910923124.

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Ramírez-Angulo, Jaime, Anindita Paul, Manaswini Gangineni, Jose Maria Hinojo-Montero et Jesús Huerta-Chua. « Class AB Voltage Follower and Low-Voltage Current Mirror with Very High Figures of Merit Based on the Flipped Voltage Follower ». Journal of Low Power Electronics and Applications 13, no 2 (24 avril 2023) : 28. http://dx.doi.org/10.3390/jlpea13020028.

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The application of the flipped voltage follower to implement two high-performance circuits is presented: (1) The first is a class AB cascode flipped voltage follower that shows an improved slew rate and an improved bandwidth by very large factors and that has a higher output range than the conventional flipped voltage follower. It has a small signal figure of merit FOMSS = 46 MHz pF/µW and a current efficiency figure of merit FOMCE = 118. This is achieved by just introducing an additional output current sourcing PMOS transistor (P-channel Metal Oxide Semiconductor Field Effect Transistor) that provides dynamic output current enhancement and increases the quiescent power dissipation by less than 10%. (2) The other is a high-performance low-voltage current mirror with a nominal gain accuracy better than 0.01%, 0.212 Ω input resistance, 112 GΩ output resistance, 1 V supply voltage requirements, 0.15 V input, and 0.2 V output compliance voltages. These characteristics are achieved by utilizing two auxiliary amplifiers and a level shifter that increase the power dissipation just moderately. Post-layout simulations verify the performance of the circuits in a commercial 180 nm CMOS (Complementary Metal Oxide Semiconductor) technology.
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Thanapitak, Surachoke, Prajuab Pawarangkoon et Chutham Sawigun. « A Flipped Voltage Follower Second-Order Bandpass Filter ». Journal of Circuits, Systems and Computers 26, no 07 (17 mars 2017) : 1750112. http://dx.doi.org/10.1142/s0218126617501122.

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This paper presents a compact second-order bandpass filter developed by combining the well-known flipped voltage follower circuit as a transconductance network with two capacitors. Operated in the subthreshold region, the filter’s center frequency can be adjusted linearly by varying the bias current. Post-layout simulation using a 0.35-[Formula: see text]m CMOS process confirms the suitability of the proposed filter in low-voltage, low-power environment.
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Ocampo-Hidalgo, J. J., J. Alducín-Castillo, I. Vázquez-Álvarez, L. N. Oliva-Moreno et J. E. Molinar-Solís. « A CMOS Low-Voltage Super Follower Using Quasi-Floating Gate Techniques ». Journal of Circuits, Systems and Computers 27, no 07 (26 mars 2018) : 1850111. http://dx.doi.org/10.1142/s0218126618501116.

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A quasi-floating gate (QFG) “super-follower” is presented. The high resistance used by the QFG transistor is constructed by two diodes connected back-to-back, leading to a simple-, temperature-stable- and small-area solution. Expressions for the behavior of the follower are introduced and verified by circuit simulations in LTSPICE using 0.5[Formula: see text][Formula: see text]m CMOS process models, which show an improved performance of the proposed circuit with respect to the original super-follower. To prove the principle, a test cell was fabricated in the same 0.5[Formula: see text][Formula: see text]m CMOS technology and characterized. Measurement results show a gain-bandwidth product of 10[Formula: see text]MHz and power consumption of 120[Formula: see text][Formula: see text]W with a 1.5[Formula: see text]V single supply.
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Rajesh, Durgam, Subramanian Tamil, Nikhil Raj et Bharti Chourasia. « Low-voltage bulk-driven flipped voltage follower-based transconductance amplifier ». Bulletin of Electrical Engineering and Informatics 11, no 2 (1 avril 2022) : 765–71. http://dx.doi.org/10.11591/eei.v11i2.3306.

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A low voltage high performance design of operational transconductance amplifier is proposed in this paper. The proposed architecture is based on bulk driven quasi-floating gate metal oxide semiconductor field effect transistor (MOSFET) which supports low voltage operation and improves the gain of the amplifier. Besides to this the tail current source requirement of operational transconductance amplifier (OTA) is removed by using the flipped voltage follower structure at the input pair along with bulk driven quasi-floating gate MOSFET. The proposed operational transconductance amplifier shows a five-fold increase in direct current (DC) gain and 3-fold increase in unity gain bandwidth when compared with its conventional bulk driven architecture. The metal oxide semiconductor (MOS) model used for amplifier design is of 0.18 um complementary metal oxide semiconductor (CMOS) technology at supply of 0.5 V.
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SAKUL, CHAIWAT, et KOBCHAI DEJHAN. « FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS ». Journal of Circuits, Systems and Computers 21, no 03 (mai 2012) : 1250024. http://dx.doi.org/10.1142/s0218126612500247.

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This paper describes squaring and square-rooting circuits operable on low voltage supplies, with their application proposed hereby as vector-summation and four-quadrant multiplier circuits. These circuits make use of a flipped voltage follower (FVF) as fundamental circuit. A detail classification of basic topologies derived from the FVF is given. The proposed circuits have simple structure, wide input range and low power consumption as well as small number of devices. All circuits are also examined and supported by a set of simulations with PSpice program. The circuits can operate at power supply of ±0.7 volts, the input voltage range of the squaring circuit is ±0.8 volts with 1.59% relative error and 1.78 μW power dispersion, the input current of the square-rooting circuit is about 50 μA with 0.55% relative error and 1.4 μW power dispersion and the vector-summation circuit have linearity error of 0.23% and 2.92 μW power dispersion. As in four-quadrant multiplier circuit, the total harmonic distortion of the multiplier is less than 1.2% for 0.8 VP-P input signal at 1 MHz fundamental frequency. Experimental result is carried out to confirm the operation by using commercial CMOS transistor arrays (CD4007). These circuits are highly expected to be effective in further application of the low voltage analog signal processing.
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Ocampo-Hidalgo, Juan Jesus, Iván Vázquez-Álvarez, Sergio Sandoval-Perez, Rodolfo Garcia-Lozano, Marco Gurrola-Navarro et Jesus Ezequiel Molinar-Solis. « A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique ». Ingeniería e Investigación 37, no 2 (1 mai 2017) : 82–88. http://dx.doi.org/10.15446/ing.investig.v37n2.62625.

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This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.
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Tripathi, S. K., Mohd Samar Ansari et Amit M. Joshi. « Carbon Nanotubes-Based Digitally Programmable Current Follower ». VLSI Design 2018 (17 janvier 2018) : 1–10. http://dx.doi.org/10.1155/2018/1080817.

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The physical constraints of ever-shrinking CMOS transistors are rapidly approaching atomistic and quantum mechanical limits. Therefore, research is now directed towards the development of nanoscale devices that could work efficiently in the sub-10 nm regime. This coupled with the fact that recent design trend for analog signal processing applications is moving towards current-mode circuits which offer lower voltage swings, higher bandwidth, and better signal linearity is the motivation for this work. A digitally controlled DVCC has been realized using CNFETs. This work exploited the CNFET’s parameters like chirality, pitch, and numbers of CNTs to perform the digital control operation. The circuit has minimum number of transistors and can control the output current digitally. A similar CMOS circuit with 32 nm CMOS parameters was also simulated and compared. The result shows that CMOS-based circuit requires 418.6 μW while CNFET-based circuit consumes 352.1 μW only. Further, the proposed circuit is used to realize a CNFET-based instrumentation amplifier with digitally programmable gain. The amplifier has a CMRR of 100 dB and ICMR equal to 0.806 V. The 3 dB bandwidth of the amplifier is 11.78 GHz which is suitable for the applications like navigation, radar instrumentation, and high-frequency signal amplification and conditioning.
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Ajayan, K. R., et Navakanta Bhat. « Linear transconductor with flipped voltage follower in 130 nm CMOS ». Analog Integrated Circuits and Signal Processing 63, no 2 (13 octobre 2009) : 321–27. http://dx.doi.org/10.1007/s10470-009-9396-5.

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Thèses sur le sujet "CMOS VOLTAGE FOLLOWER"

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KRISHNA, KUMMARAPALLI KOMALA. « ADAPTIVELY BIASED CMOS VOLTAGE FOLLOWER ». Thesis, 2016. http://dspace.dtu.ac.in:8080/jspui/handle/repository/15208.

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A novel CMOS adaptive biasing technique has been proposed for low power applications which can be applied to any CMOS circuit having differential current at one of its node. This technique gives an output current proportional to input differential voltage. The proposed technique can be used in low voltage high speed operational amplifiers. The dynamic bias current saves power and also improve slew rate, delay. A modified NMOS topology technique is also applied to a conventional operational amplifier to improve the slew rate. A SPICE simulation for proposed technique and modified NMOS topology technique in 0.18um CMOS technology is reported.
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Chen, Chia-Wei, et 陳伽維. « CMOS Operational Transconductance Amplifiers with Linearity Improving by Flipped Voltage Follower ». Thesis, 2010. http://ndltd.ncl.edu.tw/handle/88263891400795490238.

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碩士
國立交通大學
電信工程研究所
99
In recent years, the short channel effect has changed the way of designing analog circuits, which becomes a main issue as the technology marches to deep-submicron fields. The impact of the short channel effect on the design of the operational transconductance amplifier (OTA) becomes more serious and makes the circuit performance deviated from the ideal voltage-current equation, especially the performance of the linearity. This paper presents two fully balanced structures of CMOS Operational Transconductance Amplifier (OTA) with high linearity, and its applications to Gm-C filters. The transconductors are designed for highly linear applications using methods which reduce non-ideal small signal resistance. The proposed first circuit based on the source-degeneration structure and enhanced with modified Folded Flipped Voltage Follower and positive feedback for linearity improving was designed by the TSMC 0.18μm CMOS technology and dissipates 3.7mW power with 1.8V voltage supply. The result shows the HD3 of -70dB with 0.6Vpp 10MHz input signal. It occupies the area of 0.5mm * 0.395mm, including pads. The proposed second circuit based on the conventional pseudo-differential structure and enhanced with modified Folded Flipped Voltage Follower for linearity improving was designed by the TSMC 0.18μm CMOS technology and dissipates 0.7mW power with 1.8V voltage supply. The result shows the HD3 of -58dB with 0.6Vpp 10MHz input signal. The active area uses less than 0.01 mm2. Using this OTA as building blocks, a 5MHz Gm-C low-pass filter was designed with the HD3 of -48dB. It consumes 9.14mW and occupies the area of 0.502mm * 0.612mm, including pads.
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Chapitres de livres sur le sujet "CMOS VOLTAGE FOLLOWER"

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Srilakshmi Ravali, M., Lalitha Malladi et J. Sunilkumar. « Design and Implementation of High Speed and Large Bandwidth Voltage Follower Using CMOS Technology ». Dans Algorithms for Intelligent Systems, 855–61. Singapore : Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-6307-6_88.

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Nandy, Turja, Farhana Anwar et Ronald A. Coutu Jr. « Germanium Telluride : A Chalcogenide Phase Change Material with Many Possibilities ». Dans Phase Change Materials - Technology and Applications [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.108461.

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Germanium telluride (GeTe) is a chalcogenide phase change material which is nonvolatile and changes its phase from amorphous state to a highly conductive crystalline state at approximately 180–230°C temperature, dropping the material’s resistivity by six orders of magnitude. These temperature-induced states lead to different physical and chemical properties, making it a suitable candidate for optical storage, reconfigurable circuit, high-speed switching, terahertz (THz), and satellite applications. Besides, GeTe-based devices offer complementary metal oxide-semiconductor (CMOS) compatibility and simplified, low-cost fabrication processes. In this chapter, three applications of GeTe will be discussed. They are as follows: (1) how GeTe can be utilized as DC and RF switching material with their high OFF/ON resistivity ratio, (2) how GeTe can contribute to current THz technology as split-ring resonators and modulators, and (3) effect of threshold voltage on GeTe for reconfigurable circuits.
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Actes de conférences sur le sujet "CMOS VOLTAGE FOLLOWER"

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Padilla-Cantoya, Ivan, Jesus Ezequiel Molinar-Solis et Gladis O. Ducoudary. « Class AB low-voltage CMOS Voltage Follower ». Dans 2007 Joint 50th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) and the IEEE Northeast Workshop on Circuits and Systems (NEWCAS 2007). IEEE, 2007. http://dx.doi.org/10.1109/mwscas.2007.4488713.

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Kumngern, Montree. « CMOS differential difference voltage follower transconductance amplifier ». Dans 2015 IEEE International Circuits and Systems Symposium (ICSyS). IEEE, 2015. http://dx.doi.org/10.1109/circuitsandsystems.2015.7394080.

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Wongfoo, Surat, Weerachai Naklo, Apirak Suadet et Varakorn Kasemsuwan. « A Simple Rail-to-Rail CMOS Voltage Follower ». Dans TENCON 2006 - 2006 IEEE Region 10 Conference. IEEE, 2006. http://dx.doi.org/10.1109/tencon.2006.344015.

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Zhang, Jing. « A Low-Power and High Slew-rate CMOS Voltage Follower ». Dans 2010 International Conference on Machine Vision and Human-machine Interface. IEEE, 2010. http://dx.doi.org/10.1109/mvhi.2010.134.

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Bruno de Sa, Leonardo, et Antonio Mesquita. « Synthesis of Voltage Follower with Only CMOS Transistors Using Evolutionary Methods ». Dans 2007 2nd NASA/ESA Conference on Adaptive Hardware and Systems. IEEE, 2007. http://dx.doi.org/10.1109/ahs.2007.101.

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Satapathy, Amarjyoti, Subir Kumar Maity et Sushanta K. Mandal. « A flipped voltage follower based analog multiplier in 90nm CMOS process ». Dans 2015 International Conference on Advances in Computer Engineering and Applications (ICACEA). IEEE, 2015. http://dx.doi.org/10.1109/icacea.2015.7164767.

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Pakala, Sri Harsh, Mahender Manda, Punith R. Surkanti, Annajirao Garimella et Paul M. Furth. « Voltage buffer compensation using Flipped Voltage Follower in a two-stage CMOS op-amp ». Dans 2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2015. http://dx.doi.org/10.1109/mwscas.2015.7282199.

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Wangtaphan, Skawrat, et Varakorn Kasemsuwan. « A 0.6 volt class-AB CMOS voltage follower with bulk-driven quasi-floating gate super source follower ». Dans 2012 9th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON 2012). IEEE, 2012. http://dx.doi.org/10.1109/ecticon.2012.6254300.

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Moustakas, K., et S. Siskos. « Improved low-voltage low-power class AB CMOS current conveyors based on the flipped voltage follower ». Dans 2013 IEEE International Conference on Industrial Technology (ICIT 2013). IEEE, 2013. http://dx.doi.org/10.1109/icit.2013.6505801.

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Fayomi, Christian Jesus B., Gilson I. Wirth, Jamine Ramirez-Angulo et Akira Matsuzawa. « “The flipped voltage follower”-based low voltage fully differential CMOS sample-and-hold circuit ». Dans 2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008. IEEE, 2008. http://dx.doi.org/10.1109/iscas.2008.4541768.

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