Littérature scientifique sur le sujet « CMOS readout »
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Articles de revues sur le sujet "CMOS readout"
Yoon, Eun-Jung, Jong-Tae Park et Chong-Gun Yu. « CMOS ROIC for MEMS Acceleration Sensor ». Journal of IKEEE 18, no 1 (31 mars 2014) : 119–27. http://dx.doi.org/10.7471/ikeee.2014.18.1.119.
Texte intégralMorgenshtein, Arkadiy, Liby Sudakov-Boreysha, Uri Dinnar, Claudio G. Jakobson et Yael Nemirovsky. « CMOS readout circuitry for ISFET microsystems ». Sensors and Actuators B : Chemical 97, no 1 (janvier 2004) : 122–31. http://dx.doi.org/10.1016/j.snb.2003.08.007.
Texte intégralGAO, ZHIYUAN, SUYING YAO, JIANGTAO XU et CHAO XU. « DYNAMIC RANGE EXTENSION OF CMOS IMAGE SENSORS USING MULTI-INTEGRATION TECHNIQUE WITH COMPACT READOUT ». Journal of Circuits, Systems and Computers 22, no 06 (juillet 2013) : 1350042. http://dx.doi.org/10.1142/s0218126613500424.
Texte intégralBiswas, Subrata, Poly Kundu, Md Hasnat Kabir, Sagir Ahmed et Md Moidul Islam. « Design and Analysis of High Frame Rate Capable Active Pixel Sensor by Using CNTFET Devices for Nanoelectronics ». International Journal of Recent Contributions from Engineering, Science & ; IT (iJES) 3, no 4 (14 décembre 2015) : 20. http://dx.doi.org/10.3991/ijes.v3i4.5185.
Texte intégralRoy, Avisek, Mehdi Azadmehr, Bao Q. Ta, Philipp Häfliger et Knut E. Aasmundtveit. « Design and Fabrication of CMOS Microstructures to Locally Synthesize Carbon Nanotubes for Gas Sensing ». Sensors 19, no 19 (8 octobre 2019) : 4340. http://dx.doi.org/10.3390/s19194340.
Texte intégralZHAO, HONGLIANG, YIQIANG ZHAO, YIWEI SONG, JUN LIAO et JUNFENG GENG. « A LOW POWER CRYOGENIC CMOS ROIC DESIGN FOR 512 × 512 IRFPA ». Journal of Circuits, Systems and Computers 22, no 10 (décembre 2013) : 1340033. http://dx.doi.org/10.1142/s0218126613400331.
Texte intégralHabibi, Mehdi, Yunus Dawji, Ebrahim Ghafar-Zadeh et Sebastian Magierowski. « Nanopore-based DNA sequencing sensors and CMOS readout approaches ». Sensor Review 41, no 3 (15 juillet 2021) : 292–310. http://dx.doi.org/10.1108/sr-05-2020-0121.
Texte intégralSzymański, Andrzej, Dariusz Obrębski, Jacek Marczewski, Daniel Tomaszewski, Mirosław Grodner et Janusz Pieczyński. « CMOS Readout Circuit Integrated with Ionizing Radiation Detectors ». International Journal of Electronics and Telecommunications 60, no 1 (1 mars 2014) : 105–12. http://dx.doi.org/10.2478/eletel-2014-0014.
Texte intégralKavadias, S., P. De Moor et C. Van Hoof. « CMOS circuit for readout of microbolometer arrays ». Electronics Letters 37, no 8 (2001) : 481. http://dx.doi.org/10.1049/el:20010330.
Texte intégralNasri, B., et C. Fiorini. « A CMOS readout circuit for microstrip detectors ». Journal of Instrumentation 10, no 03 (24 mars 2015) : C03038. http://dx.doi.org/10.1088/1748-0221/10/03/c03038.
Texte intégralThèses sur le sujet "CMOS readout"
Guo, Xiaochuan. « A time-base asynchronous readout cmos image sensor ». [Gainesville, Fla.] : University of Florida, 2002. http://purl.fcla.edu/fcla/etd/UFE0000540.
Texte intégralKepenek, Reha. « Capacitive Cmos Readout Circuits For High Performance Mems Accelerometers ». Master's thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/12609310/index.pdf.
Texte intégralm CMOS process. Readout circuit is combined with Silicon-On-Glass (SOG) and Dissolved Wafer Process (DWP) accelerometers. Both open loop and closed loop tests of the accelerometer system are performed. Open loop test results showed high sensitivity up to 8.1 V/g and low noise level of 4.8 µ
g/&
#61654
Hz. Closed loop circuit is implemented on a PCB together with the external filtering and decimation electronics, providing 16-bit digital output at 800 Hz sampling rate. High acceleration tests showed ±
18.5 g of linear acceleration range with high linearity, using DWP accelerometers. The noise tests in closed loop mode are performed using Allan variance technique, by acquiring the digital data. Allan variance tests provided 86 µ
g/&
#61654
Hz of noise level and 74 µ
g of bias drift. Temperature sensitivity tests of the readout circuit in closed loop mode is also performed, which resulted in 44 mg/º
C of temperature dependency. Two different types of new adaptive sigma-delta readout circuits are designed in order to improve the resolution of the systems by higher frequency operation. The two circuits both change the acceleration range of operation of the system, according to the level of acceleration. One of the adaptive circuits uses variation of feedback time, while the other circuit uses multi-bit feedback method. The simulation results showed micro-g level noise in closed loop mode without the addition of the mechanical noise of the sensor.
Toprak, Alperen. « Cmos Readout Electronics For Microbolometer Type Infrared Detector Arrays ». Master's thesis, METU, 2009. http://etd.lib.metu.edu.tr/upload/3/12610390/index.pdf.
Texte intégraland a 384x288 resistive microbolometer FPA readout for 35 µ
m pixel pitch is designed and fabricated in a standard 0.6 µ
m CMOS process. A 4-layer PCB is also prepared in order to form an imaging system together with the FPA after detector fabrication. The low power output buffering architecture employs a new buffering scheme that reduces the capacitive load and hence, the power dissipation of the readout channels. Furthermore, a special type operational amplifier with digitally controllable output current capability is designed in order to use the power more efficiently. With the combination of these two methods, the power dissipation of the output buffering structure of a 384x288 microbolometer FPA with 35 µ
m pixel pitch operating at 50 fps with two output channels can be decreased to 8.96% of its initial value. The new bias correction DAC structure is designed to overcome the power dissipation and noise problems of the previous designs at METU. The structure is composed of two resistive ladder DAC stages, which are capable of providing multiple outputs. This feature of the resistive ladders reduces the overall area and power dissipation of the structure and enables the implementation of a dedicated DAC for each readout channel. As a result, the need for the sampling operation required in the previous designs is eliminated. Elimination of sampling prevents the concentration of the noise into the baseband, and therefore, allows most of the noise to be filtered out by integration. A 384x288 resistive microbolometer FPA readout with 35 &
#956
m pixel pitch is designed and fabricated in a standard 0.6 &
#956
m CMOS process. The fabricated chip occupies an area of 17.84 mm x 16.23 mm, and needs 32 pads for normal operation. The readout employs the low power output buffering architecture and the new bias correction DAC structure
therefore, it has significantly low power dissipation when compared to the previous designs at METU. A 4-layer imaging PCB is also designed for the FPA, and initial tests are performed with the same PCB. Results of the performed tests verify the proper operation of the readout. The rms output noise of the imaging system and the power dissipation of the readout when operating at a speed of 50 fps is measured as 1.76 mV and 236.9 mW, respectively.
Musayev, Javid. « Cmos Integrated Sensor Readout Circuitry For Dna Detection Applications ». Master's thesis, METU, 2011. http://etd.lib.metu.edu.tr/upload/12613645/index.pdf.
Texte intégralm pixel pitch. Pixels have 5 µ
m X 5 µ
m detector electrodes implemented with the top metal of the CMOS process, and they are capable of detecting charge transferred or induced on those electrodes with a very high sensitivity. This study also includes development of an external electronics containing ADC for analog to digital data conversion. This external circuitry is implemented on a PCB compatible with the Opal Kelly XM3010 FPGA that provides data storage and transfer to PC. The measured noise of the overall system is 6.7 e- (electrons), which can be shrunk down to even 5.1 e- with an over sampling rate. This kind of sensitivity performance is very suitable for DNA detection, as a single nucleotide of a DNA contains 1 or 2 e- and as 10 to 20 base pair long DNA&rsquo
s are usually used in microarray applications. The measured dynamic range of the system is 71 dB, in other words, at most 24603 e- per frame (20 ms) can be detected. The measured leakage is 31 e-/frame, but this does not have a dramatic effect on the sensitivity of the system, noting that the leakage is a predictable quantity. DNA detection tests are performed with the chip in addition to electronic performance measurements. The surface of the chip is covered with a nitride passivation layer to prevent the pixel crosstalk and is modified with an APTES polymer for suitable DNA immobilization. DNA immobilization and hybridization tests are performed with 5&rsquo
-TCTCACCTTC-3&rsquo
probe and its complementary 3&rsquo
-AGAGTGGAAG-5&rsquo
target sequences. Hybridization performed in 1 pM solution is shown to have a larger steady state leakage than the immobilization in a 13 µ
M solution, implying the ability to differentiate between the full match and full mismatch sequences. To best of our knowledge, the measured pM sensitivity has not yet been reported with any label free CMOS DNA microarrays in literature, and it is comparable with the sensitivity of techniques like QCM or the fluorescence imaging. The 1 pM sensitivity is not a theoretical limit of the sensor, since theoretically the sensitivity level of 6.7 e- can offer much better results, down to the aM level, as far as the noise of electronics is considered, nevertheless the sensitivity is expected to be limited by DNA immobilization and hybridization probabilities which are determined by the surface modification technique and applied protocol. Improving those can lead to much smaller detection limits, such as aM level as stated above.
CICIOTTI, FULVIO. « Oscillator-Based CMOS Readout Interfaces for Gas Sensing Applications ». Doctoral thesis, Università degli Studi di Milano-Bicocca, 2019. http://hdl.handle.net/10281/241089.
Texte intégralDetection of toxic and dangerous gases has always been a need for safety purpose and, in recent years, portable and low-cost gas sensing systems are becoming of main interest. This thesis presents fast, high precision, low-power, versatile CMOS interface circuits for portable gas sensing applications. The target sensors are Metal Oxide Semiconductor (MOX) sensors which are widely used due to their inherent compatibility with integrated MEMS technologies. The chosen readout typologies are based on the time-domain Resistor-Controlled Oscillator. This guarantees wide dynamic range, good precision and the ability to cope with the large MOX sensor resistance variations. Four different prototypes have been successfully developed and tested. Chemical measurements with a real SnO2 MOX sensor have also been performed to validate the results, showing a minimum CO detection capability in ambient air of 5 ppm. The ASICs are able to cover 128 dB of DR at 4 Hz of digital output data rate, or 148 dB at 0.4 Hz, while providing a relative error always better than 0.4% (SNDR >48 dB). Target performances have been achieved with aggressive design strategies and system-level optimization, and using a scaled (compared to typical implementations in this field) 130nm CMOS technology provided by Infineon Technologies AG. Power consumption is about 450 μA. Moreover, this work introduces the possibility to use the same oscillator-based architecture to perform capacitive sensors readout. Measurement results with capacitive MEMS sensors have shown 116 dB of DR in CSENS mode, with an SNR of 74 dB at 10 Hz of digital output data rate. The architectures developed in this thesis are compatible with the modern standards in the portable gas sensing industry.
RESTA, FEDERICA. « Integrated Read-out Front-end for High-Energy Physics Experiments ». Doctoral thesis, Università degli Studi di Milano-Bicocca, 2017. http://hdl.handle.net/10281/158121.
Texte intégralPhysic researches and discoveries depend heavily from efficient and reliability of the High-Energy Physics (HEP) experiments. The main goal is to study the fundamental constituents of the matter in terms of elementary charge particles, their interactions and their secondary products. The Large Hadron Collider (LHC) at the CERN works every day to discover details on new charged particles as neutrinos and Higgs Bosons. Charges are generated and accelerated from beam collisions inside the LHC. Different detectors are organized in shell structures and are designed to detect few particles topology. Typically, the parameters useful to identify a charged particle are momentum, electrical charge, energy, time of flight and distance. Detectors design is important but it is enhanced from proper electronic readout systems. In the last years, electronics parts are more and more efficient and compact. CMOS integrated solution are preferred to discrete one allowing major reliability, cost reduction and performance improvement. The design is not trivial but not impossible. Some characteristics depend on the electronic designer and his capability to manage the external parasitic effects, as the parasitic capacitance of the connected detector. Unfortunately, phenomena as radiation effects on electronics must be taken in account but they are not completely eliminated. CMOS technology influences strongly the integrated circuit performance and radiation hardness. In this scenario, 3 readout frontend circuits for HEP experiments have been designed, integrated and measured. 2 of them represent 2 different prototypes realized in IBM 130nm technology for ATLAS experiment at CERN laboratory with Max-Plank Institute for Physics collaboration. They include an analog chain in cascade with a digital one. Input charges (up to 100fC) are detected and converted into voltage signals. Their amplitude are proportional to the input and are sent to the following digital part. The digital part provides information about arrival time and amount of the input charge. When the discriminator switches, an event is detected and the Wilkinson ADC starts the voltage-to-time conversion. The full chips have a JTAG section to manage all programmable parameters (i.e. thresholds, hysteresis, deadtime, etc.) The second prototype is designed improving the previous version in terms of supply rejection noise, deadtime range and hysteresis management. The third circuit presented in this thesis is the first readout frontend for Pixel detectors in 28nm technology. The channel includes a charge sensitive preamplifier with an inverter switched based comparator. Reduced supply voltage and 28nm technology imply some difficult in the design with a major tolerance to the radiations, a lower area occupancy and a lower power consumption. The circuits are been designed for 2 different scenarios in terms of detector parasitic capacitance, detectable input charges, supply voltage, threshold voltage, power consumption and noise. In overall cases, the integrated systems provide information about amount of detected input charge and arrival time within 25ns. This aspect is very important and allows avoiding mistakes. Successive collisions lead to spurious signals presence and a single detection could have information about two different events. Maintaining the processing time within 25ns, consecutive collisions are detected as different events. This work is organized as follows. Part I includes a brief summary of the entire work in order to fix the goals of my activities. Then, the Part II is dedicated on a simplified description of the application field and the next target of the future experiments. In particular, some details on the effects induced by the radiation to integrated electronic component are provided. Part III and Part IV represent the core, including 3 readout frontend circuits design and measurements. Finally, there are correlated publications and conclusions.
Kramnik, Danielius. « Scaling trapped-ion quantum computers with CMOS-integrated state readout ». Thesis, Massachusetts Institute of Technology, 2020. https://hdl.handle.net/1721.1/129912.
Texte intégralCataloged from student-submitted PDF of thesis.
Includes bibliographical references (pages 155-164).
Quantum information processing (QIP) has emerged as a powerful new computing paradigm as traditional Moore's law scaling slows due to skyrocketing costs of shrinking feature sizes, interconnects becoming the dominant source of energy consumption and delay as transistor critical dimensions fall below 10 nm, and power density limiting the activity factor in digital systems on a chip. Quantum computers use quantum states ("qubits") to store and manipulate information, giving them fundamental performance advantages over classical digital computers in certain applications. Although the feasibility of QIP has been proven for decades using smallscale (. 50 physical qubit) demonstration systems, the main problem is achieving scalability using existing designs.
Individual atomic ions trapped by electromagnetic fields in a vacuum and manipulated using lasers have been a leading candidate for a physical substrate for QIP since the beginning, but scaling has been limited by the bulky free-space optics that are traditionally used for state manipulation and readout. CMOS chips with integrated photonics, on the other hand, can solve the scalability issue by tightly packing photodetectors for state readout, classical computing resources for timing and control, and optical waveguides and modulators for state manipulation onto the same chip. In recent years researchers have fabricated a planar ion trap in a CMOS foundry and addressed individual ions using photonic components built on a custom-fabricated ion trap, but the problem of CMOS-integrated state readout remains unaddressed. Current approaches to state readout use a large external lens and photomultiplier tube to detect state-dependent ion fluorescence.
Instead, fabricating silicon photodetectors directly below the trap location would eliminate large light collection optics and enable scaling of readout to greater numbers of ions by closing the sensing-to-manipulation loop on-chip. This thesis addresses this issue by developing hardware and methodology to perform detailed characterization of single-photon avalanche diodes (SPADs) integrated on a CMOS ion trap at cryogenic temperatures, showing that state readout with speed and fidelity comparable to the bulk optics approach is possible. Based on our results, state readout experiments using a CMOS ion trap with integrated SPADs are presently underway at the MIT Lincoln Laboratory.
by Danielius Kramnik.
M. Eng.
M.Eng. Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science
Shiah, Jack Chih-Chieh. « Design techniques for low-power low-noise CMOS capacitive-sensor readout circuits ». Thesis, University of British Columbia, 2015. http://hdl.handle.net/2429/54529.
Texte intégralApplied Science, Faculty of
Electrical and Computer Engineering, Department of
Graduate
Herrera, Hugo Daniel Hernández. « Noise and PSRR improvement technique for TPC readout front-end in CMOS. technology ». Universidade de São Paulo, 2015. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-05072016-151016/.
Texte intégralALICE é um dos quatro grandes experimentos do acelerador de partículas LHC (Large Hadron Collider) instalado no laboratório europeu CERN. Um programa de atualizações desse experimento acaba de ser aprovado pelo comitê gestor do acelerador LHC. Dentro das atualizações planejadas para os próximos anos do experimento ALICE, está melhorar a resolução e eficiência de rastreamento de partículas produzidas em colisões entre íons pesados, mantendo a excelente capacidade de identificação de partículas para uma taxa de leitura de eventos significativamente maior da atual. Para se alcançar esse objetivo, entre outras ações, é preciso atualizar os detectores Time Projection Chamber (TPC), modificando a eletrônica de leitura de eventos, a qual não é adequada para esta migração. Para superar esta limitação tem sido proposto o projeto, simulação, fabricação, teste experimental e validação de um ASIC protótipo de aquisição de sinais e de processamento digital chamado SAMPA, que possa ser usado na eletrônica de detecção dos sinais no cátodo do TPC, que suporte polaridades negativas de tensão de entrada e leitura continua de dados, com 32 canais por chip, com menor consumo de potência comparado com a versão anterior do chip. Este trabalho tem como objetivo o projeto, fabricação, e teste experimental de um readout front-end em tecnologia CMOS 130nm, com polaridade configurable (positiva/ negativa), peaking time e sensibilidade, de forma que o novo SAMPA ASIC possa ser usada em ambos detectores. Para obter um ASIC integrando 32 canais por chip, o projeto do front-end proposto precisa ter baixa área e baixo consumo de potência, mas ao mesmo tempo requer baixo ruido. Neste sentido, uma nova técnica para melhorar a especificação de ruido e o PSRR (Power Supply Rejection Ratio) sem impacto no consumo de área e potência é proposta neste trabalho. A análise e as equações do circuito proposto são apresentadas as quais foram validadas por simulação e teste experimental de um circuito integrado com 5 canais do front-end projetado. O Equivalent Noise Charge medido foi <550e para uma capacitance do detector de 18.5pF. A área total do front-end foi de 2300?m × 150?m, e o consumo total de potencia medido foi de 9.1mW por canal.
Trunk, Ulrich. « Development and characterisation of the radiation tolerant HELIX 128-2 readout chip for the HERA-B microstrip detectors ». [S.l. : s.n.], 2001. http://www.bsz-bw.de/cgi-bin/xvms.cgi?SWB9142825.
Texte intégralLivres sur le sujet "CMOS readout"
Nawito, Moustafa. CMOS Readout Chips for Implantable Multimodal Smart Biosensors. Wiesbaden : Springer Fachmedien Wiesbaden, 2018. http://dx.doi.org/10.1007/978-3-658-20347-4.
Texte intégralCMOS Readout Chips for Implantable Multimodal Smart Biosensors. Springer Vieweg, 2017.
Trouver le texte intégralChapitres de livres sur le sujet "CMOS readout"
Yazicioglu, R. Firat. « Readout Circuits ». Dans Bio-Medical CMOS ICs, 125–55. Boston, MA : Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6597-4_4.
Texte intégralBoukhayma, Assim. « Noise Reduction in CIS Readout Chains ». Dans Ultra Low Noise CMOS Image Sensors, 85–99. Cham : Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-68774-2_5.
Texte intégralBuckhorst, Rolf, Bedrich J. Hosticka et Helmut Seidel. « CMOS Readout Electronics for Capacitive Acceleration Sensors ». Dans Micro System Technologies 90, 636–41. Berlin, Heidelberg : Springer Berlin Heidelberg, 1990. http://dx.doi.org/10.1007/978-3-642-45678-7_91.
Texte intégralChang, Zhong Yuan, et Willy M. C. Sansen. « Low-Noise High-Speed CMOS Detector Readout Electronics ». Dans Low-Noise Wide-Band Amplifiers in Bipolar and CMOS Technologies, 153–200. Boston, MA : Springer US, 1991. http://dx.doi.org/10.1007/978-1-4757-2126-3_5.
Texte intégralNawito, Moustafa. « Introduction ». Dans CMOS Readout Chips for Implantable Multimodal Smart Biosensors, 1–6. Wiesbaden : Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-20347-4_1.
Texte intégralNawito, Moustafa. « The SMARTImplant Project ». Dans CMOS Readout Chips for Implantable Multimodal Smart Biosensors, 7–18. Wiesbaden : Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-20347-4_2.
Texte intégralNawito, Moustafa. « ASIC Version 1 ». Dans CMOS Readout Chips for Implantable Multimodal Smart Biosensors, 19–40. Wiesbaden : Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-20347-4_3.
Texte intégralNawito, Moustafa. « ASIC Version 2 ». Dans CMOS Readout Chips for Implantable Multimodal Smart Biosensors, 41–84. Wiesbaden : Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-20347-4_4.
Texte intégralNawito, Moustafa. « ASIC Version 3 ». Dans CMOS Readout Chips for Implantable Multimodal Smart Biosensors, 85–96. Wiesbaden : Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-20347-4_5.
Texte intégralNawito, Moustafa. « Measurement Results ». Dans CMOS Readout Chips for Implantable Multimodal Smart Biosensors, 97–118. Wiesbaden : Springer Fachmedien Wiesbaden, 2017. http://dx.doi.org/10.1007/978-3-658-20347-4_6.
Texte intégralActes de conférences sur le sujet "CMOS readout"
Charlier, Olivier, Thys Cronje et Chris A. Van Hoof. « Cryogenic standard CMOS sensor readout electronics ». Dans International Symposium on Optical Science and Technology, sous la direction de Marija Strojnik et Bjorn F. Andresen. SPIE, 2000. http://dx.doi.org/10.1117/12.406540.
Texte intégralAy, Suat U. « Boosted readout for CMOS APS pixels ». Dans 2011 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, 2011. http://dx.doi.org/10.1109/iscas.2011.5938038.
Texte intégralMiyatake, Shigehiro, Kouichi Ishida, Takashi Morimoto, Yasuo Masaki et Hideki Tanabe. « Transversal-readout CMOS active pixel image sensor ». Dans Photonics West 2001 - Electronic Imaging, sous la direction de Morley M. Blouke, John Canosa et Nitin Sampat. SPIE, 2001. http://dx.doi.org/10.1117/12.426949.
Texte intégralSami, Denis, Deyan Levski, Guy Meynants, Martin Waeny, Nikolai Dimitrov, Georgi Bochev et Rostislav Kandilarov. « A Flexible CMOS Test-Pixel Readout System ». Dans 2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES). IEEE, 2022. http://dx.doi.org/10.23919/mixdes55591.2022.9838323.
Texte intégralXu, Sheng, Yao-Zu Guo, Xiang-Shun Kong, Hao-Yu Zhu, Hao-Lan Ma et Xiao-Li Ji. « Self-Calibration Readout Circuits for CMOS Microbolometers ». Dans 2022 IEEE 16th International Conference on Solid-State & Integrated Circuit Technology (ICSICT). IEEE, 2022. http://dx.doi.org/10.1109/icsict55466.2022.9963359.
Texte intégralPellerano, Stefano, Sushil Subramanian, Jong-Seok Park, Bishnu Patra, Todor Mladenov, Xiao Xue, Lieven M. K. Vandersypen, Masoud Babaie, Edoardo Charbon et Fabio Sebastiano. « Cryogenic CMOS for Qubit Control and Readout ». Dans 2022 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2022. http://dx.doi.org/10.1109/cicc53496.2022.9772841.
Texte intégralYao, Libin. « CMOS readout circuit design for infrared image sensors ». Dans International Symposium on Photoelectronic Detection and Imaging 2009, sous la direction de Kun Zhang, Xiang-jun Wang, Guang-jun Zhang et Ke-cong Ai. SPIE, 2009. http://dx.doi.org/10.1117/12.835520.
Texte intégralMa, Cheng, Jing Li et Xinyang Wang. « Readout architectures for high speed CMOS image sensor ». Dans ISPDI 2013 - Fifth International Symposium on Photoelectronic Detection and Imaging, sous la direction de Jun Ohta, Nanjian Wu et Binqiao Li. SPIE, 2013. http://dx.doi.org/10.1117/12.2033402.
Texte intégralKim, Dong-Kyu, et Hyun-Sik Kim. « Low-noise high-speed CMOS CID readout IC ». Dans 2017 International SoC Design Conference (ISOCC). IEEE, 2017. http://dx.doi.org/10.1109/isocc.2017.8368858.
Texte intégralZhang, Ming, Wenbin Yang, Nicolas Llaser et Herve Mathias. « CMOS reconfigurable readout circuit for a multifunction sensor ». Dans 2009 Joint IEEE North-East Workshop on Circuits and Systems and TAISA Conference (NEWCAS-TAISA). IEEE, 2009. http://dx.doi.org/10.1109/newcas.2009.5290470.
Texte intégralRapports d'organisations sur le sujet "CMOS readout"
Ivanov, Andrew. Quest for a Top Quark Partner and Upgrade of the Pixel Detector Readout Chain at the CMS. Office of Scientific and Technical Information (OSTI), octobre 2018. http://dx.doi.org/10.2172/1478074.
Texte intégral