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Fayed, Ayman Adel. « Adaptive techniques for analog and mixed signal integrated circuits ». Connect to this title online, 2004. http://rave.ohiolink.edu/etdc/view?acc%5Fnum=osu1097519730.
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Thesis (Ph. D.)--Ohio State University, 2004.Title from first page of PDF file. Document formatted into pages; contains xix, 232 p.; also includes graphics (some col.). Includes bibliographical references (p. 222-230).
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Liu, Zhi-Hong. « Mixed-signal testing of integrated analog circuits and modules ». Ohio : Ohio University, 1999. http://www.ohiolink.edu/etd/view.cgi?ohiou1181174339.
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Variyam, Pramodchandran. « Efficient testing techniques for analog and mixed-signal circuits ». Diss., Georgia Institute of Technology, 1999. http://hdl.handle.net/1853/13457.
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Sadeghi, Nima. « Design techniques for high-temperature analog and mixed-signal integrated circuits ». Thesis, University of British Columbia, 2012. http://hdl.handle.net/2429/43092.
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Reliable high-temperature analog and mixed-signal CMOS circuits are required for several applications including aerospace, automotive control, oil field instrumentation, and pulp and paper digesters. In particular, in this work we focus on the design of key building blocks of a miniature sensor interface system that is intended to operate in a pulp and paper digester and collect and record sensory data such as pressure
and temperature along its trajectory within the digester. The temperature inside the
digester can be as high as 180℃.
Design considerations and techniques for implementing these building blocks both at
component- and circuit-levels are presented. At the component level, techniques for
designing monolithic resistors with a desired temperature coefficient (TC) are proposed, and an analysis on the effects of design parameters such as resistor length, width and the number of fingers on the TC of such multi-finger resistor structures is presented. Furthermore, since the foundry-provided transistor models are typically
valid up to 125℃, various NMOS and PMOS transistors with diff erent sizes are implemented to study their behaviour at high temperature. Based on our observations, a suitable sizing for transistors is suggested for circuits operating up to 200℃. At the circuit-level, several key building blocks such as bias circuits, voltage references and oscillators are designed and proof-of-concept prototypes are implemented in a
standard 0.13 ㎛ CMOS process. The operation of the circuits is experimentally
validated over the temperature range of interest, namely, 25 to 200℃.
Also, a low-complexity resistive and capacitive temperature-compensation techniques
for high-temperature relaxation oscillators is proposed. Although the temperature
stability of the proposed oscillator (108 ppm/℃) compares favourably with that of
state-of-the-art designs, it occupies 0.007 mm² which is 2.3 to 114 times smaller than
other comparable designs. Also, the proposed circuit operates reliably up to 200℃
(as compared to 125℃ in other designs).
Although the proposed techniques are only validated using proof-of-concept prototypes in a 0.13 ㎛ CMOS technology, they are general and our preliminary studies on
several technologies indicate that the techniques can be implemented in other CMOS
technologies as well.
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Kasturi, Prasan. « A CAD tool for analog and mixed signal CMOS circuits / ». View online ; access limited to URI, 2006. http://0-digitalcommons.uri.edu.helin.uri.edu/dissertations/AAI3248232.
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Bhattacharya, Sambuddha. « Template-driven parasitic-aware optimization of analog/RF IC layouts / ». Thesis, Connect to this title online ; UW restricted, 2005. http://hdl.handle.net/1773/6121.
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Fei, Haibo. « High linearity analog and mixed-signal integrated circuit design ». [Ames, Iowa : Iowa State University], 2007.
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Hedayati, Raheleh. « High-Temperature Analog and Mixed-Signal Integrated Circuits in Bipolar Silicon Carbide Technology ». Doctoral thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-213697.
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Silicon carbide (SiC) integrated circuits (ICs) can enable the emergence of robust and reliable systems, including data acquisition and on-site control for extreme environments with high temperature and high radiation such as deep earth drilling, space and aviation, electric and hybrid vehicles, and combustion engines. In particular, SiC ICs provide significant benefit by reducing power dissipation and leakage current at temperatures above 300 °C compared to the Si counterpart. In fact, Si-based ICs have a limited maximum operating temperature which is around 300 °C for silicon on insulator (SOI). Owing to its superior material properties such as wide bandgap, three times larger than Silicon, and low intrinsic carrier concentration, SiC is an excellent candidate for high-temperature applications. In this thesis, analog and mixed-signal circuits have been implemented using SiC bipolar technology, including bandgap references, amplifiers, a master-slave comparator, an 8-bit R-2R ladder-based digital-to-analog converter (DAC), a 4-bit flash analog-to-digital converter (ADC), and a 10-bit successive-approximation-register (SAR) ADC. Spice models were developed at binned temperature points from room temperature to 500 °C, to simulate and predict the circuits’ behavior with temperature variation. The high-temperature performance of the fabricated chips has been investigated and verified over a wide temperature range from 25 °C to 500 °C. A stable gain of 39 dB was measured in the temperature range from 25 °C up to 500 °C for the inverting operational amplifier with ideal closed-loop gain of 40 dB. Although the circuit design in an immature SiC bipolar technology is challenging due to the low current gain of the transistors and lack of complete AC models, various circuit techniques have been applied to mitigate these problems. This thesis details the challenges faced and methods employed for device modeling, integrated circuit design, layout implementation and finally performance verification using on-wafer characterization of the fabricated SiC ICs over a wide temperature range.QC 20170905
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Al-Qutayri, Mahmoud A. « Testing techniques for analogue and mixed-signal integrated circuits ». Thesis, University of Bath, 1992. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.317309.
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Elshamy, Mohamed. « Design for security in mixed analog-digital integrated circuits ». Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS093.
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Récemment, les coûts faramineux d'une usine de fabrication de semi-conducteurs ont contraint de nombreuses entreprises à renoncer à avoir leur usine en propre. En externalisant la fabrication de CI/PI à des sociétés tierces, le procédé de fabrication a été confié à des sociétés potentiellement peu fiables. Il en résulte des menaces de sécurité pour l'industrie des semi-conducteurs, telles que la contrefaçon, la rétro-ingénierie et l'insertion de HT. Dans cette thèse, nous proposons une contre-mesure anti-piratage pour protéger les CI/PI AMS, une nouvelle attaque HT pour les CI/PI AMS et une nouvelle PUF. La technique anti-piratage que nous proposons est basée sur le verrouillage des circuits analogiques configurables. Notre technique exploite le mécanisme de configuration du circuit pour y introduire une fonction verrouillage. Nous présentons son implémentation et ses capacités de résilience contre les attaques. L'attaque HT proposée pour les circuits analogiques exploite l'infrastructure de test. Le HT est introduit dans le sous-système numérique du système AMS et transfère sa charge utile au circuit analogique via le bus de test. Le HT est invisible dans le domaine analogique. Le HT est montré sur deux études de cas. Cette thèse montre l'importance de nouvelles contre-mesures de sécurité et de confiance adaptées aux CI analogiques. La fonction PUF proposée utilise un neurone à impulsions comme source d'entropie. Sa caractéristique principale est de n'utiliser qu'une seule cellule PUF et une redondance temporelle pour générer une clé arbitrairement longue, ce qui réduit les coûts additionnels en surface et en énergie par rapport aux fonctions PUF traditionnellesRecently, the enormous cost of owning and maintaining a modern semiconductor manufacturing plant has coerced many companies to go fabless. By outsourcing the manufacturing IC/IP to third-party and often off-shore companies, the process has been extended to potentially untrustworthy companies. This has resulted in several security threats to the semiconductor industry such as counterfeiting, reverse engineering, and HTs insertion. In this thesis, we propose an anti-piracy countermeasure to protect AMS ICs/IPs, a novel HT attack for AMS ICs/IPs, and a novel PUF. More specifically, we propose an anti-piracy technique based on locking for programmable analog circuits. The proposed technique leverages the programmability fabric to implement a natural lock-less locking. We discuss its implementation and its resilience capabilities against foreseen attacks. The proposed HT attack for analog circuits leverages the test infrastructure. The HT is hidden effectively in a digital core and transfers its payload to the analog circuit via the test bus and the interface of the analog circuit to the test bus. Its key characteristic is that it is invisible in the analog domain. The proposed HT is demonstrated on two case studies. This thesis sheds light on the importance of developing new security and trust countermeasures tailored for analog circuits. The proposed PUF, called "neuron-PUF", uses a single spiking neuron as the source of entropy. Its key characteristic is that it uses a single PUF cell and temporal redundancy to generate an arbitrarily long key, which results in significant low area and power overheads compared to mainstream PUFs, such as delay-based and memory-based PUFs
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Chang, Yu-Hsu Henry. « Macromodeling and simulation of high-performance mixed Analog/Digital circuits / ». Thesis, Connect to this title online ; UW restricted, 1994. http://hdl.handle.net/1773/5956.
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Povazanec, Juraj. « Test process evaluation techniques for analogue and mixed signal integrated circuits ». Thesis, Leeds Beckett University, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.309793.
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Son, Kyung-Im. « A multi-class, multi-dimensional classifier as a topology selector for analog circuit design / by Kyung-Im Son ». Thesis, Connect to this title online ; UW restricted, 1998. http://hdl.handle.net/1773/5919.
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Thomsen, Axel. « High speed high accuracy signal processing with parallel analog circuits ». Diss., Georgia Institute of Technology, 1992. http://hdl.handle.net/1853/13846.
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Cheung, Wing-tai. « Geometric programming and signal flow graph assisted design of interconnect and analog circuits ». Click to view the E-thesis via HKUTO, 2007. http://sunzi.lib.hku.hk/HKUTO/record/B39558526.
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Perkins, Andrew John. « Structural testing and DFT insertion for analogue and mixed signal integrated circuits ». Thesis, University of Southampton, 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.299287.
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Twigg, Christopher M. « Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing ». Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11601.
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Large-scale reconfigurable and programmable analog devices provide a new option for prototyping and synthesizing analog circuits for analog signal processing and beyond. Field-programmable analog arrays (FPAAs) built upon floating gate transistor technologies provide the analog reconfigurability and programmability density required for large-scale devices on a single integrated circuit (IC). A wide variety of synthesized circuits, such as OTA followers, band-pass filters, and capacitively coupled summation/difference circuits, were measured to demonstrate the flexibility of FPAAs. Three generations of devices were designed and tested to verify the viability of such floating gate based large-scale FPAAs. Various architectures and circuit topologies were also designed and tested to explore the trade-offs present in reconfigurable analog systems. In addition, large-scale FPAAs have been incorporated into class laboratory exercises, which provide students with a much broader range of circuit and IC design experiences than have been previously possible. By combining reconfigurable analog technologies with an equivalent large-scale digital device, such as a field-programmable gate array (FPGA), an extremely powerful and flexible mixed signal development system can be produced that will enable all of the benefits possible through cooperative analog/digital signal processing (CADSP).
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Wemple, Ivan L. « Parasitic substrate modeling for monolithic mixed analog/digital circuit design and verification / ». Thesis, Connect to this title online ; UW restricted, 1996. http://hdl.handle.net/1773/5944.
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Wu, Pan. « The Design of High-Frequency Continuous-Time Integrated Analog Signal Processing Circuits ». PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/1162.
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High-performance, high-frequency operational transconductance amplifiers (OTAs) are very important elements in the design of high-frequency continuous-time integrated analog signal processing circuits, because resistors, inductors, integrators, mutators, buffers, multipliers, and filters can be built by OTAs and capacitors. The critical considerations for OTA design are linearity, tuning, frequency response, output impedance, power supply rejection (PSR) and common-mode rejection (CMR). For linearity considerations, two different methods are proposed. One uses cross-coupled pairs (CMOS or NMOS), producing OTAs with very high linearity but either the input range is relatively small or the CMR to asymmetrical inputs is poor. Another employs multiple differential pairs (current addition or subtraction), producing OTAs with high linearity over a very large input range. So, there are tradeoffs among the critical considerations. For different applications, different OTAs should be selected. For consideration of frequency response, the first reported GaAs OTA was designed for achieving very-high-frequency performance, instead of using AC compensation techniques. GaAs is one of the fastest available technologies, but it was new and less mature than silicon when we started the design in 1989. So, there were several issues, such as low output impedance, no P-channel devices, and Schottky clamp. To overcome these problems, new techniques are proposed, and the designed OTA has comparable performance to a CMOS OTA. For PSR and CMR considerations, a fully balanced circuit structure is employed with a common-mode feedback (CMF) circuit used to stabilize the DC output voltages. To reduce the interaction of the operation of CMF and tuning of OTAs, three improved versions of the CMF circuits used in operational amplifiers are proposed. With the designed OTAs, a I GHz GaAs inductor with small parasitics is designed using the proposed procedure to reduce high-frequency effects. Two CMOS high-order, high-frequency filters are designed: one in cascade structure and one in LC ladder form. Also, a 200 MHz third-order elliptic GaAs filter is designed with special consideration of very-high-frequency parasitics. All circuits were fabricated and measured. The experimental results were used to verify the designs.
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張永泰 et Wing-tai Cheung. « Geometric programming and signal flow graph assisted design of interconnect and analog circuits ». Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2007. http://hub.hku.hk/bib/B39558526.
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Chakrabarti, Sudip. « Test generation for fault isolation in analog and mixed-mode circuits ». Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/14899.
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al-Sarʻāwī, Said Fares. « Design techniques for low power mixed analog-digital circuits with application to smart wireless systems / ». Title page, contents and abstract only, 2003. http://web4.library.adelaide.edu.au/theses/09PH/09pha461.pdf.
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Hirschman, Karl D. « Process development of an analog/digital mixed-mode BiCMOS system at RIT / ». Online version of thesis, 1992. http://hdl.handle.net/1850/11238.
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Hooper, Mark S. « Submicron CMOS programmable analog floating-gate circuits and arrays using DC-DC converters ». Diss., Available online, Georgia Institute of Technology, 2005, 2005. http://etd.gatech.edu/theses/available/etd-12032004-155022/unrestricted/Hooper%5FMark%5FS%5F200505%5Fphd.pdf.
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Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005.Kucic, Matthew, Committee Member ; Hasler, Paul, Committee Chair ; Heck, Bonnie, Committee Member ; Cressler, John, Committee Member ; Anderson, David, Committee Member. Vita. Includes bibliographical references.
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Toner, Michael F. « MADBIST : a scheme for built-in self-test of mixed analog-digital integrated circuits ». Thesis, McGill University, 1996. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=40451.
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Consumers are demanding more and more value for each dollar spent on new electronic equipment. Built-In Self-Test (BIST) of electronic circuits and equipment will help to satiate the demand for self test, self diagnostics, and self repair. This dissertation explores a technique for a Mixed Analog Digital BIST (MADBIST) on a mixed-signal Integrated Circuit (IC). Specifically, on-chip tests for the Analog-to-Digital Converter and Digital-to-Analog Converter on the mixed-signal IC are developed. (The digital portion of the IC can be tested using digital BIST techniques). The tests implemented include Frequency Response, Signal-to-Noise Ratio, Gain Tracking, Inter-Modulation Distortion, and Harmonic Distortion. A precision analog test stimulus is efficiently generated on-chip using digital circuitry. The test stimulus itself is encoded within a Pulse-Density-Modulated bit stream. A narrow-band digital filter is employed to extract the measurement results. Experimental results from a test chip and a prototype circuit board are provided. Some of the engineering and economical trade-offs associated with the design of the tests are considered. The overhead required to implement several types of tests is dealt with. We also explore the relationship between the accuracy achieved by the test and the amount of resources required to implement it.
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Park, Shinwoong. « Reconfigurable Discrete-time Analog FIR filters for Wideband Analog Signal Processing ». Diss., Virginia Tech, 2019. http://hdl.handle.net/10919/99794.
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Demand for data communication capacity is rapidly increasing with more and more number of users and higher bandwidth services. As a result, a critical research issue is the implementation of wideband and flexible signal processing in communication and sensing applications. Although software defined radio (SDR) is a possible solution, it may not be practical due to the excessive requirements for analog-to-digital converter (ADCs) and digital filters for wideband signals. In this environment, discrete-time (DT) domain circuits are gaining attention in various architectures such as N-path filters, sampling mixers, and analog FIR/IIR/FFT filters. DT analog signal processing (DT-ASP) ahead of an ADC considerably relaxes the ADC requirements by flexible filtering, offers the potential for higher dynamic range performance, and provides robustness in the presence of digital CMOS scaling.
The primary work presented in this dissertation is the design of wideband analog finite impulse response (AFIR) filters. Analog FIR filters have been used as low pass filters for out-of-band rejection in narrow-band applications. However, this work seeks to develop AFIR filters suitable for wideband applications, extending its possible applications. To achieve these performance goals, capacitive digital to analog converters (CDACs) have been introduced for the first time as wideband analog coefficient multipliers, which has led to high linearity analog multiplication with coefficient selection at the DAC resolution. A prototype 4th order DT FIR filter has been implemented in 32nm SOI CMOS technology and has achieved low-pass, band-pass, and high-pass filter (LPF, BPF and HPF) transfer functions corresponding to the programmed coefficient sets with IIP3>11dBm linearity and less than 2 mW/tap of power consumption. The AFIR filter is also utilized to demonstrate a proof-of-concept FIR-based beamforming. The beamforming network consisting of 4 antenna element inputs followed by AFIR filters was implemented with PCB modules with the previously fabricated AFIR filter chip. Behavioral simulations are used to verify the beamforming function with given coefficient sets. Based on the developed AFIR filter modules, FIR-based beamforming was demonstrated with measurement results matching well with the simulations.
Further work presented is the design and optimization of multi-section CDAC (MS-CDAC) structures. The proposed MS-CDAC approach provides wide range of options to optimize the tradeoff between kT/C noise, linearity versus switching energy, speed and area. When the optimization approach is applied to a proof-of-concept 10-bit CDAC design, the selected MS-CDAC structure reduces total capacitance and switching energy by 97% and 98%, respectively for given linearity and noise limitations. The proposed MS-CDAC structures are applicable in both DT-ASP coefficient multiplier and SAR-ADC applications.PHD
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Yu, Xinyu. « High-temperature Bulk CMOS Integrated Circuits for Data Acquisition ». Case Western Reserve University School of Graduate Studies / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=case1144420886.
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Kucic, Matthew R. « Analog programmable filters using floating-gate arrays ». Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13755.
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Palakurthi, Praveen Kumar. « Design of a low voltage analog to digital converter ». To access this resource online via ProQuest Dissertations and Theses @ UTEP, 2009. http://0-proquest.umi.com.lib.utep.edu/login?COPT=REJTPTU0YmImSU5UPTAmVkVSPTI=&clientId=2515.
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More, Shailesh [Verfasser], Doris [Akademischer Betreuer] Schmitt-Landsiedel et Helmut [Akademischer Betreuer] Gräb. « Aging Degradation and Countermeasures in Deep-submicrometer Analog and Mixed Signal Integrated Circuits / Shailesh More. Gutachter : Helmut Gräb ; Doris Schmitt-Landsiedel. Betreuer : Doris Schmitt-Landsiedel ». München : Universitätsbibliothek der TU München, 2012. http://d-nb.info/1024354938/34.
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Oliveira, Vlademir de Jesus Silva [UNESP]. « Desenvolvimento de um sintetizador de freqüência de baixo custo em tecnologia CMOS ». Universidade Estadual Paulista (UNESP), 2009. http://hdl.handle.net/11449/100280.
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Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS...
In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture
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Qureshi, Muhammad Shakeel. « Integrated front-end analog circuits for mems sensors in ultrasound imaging and optical grating based microphone ». Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29613.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.Committee Chair: Hasler, Paul; Committee Co-Chair: Degertekin, Levent; Committee Member: Anderson, David; Committee Member: Ayazi, Farrokh; Committee Member: Brand, Oliver; Committee Member: Hesketh, Peter. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Ramakrishnan, Shubha. « A system design approach to neuromorphic classifiers ». Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/51718.
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This work considers alternative strategies to mainstream digital approaches to signal processing - namely analog and neuromorphic solutions, for increased computing efficiency. In the context of a speech recognizer application, we use low-power analog approaches for the signal conditioning and basic auditory feature extraction, while using a neuromorphic IC for building a dendritic classifier that can be used as a low-power word spotter. In doing so, this work also aspires to posit the significance of dendrites in neural computation.
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Sadeghifar, Mohammad Reza. « On High-Speed Digital-to-Analog Converters and Semi-Digital FIR Filters ». Licentiate thesis, Linköpings universitet, Elektroniska Kretsar och System, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-114274.
Texte intégralRésumé :
High-speed and high-resolution digital-to-analog converters (DACs) are vital components in all telecommunication systems. Radio-frequency digital-to-analog converter (RFDAC) provides high-speed and high-resolution conversion from digital domain to an analog signal. RFDACs can be employed in direct-conversion radio transmitter architectures. The idea of RFDAC is to utilize an oscillatory pulse-amplitude modulation instead of the conventional zero-order hold pulse amplitude modulation, which results in DAC output spectrum to have high energy high-frequency lobe, other than the Nyquist main lobe. The frequency of the oscillatory pulse can be chosen, with respect to the sample frequency, such that the aliasing images of the signal at integer multiples of the sample frequency are landed in the high-energy high-frequency lobes of the DAC frequency response. Therefore the high-frequency images of the signal can be used as the output of the DAC, i.e., no need to the mixing stage for frequency up-conversion after the DAC in the radio transmitter. The mixing stage however is not eliminated but it is rather moved into the DAC elements and therefore the local oscillator (LO) signal with high frequency should be delivered to each individual DAC element. In direct-conversion architecture of IQ modulators which utilize the RFDAC technique, however, there is a problem of finite image rejection. The origin of this problem is the different polarity of the spectral response of the oscillatory pulse-amplitude modulation in I and Q branches. The conditions where this problem can be alleviated in IQ modulator employing RFDACs is also discussed in this work. ΣΔ modulators are used preceding the DAC in the transmitter chain to reduce the digital signal’s number of bits, still maintain the same resolution. By utilizing the ΣΔ modulator now the total number of DAC elements has decreased and therefore the delivery of the high-frequency LO signal to each DAC element is practical. One of the costs of employing ΣΔ modulator, however, is a higher quantization noise power at the output of the DAC. The quantization noise is ideally spectrally shaped to out-of-band frequencies by the ΣΔ modulator. The shaped noise which usually has comparatively high power must be filtered out to fulfill the radio transmission spectral mask requirement. Semi-digital FIR filter can be used in the context of digital-to-analog conversion, cascaded with ΣΔ modulator to filter the out-of-band noise by the modulator. In the same time it converts the signal from digital domain to an analog quantity. In general case, we can have a multi-bit, semi-digital FIR filter where each tap of the filter is realized with a sub-DAC of M bits. The delay elements are also realized with M-bit shift registers. If the output of the modulator is given by a single bit, the semi-digital FIR filter taps are simply controlled by a single switch assuming a current-steering architecture DAC. One of the major advantages is that the static linearity of the DAC is optimum. Since there are only two output levels available in the DAC, the static transfer function, regardless of the mismatch errors, is always given by a straight line. In this work, the design of SDFIR filter is done through an optimization procedure where the ΣΔ noise transfer function is also taken into account. Different constraints are defined for different applications in formulation of the SDFIR optimization problem. For a given radio transmitter application the objective function can be defined as, e.g., the hardware cost for SDFIR implementation while the constraint can be set to fulfill the radio transmitter spectral emission mask.
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Petre, Csaba. « Sim2spice a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits / ». Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31820.
Texte intégralRésumé :
Thesis (M. S.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.Committee Chair: Paul Hasler; Committee Member: Christopher Rozell; Committee Member: David Anderson. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Xu, Ping. « High-frequency Analog Voltage Converter Design ». PDXScholar, 1994. https://pdxscholar.library.pdx.edu/open_access_etds/4891.
Texte intégralRésumé :
For many high-speed, high-performance circuits, purely differential inputs are needed. This project focuses on building high-speed voltage converters which can transfer a single-ended signal to a purely differential signal, or a differential input signal to a single-ended signal. Operational transconductance amplifier (OTAs) techniques are widely used in high-speed continuous-time integrated analog signal processing (ASP) circuits because resistors, inductors, integrators, buffers, multipliers and filters can be built by OT As and capacitors. Taking advantage of OT As, very-high-speed voltage converters are designed in CMOS technology. These converters can work in a frequency range from DC (OHz) up to lOOMHz and higher, and keep low distortion over a± 0.5V input range. They can replace transformers so that designing fully integrated differential circuits becomes possible. The designs are based on a MOSIS 2μm n-well process. SPICE simulations of these designs are given. The circuit was laid out with MAGIC layout tools and fabricated through MOSIS. The chip was measured at PSU and Intel circuit labs and the experimental results show the correctness of the designs.
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Oliveira, Vlademir de Jesus Silva. « Desenvolvimento de um sintetizador de freqüência de baixo custo em tecnologia CMOS / ». Ilha Solteira : [s.n.], 2009. http://hdl.handle.net/11449/100280.
Texte intégralRésumé :
Orientador: Nobuo OkiBanca: Suely Cunha Amaro Mantovani
Banca: Jozué Vieira Filho
Banca: Marcelo Arturo Jara Perez
Banca: Paulo Augusto Dal fabbro
Resumo: Nesta tese, propõe-se um sintetizador de freqüência baseado em phase locked loops (PLL) usando uma arquitetura que utiliza um dual-path loop filter, constituído de componentes passivos e um integrador digital. A proposta é empregar técnicas digitais, para reduzir o custo da implementação do sintetizador de freqüência, e flexibilizar o projeto do loop filter, para possibilitar que a arquitetura opere em uma faixa de freqüência larga de operação e com redução de tons espúrios. O loop filter digital é constituído de um contador crescente/ decrescente cujo clock é proveniente da amostragem da diferença de fase de entrada. As técnicas digitais aplicadas ao loop filter se baseiam em alterações da operação do contador, em tempos pré-estabelecidos, os quais são controlados digitalmente. Essas técnicas possibilitam reduzir o tempo de estabelecimento do PLL ao mesmo tempo em que problemas de estabilidade são resolvidos. No desenvolvimento da técnica de dual-path foi realizado o estudo de sua estabilidade, primeiramente, considerando a aproximação do PLL para um sistema linear e depois usando controle digital. Nesse estudo foram deduzidas as equações do sistema, no domínio contínuo e discreto, tanto para o projeto da estabilidade, quanto para descrever o comportamento do PLL. A metodologia top-down é usada no projeto do circuito integrado. As simulações em nível de sistema são usadas, primeiramente, para as criações das técnicas e posteriormente para a verificação do seu comportamento, usando modelos calibrados com os blocos projetados em nível de transistor. O circuito integrado é proposto para ser aplicado em identificação por rádio freqüência (RFID) na banda de UHF (Ultra High Frequency), usando multi-standard, e deve operar na faixa de 850 MHz a 1010 MHz. O sintetizador de freqüência foi projetado na tecnologia CMOS... (Resumo completo, clicar acesso eletrônico abaixo)
Abstract: In this thesis, a frequency synthesizers phase locked loops (PLL) based with an architecture that uses a dual-path loop filter consisting of passive components and a digital integrator are proposed. The objective is to employ digital techniques to reduce the implementation cost and get loop filter design flexibility to enable the architecture to have a large tuning range operation and spurious reduction. The digital loop filter is based in an up/down counter where the phase difference is sampled to generate the clock of the counter. The techniques applied in the digital path are based in digitally controlled changes in the counter operation in predefined time points. These techniques provide PLL settling time reductions whiling the stability issues are solved. The stability study of the proposed dual path has been developed. First the linear system approximation for the PLL has been assumed and then employing digital control. The continuous and discrete time equations of architecture were derived in that study applied to stability design as well as to describe the architecture behavior. The top-down methodology has been applied to the integrated circuit design. In the beginning, the system level simulations are used for the techniques creation and then the behavioral models that were calibrated with transistor level blocks are simulated. The application of the circuit is proposed to Radio Frequency Identification (RFID) using UHF (Ultra High Frequency) band for multi-standards application and will operate in range of 850 MHz to 1010 MHz. The proposed frequency synthesizer has been designed in the AMS 0.35 μm CMOS technology with 2V power supply. A 300 μs of settling time and 140 Hz of resolution was obtained in simulations. The proposed frequency synthesizer have low complexity and shown a reference noise suppression about 45.6 dB better than the conventional architecture
Doutor
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Korhonen, E. (Esa). « On-chip testing of A/D and D/A converters:static linearity testing without statistically known stimulus ». Doctoral thesis, University of Oulu, 2010. http://urn.fi/urn:isbn:9789514263064.
Texte intégralRésumé :
Abstract
The static linearity testing of analog-to-digital and digital-to-analog converters (ADCs and DACs) has traditionally required test instruments with higher linearity and resolution than that of the device under test. In this thesis ways to test converters without expensive precision instruments are studied. A novel calculation algorithm for the ADC differential non-linearity (DNL) and integral non-linearity (INL) estimation is proposed. The algorithm assumes that two stimuli with constant offset between them are applied to the ADC under test and that the code density histograms for both stimuli are recorded. The probability density function (PDF) of the stimulus is then solved using simple calculations so that DNL and INL of the ADC can be estimated without a priori known stimuli. If a DAC is used to generate the stimulus to ADC, all inputs and outputs are digital and the new algorithm can be used to obtain the PDF of the DAC output. Moreover, the PDF of DAC actually characterizes its INL and DNL so that this all-digital test configuration enables a simultaneous testing of both converters thanks to the new algorithm.
The proposed algorithm is analyzed thoroughly both mathematically and by carrying out several simulations and experimental tests. On the basis of the analysis it is possible to approximate the impending estimation error and select the optimal value for the offset between the stimuli. In theory, the accuracy of the algorithm proposed equals that of the standard histogram method with ideal stimulus, but in practice, the accuracy is limited by that of the offset between the stimuli. Therefore, special attention is paid to development of an accurate and small offset generator which enables ratiometric test setup and solves the problems in the case of reference voltage drift. The proposed on-chip offset generator is built using only four resistors and switches. It occupies 122·22 μm2 in a 130 nm CMOS process and accuracy is appropriate for the INL testing of 12-bit converters from rail-to-rail. Based on the analysis of the influence of resistor non-linearity on the accuracy of offset, it is possible to improve the offset generator further. With discrete resistors, the INL of 16-bit ADCs was tested using a 12-bit signal generator.
The proposed simple algorithm and tiny offset generator are considered to be important steps towards built-in DNL and INL testing of ADCs and DACs.
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Michal, Vratislav. « Design of CMOS analog integrated circuits as readout electronics for High-TC superconductor and semiconductor terahertz bolometric sensors ». Phd thesis, Université Pierre et Marie Curie - Paris VI, 2006. http://tel.archives-ouvertes.fr/tel-00417838.
Texte intégralRésumé :
Cette thèse porte sur la conception d'un circuit intégré CMOS pour l'électronique de lecture de capteurs bolométriques à base de semiconducteurs ou supraconducteurs haute-température. Dans ce manuscrit, une chaîne de traitement du signal est étudiée. Elle est composée d'un amplificateur différentiel à gain fixé pour des températures de 40 à 400K, ainsi que d'un filtre de fréquence passe-bas actif à haute dynamique. Une architecture optimale d'amplificateur est définie sans contre-réaction, permettant d'atteindre une large bande passante (17MHz pour un gain de 40dB), une consommation réduite (Iq = 2mA) et une haute impédance d'entrée. Afin de fixer le gain avec précision dans la structure CMOS, deux méthodes différentes sont présentées et vérifiées sur un circuit intégré. Par la suite, le comportement des filtres dans la bande d'atténuation est étudié afin d'augmenter la fréquence de coupure maximale. Deux structures avec une faible influence des éléments actifs « réels » sont conçues: le filtre Sallen-Key amélioré et la structure basée sur un convoyeur du courant CCII-. Enfin, nous présentons un CCII- intégré en CMOS ayant une très faible impédance de sortie.
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Chamas, Ibrahim. « The Analysis and Design of Phase-tunable Low-Power Low-Phase-Noise I/Q Signal Sources for Analog Phase Calibrated Transceivers ». Diss., Virginia Tech, 2008. http://hdl.handle.net/10919/102076.
Texte intégralRésumé :
Due to the demand for low-cost, small-form factor and large-scale integration of system-on-chip wireless transceivers, the image-reject, zero-IF and low-IF receiver architectures have become the main topologies used in mainstream wireless communication systems. Consequently, signal sources with quadrature phase outputs [quadrature oscillators (QOs)] are therefore essential, and their phase noise, driving capability, tuning range, oscillation frequency, and power consumption have a major impact on the overall receiver performance. Additionally, it is required that the QO synthesize precise I/Q waveforms across the signal bandwidth over process, voltage, and temperature variations for adequate image-rejection and signal modulation/demodulation. While the use of symmetrical layout and large inter-digitated devices minimize both systematic and random mismatches, this solution alone may not succeed in achieving the stringent performance requirements dictated by modern wireless standards particularly as the technology scales into the sub-100nm regime, necessitating both phase and gain calibration of the mismatched I/Q channels post-fabrication. Given the necessity for precise RF quadrature signal synthesis, the goal of this work is to investigate low-power low-phase-noise quadrature oscillator (QVCO) topologies with an integrated phase calibration feature.
The first part of this work focuses on the analysis and modeling of cross-coupled LC QVCOs. The analysis focuses on understanding the oscillator basic performance characteristics, design trade-offs, phase-noise performance, effect of including phase shift in the coupling paths, and on examining the quadrature accuracy in presence of process variations. New design parameters and circuit insight are developed and a generalized first order linear model and a one-port model are proposed. Particularly, we introduce the concept of an effective core and coupling transconductances to explain various oscillator properties. Additionally, a new incremental circuit element — the quadrature resistance — is introduced to evaluate the effect of coupling on the open-loop quality factor and hence on the oscillator phase noise performance. Mechanisms affecting the mode selectivity are identified and modeled. A qualitative and quantitative study of the effect of mismatch on the phase imbalance and amplitude error is presented. Particularly, closed-form intuitive expressions of the phase imbalance and amplitude error are derived and verified via circuit simulation.
Based on our understanding of the various mechanisms affecting the quadrature accuracy, the second part of this work introduces a very efficient quadrature phase calibration technique based on the disconnected-source parallel-coupled LC QVCO topology. The phase-tunable LC QVCO (PT-QVCO) achieves an ultra-wide I/Q phase tuning range without affecting the relative amplitude error or consuming additional power or chip area. Additionally, in restoring the phase balance, it is observed that the proposed method restores the phase noise performance to its optimal value which presents a potential advantage over classical calibration techniques. Time domain measurements performed on a 5 GHz prototype show that I/Q signals with phase error up to ~±30°, beyond which the VCO cores are unlocked, can be driven to perfect quadrature phase. The PT-QVCO can be tuned from 3.87-4.45 GHz at the negative mode and 4.4-5.4 GHz at the positive mode, a total of ~1.5 GHz. The fabricated circuit including pad structures occupies an area of 1.1x0.7 mm² and drains 18mW (excluding buffer circuits) from a 1.8 V supply voltage.
The third part of this work introduces a new low-power, low-phase-noise super harmonic injection-coupled LC QVCO (IC-QVCO) topology. Analysis of the waveform accuracy reveals an inverse dependence of the quadrature error on the tank quality factor thus allowing circuit optimization for both low phase noise and precise quadrature synthesis. Additionally, a tunable tail filter (TTF) is incorporated to calibrate the residual quadrature imbalance in presence of a 3-σ variation in the device parameters. An X-band IC-QVCO prototype with a TTF implemented in a 0.18μm RF CMOS process, achieves a measured phase noise figure-of-merit ranging from 177.3 to 182.6 dBc/Hz along the 9.0 to 9.6 GHz frequency tuning range while dissipating only 9mW from the 1.8V supply. The TTF reduces both the 1/f² and 1/f³ phase noise and calibrates the residual phase error within ±11° post-fabrication without affecting the relative amplitude error or the phase noise performance. The circuit performance compares favorably with recently published work.
In the fourth part of this work, we explore the implementation of LC QVCOs as potential I/Q sources at millimeter-wave (MMW) frequencies. Among the several design challenges that emerge as the oscillator frequency is scaled into the MMW band, precise quadrature synthesis and adequate frequency tuning range are among the hardest to achieve. After describing the limitation of using an MOS varactor and a digitally controlled switch capacitor array for frequency tuning, we propose an alternative frequency tuning technique based on the fundamental operation of LC QVCOs. The off-resonance operation, which is defined by the coupling network, suggests varying the coupling current to achieve frequency tuning. In essence, by modifying the bias current of the coupling transistors (GMc-tuning), a wide and linear frequency tuning range can be achieved. Extensive simulation results of a 60 GHz prototype, implemented in a 90 nm commercial RF CMOS process, demonstrates a 5 GHz of frequency tuning range (57.5 GHz → 62.5 GHz), a tuning sensitivity of 1GHz/mA, and a 4dB improvement in the phase noise compared to a varactor solution.
Finally, the Appendix includes recent research work on the analysis and design of gPh.D.
While resting in bed due to illness, the Dutch scientist Christiaan Huygens keenly observed that the pendulums of two clocks hanging on the wall moved synchronously when the clocks were hung close to each other. He concluded that these two oscillatory systems were forced to move in unison by virtue of mechanical coupling through the wall. In essence, each pendulum injected mechanical vibrations into the wall that was strong enough to lock the adjacent pendulum into synchronous motion. Injection locking of oscillatory systems plays a critical role in communication systems ranging from frequency division, to generating clocks (oscillators) with finer phase separation, to the synthesis of orthogonal (quadrature) clocks. All communication systems have the same basic form. Firstly, there will some type of an information or data source which can be a keyboard or a microphone in a smartphone. The source is connected to a receiver by some sort of a channel. In wireless systems, the channel is the air medium. Moreover, to comply with the FCC and 3GPP requirements, data can only be transmitted wirelessly within a predefined set of frequencies and with stringent emission requirements to avoid interference with other wireless systems. These frequencies are generated by high fidelity clock sources, also known as oscillators. Consider a group of people sharing the same room and hence the same channel want to share information. Without regulating the “loudness” of each communicating ensemble, the quality of communication can be severely impaired. Moreover, it is to be expected that information can be shared more efficiently if each pair is allocated non-overlapping timeslots – speak when others are quiet. Called time orthogonality, all wireless systems require precise orthogonal (quadrature) clock sources to improve the communication efficiency. The precision of quadrature clocks is determined by the amplitude and phase accuracy. This dissertation takes a deep dive into the analysis and implementation of high accuracy quadrature (I/Q) clock sources using the concept of injection locking. These I/Q clocks or oscillators, also known as quadrature voltage controlled oscillators (QVCOs), have gained enormous popularity in the last decade. The first part of this work focuses on the analysis and modeling of QVCOs. The analysis focuses on understanding the oscillator basic performance characteristics, and on examining the quadrature accuracy in presence of process variations. New design parameters and circuit insight are developed and a generalized first order linear model and a one-port model are proposed. A qualitative and quantitative study of the effect of mismatch on the phase imbalance and amplitude error is presented. Particularly, closed-form intuitive expressions of the phase imbalance and amplitude error are derived and verified via circuit simulation. Based on our understanding of the various mechanisms affecting the quadrature accuracy, the second part of this work introduces a very efficient quadrature phase calibration technique based The phase-tunable QVCO (PT-QVCO) achieves an ultra-wide I/Q phase tuning range without affecting the oscillator other performance metrics. The proposed topology was successfully verified in silicon using a 5GHz prototype. The third part of this work introduces a new low-power, low-phase-noise injection coupled QVCO (IC-QVCO) topology. An X-band IC-QVCO prototype was successfully verified in a 0.18m RF CMOS process. In the fourth part of this work, we explore the implementation of QVCOs as potential I/Q sources at millimeter-wave (MMW) frequencies. Among the several design challenges that emerge as the oscillator frequency is scaled into the MMW band, precise quadrature synthesis and adequate frequency tuning range are among the hardest to achieve. After describing the limitation of using an conventional frequency tuning techniques, we propose an alternative approach based on the fundamental operation of QVCOs that outperforms existing solutions.
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Laraba, Asma. « Conception en vue de test de convertisseurs de signal analogique-numérique de type pipeline ». Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00947360.
Texte intégralRésumé :
La Non-Linéarité-Différentielle (NLD) et la Non-Linéarité-Intégrale (NLI) sont les performances statiques les plus importantes des Convertisseurs Analogique-Numérique (CAN) qui sont mesurées lors d'un test de production. Ces deux performances indiquent la déviation de la fonction de transfert du CAN par rapport au cas idéal. Elles sont obtenues en appliquant une rampe ou une sinusoïde lente au CAN et en calculant le nombre d'occurrences de chacun des codes du CAN.Ceci permet la construction de l'histogramme qui permet l'extraction de la NLD et la NLI. Cette approche requiert lacollection d'une quantité importante de données puisque chacun des codes doit être traversé plusieurs fois afin de moyenner le bruit et la quantité de données nécessaire augmente exponentiellement avec la résolution du CAN sous test. En effet,malgré que les circuits analogiques et mixtes occupent une surface qui n'excède pas généralement 5% de la surface globald'un System-on-Chip (SoC), leur temps de test représente souvent plus que 30% du temps de test global. Pour cette raison, la réduction du temps de test des CANs est un domaine de recherche qui attire de plus en plus d'attention et qui est en train deprendre de l'ampleur. Les CAN de type pipeline offrent un bon compromis entre la vitesse, la résolution et la consommation.Ils sont convenables pour une variété d'applications et sont typiquement utilisés dans les SoCs destinés à des applicationsvidéo. En raison de leur façon particulière du traitement du signal d'entrée, les CAN de type pipeline ont des codes de sortiequi ont la même largeur. Par conséquent, au lieu de considérer tous les codes lors du test, il est possible de se limiter à un sous-ensemble, ce qui permet de réduire considérablement le temps de test. Dans ce travail, une technique pour l'applicationdu test à code réduit pour les CANs de type pipeline est proposée. Elle exploite principalement deux propriétés de ce type deCAN et permet d'obtenir une très bonne estimation des performances statiques. La technique est validée expérimentalementsur un CAN 11-bit, 55nm de STMicroelectronics, obtenant une estimation de la NLD et de la NLI pratiquement identiques àla NLD et la NLI obtenues par la méthode classique d'histogramme, en utilisant la mesure de seulement 6% des codes.
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França, Ferreira João Alberto de. « Contribution to the Design of a Real-Time Fourier Transformer in Integrated Technology ». Thesis, Université Paris-Saclay (ComUE), 2019. http://www.theses.fr/2019SACLS502.
Texte intégralRésumé :
L'accroissement constant des bandes passantes et des débits dans les applications de la vie courante (e.g., télécommunications, objets connectés), comme dans des applications plus spécialisées (e.g., radar, observations en radioastronomie), impose de très fortes contraintes en termes de vitesse, consommation de puissance et dissipation thermique aux étages de conversion analogique-numérique des chaînes d'acquisition. Par conséquent une tendance actuelle consiste à effectuer le traitement de signaux (e.g., transformation de Fourier) dans le domaine analogique pour pouvoir traiter des signaux ultra-large bande avec faible latence et de manière plus efficace en termes énergétiques. Plusieurs architectures de traitement de signal analogique repose sur des blocs encore peu explorées dans la littérature : les filtres à retard de groupe arbitraires. Ces filtres sont plutôt réalisés en technologie SAW ou avec des structures microondes discrètes (non intégrés), conduisant à des filtres avec des bandes passantes limitées et beaucoup de pertes, dans le cas des dispositifs SAW, ou avec un encombrement et poids importantes, dans le cas des filtres microondes. Très peu de réalisations intégrées en semi-conducteurs ont été reporté à ce jour.L'innovation présentée dans cette thèse a deux aspects, un aspect architectural au niveau système, lequel a donné lieu à une proposition d'architecture pour un transformateur de Fourier analogique permettant d'améliorer les performances en précision par rapport aux autres architectures rapportées dans la littérature, et un aspect concernant le développement des méthodes de conception de filtres à retard de groupe linéaire et leur implémentation dans une technologie de circuit intégré. Trois réseaux de filtres différents ont été conçus en utilisant ces méthodes, un filtre passe-bande à minimum de phase dans une structure en échelle, un réseau passe-tout équilibré avec un retard de groupe linéaire à pente positive et un réseau passe-tout non équilibré avec un retard de groupe linéaire de pente négative. Il a aussi été démontré que les filtres passe-tout peuvent être transformés dans des filtres transversales basé sur la structure d'un amplificateur distribuéThe constant increase of bandwidths and bitrates in everyday applications (e.g., telecommunications, internet of things), as also in more specialized applications (e.g., radar, radio astronomy observations), imposes stringent constraints in terms of speed, power consumption and heat dissipation at the analog-to-digital conversion stages of acquisition chains. Therefore, a current trend is to perform signal processing (e.g., Fourier transform) in the analog domain to be able to process ultra-wideband signals with low latency and in a more energy-efficient way. Many of the analog signal processing architectures rely on blocks that have not been widely explored in the literature: arbitrary group delay filters. These filters are generally realized in SAW technology or with discrete (non-integrated) microwave structures, leading to filters with limited bandwidth and high loss, in the case of SAW devices, or with a large size and weight, in the case of microwave filters. Very few integrated circuit implementations have been reported to date.The innovation presented in this thesis has two aspects, a system-level architectural aspect, which gave rise to the proposal for an analog Fourier transformer architecture that enables improve the precision performance when compared to the previously reported architectures, and an aspect concerning the development of linear group delay filter design methods and their implementation in an integrated circuit technology. Three different filter networks were designed using these methods, a minimum phase band-pass ladder filter, a balanced all-pass network with positive-slope linear group delay, and a balanced all-pass network with a linear group delay of negative slope. It has also been shown that the all-pass filters can be transformed into distributed amplifier-based transversal filters
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Douglas, Dale Scott. « Flicker noise in cmos lc oscillators ». Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/26550.
Texte intégralRésumé :
Sources of flicker noise generation in the cross-coupled negative resistance oscillator (NMOS, PMOS, and CMOS) are explored. Also, prior and current work in the area of phase noise modeling is reviewed, including the work of Leeson, Hajimiri, Hegazi, and others, seeking the mechanisms by which flicker noise is upconverted.
A Figure of Merit (FOM) methodology suitable to the 1/f3 phase noise region is also developed, which allows a new quantity, FOM1, to be defined. FOM1 is proportional to flicker noise upconverted, thus allowing the effectiveness of flicker noise upconversion suppression techniques to be evaluated, despite possibly changing bias points or tank Q, which would change phase noise and FOM in the 1/f2 region.
The work of Hajimiri is extended with a simple Amplitude ISF DC component estimator for the special case of LC CMOS oscillators. A method of adaptive control of an oscillator core is presented, as well, comprised of a CMOS oscillator with a digitally adjustable N and P width, and a circuit (which is essentially a tracking ADC) which repeatedly adjusts the relative N to P width dependent on the estimate to maintain the condition of minimum flicker noise upconversion. A fixed calibration constant is sufficient to allow convergence to within 0.7dB of optimal FOM1 for all cases of N width, for a varactorless oscillator test cell.
Finally, a circuit is proposed which would allow the flicker noise reduction technique of cycling to accumulation to be applied to continuous time oscillators, but is not rigorously vetted.
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Chitnis, Danial. « Single photon avalanche diodes for optical communications ». Thesis, University of Oxford, 2013. http://ora.ox.ac.uk/objects/uuid:5fd582dd-8167-4fe4-88f8-871ba905ade1.
Texte intégralRésumé :
In order to improve the sensitivity of an optical receiver, the gain and the collection area of the photo-detectors within the receiver should be increased. Detectors with internal gain such as avalanche photodiodes (APD) are usually used to increase the sensitivity of the receiver. One problem with APDs is the sensitivity of their gain to their bias voltage, which makes them challenging to be fabricated in a standard CMOS process due to variations in their gain. However, when an APD is biased over its breakdown voltage, it is sensitive to a single photon, hence, referred to as a single photon avalanche diodes (SPAD). The SPADs are photon-counting detectors, which are less sensitive to their bias voltage, and can be integrated with rest of the electronic circuitry that form an optical receiver. An avalanche diode requires dedicated circuits to be operated in the SPAD mode. These circuits make the diode insensitive to an incident photon for a duration that is known as deadtime. Unfortunately, The collection area of the PD, APD, and SPADs are limited to their capacitance. Hence, a large photo-detector leads to a larger capacitance, which reduces the bandwidth of the receiver. In this thesis, a photon counting optical receiver based on an array of SPADs is proposed which increases the collection area with a low output capacitance. The avalanche diode and peripheral circuits which operate and readout-out the SPAD array are fabricated in the commercially available UMC 0.18 μm CMOS process. Initially, the avalanche diode is tested and characterised. A high performance circuit is then designed and tested which is able to achieve short deadtimes up to 4 ns. Once the photon counting operation of the SPAD is verified, a numerical model is developed to investigate the influence of several factors, including the deadtime, on the performance of the photon-counting detector in a communication link. Based on the simulation results, which show the advantages of an array over a single detector, a prototype detector array of 64 asynchronous SPADs is designed and tested. This array uses a high-speed readout mechanism which is inspired by the current steering digital-to-analogue converters. Bit error ratio tests (BERT) verify the photon counting capability of the proposed detector, and a bit error rate of 1E-3 has been achieved at data rate of 100 Mbps. In addition, the array of SPAD is compatible with a front-end of conventional optical receiver which uses a photodiode as a photo detector.
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Fisher, Andrew N. « Efficient, sound formal verification for analog/mixed-signal circuits ». Thesis, The University of Utah, 2016. http://pqdtopen.proquest.com/#viewpdf?dispub=10003590.
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The increasing demand for smaller, more efficient circuits has created a need for both digital and analog designs to scale down. Digital technologies have been successful in meeting this challenge, but analog circuits have lagged behind due to smaller transistor sizes having a disproportionate negative affect. Since many applications require small, low-power analog circuits, the trend has been to take advantage of digital's ability to scale by replacing as much of the analog circuitry as possible with digital counterparts. The results are known as \emph{digitally-intensive analog/mixed-signal} (AMS) circuits. Though such circuits have helped the scaling problem, they have further complicated verification. This dissertation improves on techniques for AMS property specifications, as well as, develops sound, efficient extensions to formal AMS verification methods. With the \emph{language for analog/mixed-signal properties} (LAMP), one has a simple intuitive language for specifying AMS properties. LAMP provides a more procedural method for describing properties that is more straightforward than temporal logic-like languages. However, LAMP is still a nascent language and is limited in the types of properties it is capable of describing. This dissertation extends LAMP by adding statements to ignore transient periods and be able to reset the property check when the environment conditions change. After specifying a property, one needs to verify that the circuit satisfies the property. An efficient method for formally verifying AMS circuits is to use the restricted polyhedral class of \emph{zones}. Zones have simple operations for exploring the reachable state space, but they are only applicable to circuit models that utilize constant rates. To extend zones to more general models, this dissertation provides the theory and implementation needed to soundly handle models with ranges of rates. As a second improvement to the state representation, this dissertation describes how octagons can be adapted to model checking AMS circuit models. Though zones have efficient algorithms, it comes at a cost of over-approximating the reachable state space. Octagons have similarly efficient algorithms while adding additional flexibility to reduce the necessary over-approximations. Finally, the full methodology described in this dissertation is demonstrated on two examples. The first example is a switched capacitor integrator that has been studied in the context of transforming the original formal model to use only single rate assignments. Th property of not saturating is written in LAMP, the circuit is learned, and the property is checked against a faulty and correct circuit. In addition, it is shown that the zone extension, and its implementation with octagons, recovers all previous conclusions with the switched capacitor integrator without the need to translate the model. In particular, the method applies generally to all the models produced and does not require the soundness check needed by the translational approach to accept positive verification results. As a second example, the full tool flow is demonstrated on a digital C-element that is driven by a pair of RC networks, creating an AMS circuit. The RC networks are chosen so that the inputs to the C-element are ordered. LAMP is used to codify this behavior and it is verified that the input signals change in the correct order for the provided SPICE simulation traces.
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Hou, Junwei. « Concurrent fault simulation for mixed-signal circuits ». Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/15735.
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Chen, Jin. « Fault modeling and test techniques for analog and mixed-signal circuits / ». Digital version accessible at:, 1998. http://wwwlib.umi.com/cr/utexas/main.
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SAMPATH, HEMANTH KUMAR. « A MODULE GENERATION ENVIRONMENT FOR MIXED-SIGNAL CIRCUITS ». University of Cincinnati / OhioLINK, 2003. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1052321882.
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KANKIPATI, SUNDER RAJAN. « MACRO MODEL GENERATION FOR SYNTHESIS OF ANALOG AND MIXED SIGNAL CIRCUITS ». University of Cincinnati / OhioLINK, 2004. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1077297705.
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Clewell, Matthew John. « Reducing signal coupling and crosstalk in monolithic, mixed-signal integrated circuits ». Thesis, Kansas State University, 2013. http://hdl.handle.net/2097/18138.
Texte intégralRésumé :
Master of ScienceDepartment of Electrical Engineering
William B. Kuhn
Designers of mixed-signal systems must understand coupling mechanisms at the system, PC board, package and integrated circuit levels to control crosstalk, and thereby minimize degradation of system performance. This research examines coupling mechanisms in a RF-targeted high-resistivity partially-depleted Silicon-on-Insulator (SOI) IC process and applying similar coupling mitigation strategies from higher levels of design, proposes techniques to reduce coupling between sub-circuits on-chip. A series of test structures was fabricated with the goal of understanding and reducing the electric and magnetic field coupling at frequencies up to C-Band. Electric field coupling through the active-layer and substrate of the SOI wafer is compared for a variety of isolation methods including use of deep-trench surrounds, blocking channel-stopper implant, blocking metal-fill layers and using substrate contact guard-rings. Magnetic coupling is examined for on-chip inductors utilizing counter-winding techniques, using metal shields above noisy circuits, and through the relationship between separation and the coupling coefficient. Finally, coupling between bond pads employing the most effective electric field isolation strategies is examined. Lumped element circuit models are developed to show how different coupling mitigation strategies perform. Major conclusions relative to substrate coupling are 1) substrates with resistivity 1 kΩ·cm or greater act largely as a high-K insulators at sufficiently high frequency, 2) compared to capacitive coupling paths through the substrate, coupling through metal-fill has little effect and 3) the use of substrate contact guard-rings in multi-ground domain designs can result in significant coupling between domains if proper isolation strategies such as the use of deep-trench surrounds are not employed. The electric field coupling, in general, is strongly dependent on the impedance of the active-layer and frequency, with isolation exceeding 80 dB below 100 MHz and relatively high coupling values of 40 dB or more at upper S-band frequencies, depending on the geometries and mitigation strategy used. Magnetic coupling was found to be a strong function of circuit separation and the height of metal shields above the circuits. Finally, bond pads utilizing substrate contact guard-rings resulted in the highest degree of isolation and the lowest pad load capacitance of the methods tested.