Literatura académica sobre el tema "Vrram"
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Artículos de revistas sobre el tema "Vrram"
Sun, Wookyung, Sujin Choi, Bokyung Kim y Hyungsoon Shin. "Effect of Initial Synaptic State on Pattern Classification Accuracy of 3D Vertical Resistive Random Access Memory (VRRAM) Synapses". Journal of Nanoscience and Nanotechnology 20, n.º 8 (1 de agosto de 2020): 4730–34. http://dx.doi.org/10.1166/jnn.2020.17798.
Texto completoChen, Zhisheng, Renjun Song, Qiang Huo, Qirui Ren, Chenrui Zhang, Linan Li y Feng Zhang. "Analysis of Leakage Current of HfO2/TaOx-Based 3-D Vertical Resistive Random Access Memory Array". Micromachines 12, n.º 6 (26 de mayo de 2021): 614. http://dx.doi.org/10.3390/mi12060614.
Texto completoSun, Wookyung, Sujin Choi, Bokyung Kim y Junhee Park. "Three-Dimensional (3D) Vertical Resistive Random-Access Memory (VRRAM) Synapses for Neural Network Systems". Materials 12, n.º 20 (22 de octubre de 2019): 3451. http://dx.doi.org/10.3390/ma12203451.
Texto completoAlimkhanuly, Batyrbek, Sanghoek Kim, Lok-won Kim y Seunghyun Lee. "Electromagnetic Analysis of Vertical Resistive Memory with a Sub-nm Thick Electrode". Nanomaterials 10, n.º 9 (20 de agosto de 2020): 1634. http://dx.doi.org/10.3390/nano10091634.
Texto completoChoi, Sujin, Wookyung Sun y Hyungsoon Shin. "Analysis of Read Margin and Write Power Consumption of a 3-D Vertical RRAM (VRRAM) Crossbar Array". IEEE Journal of the Electron Devices Society 6 (2018): 1192–96. http://dx.doi.org/10.1109/jeds.2018.2873016.
Texto completoWu, Min‐Ci, Yi‐Hsin Ting, Jui‐Yuan Chen y Wen‐Wei Wu. "Low Power Consumption Nanofilamentary ECM and VCM Cells in a Single Sidewall of High‐Density VRRAM Arrays". Advanced Science 6, n.º 24 (7 de octubre de 2019): 1902363. http://dx.doi.org/10.1002/advs.201902363.
Texto completoChoi, Sujin, Wookyung Sun y Hyungsoon Shin. "Analysis of Cell Variability Impact on a 3-D Vertical RRAM (VRRAM) Crossbar Array Using a Modified Lumping Method". IEEE Transactions on Electron Devices 66, n.º 1 (enero de 2019): 759–65. http://dx.doi.org/10.1109/ted.2018.2878440.
Texto completoYu, Jie, Woyu Zhang, Danian Dong, Wenxuan Sun, Jinru Lai, Xu Zheng, Tiancheng Gong et al. "Long-Term Accuracy Enhancement of Binary Neural Networks Based on Optimized Three-Dimensional Memristor Array". Micromachines 13, n.º 2 (17 de febrero de 2022): 308. http://dx.doi.org/10.3390/mi13020308.
Texto completoLo, Shih-Che y Hung-Hsu Tsai. "Design of 3D Virtual Reality in the Metaverse for Environmental Conservation Education Based on Cognitive Theory". Sensors 22, n.º 21 (30 de octubre de 2022): 8329. http://dx.doi.org/10.3390/s22218329.
Texto completoChaudhry, Arif, Jeremie D. Oliver, Krishna S. Vyas, Nho V. Tran, Jorys Martinez-Jorge, David Larson, Eric Dozois, Heidi Nelson y Oscar J. Manrique. "Comparison of Outcomes in Oncoplastic Pelvic Reconstruction with VRAM versus Omental Flaps: A Large Cohort Analysis". Journal of Reconstructive Microsurgery 35, n.º 06 (18 de enero de 2019): 425–29. http://dx.doi.org/10.1055/s-0038-1677524.
Texto completoTesis sobre el tema "Vrram"
Ezzadeen, Mona. "Conception d'un circuit dédié au calcul dans la mémoire à base de technologie 3D innovante". Electronic Thesis or Diss., Aix-Marseille, 2022. http://theses.univ-amu.fr.lama.univ-amu.fr/221212_EZZADEEN_955e754k888gvxorp699jljcho_TH.pdf.
Texto completoWith the advent of edge devices and artificial intelligence, the data deluge is a reality, making energy-efficient computing systems a must-have. Unfortunately, classical von Neumann architectures suffer from the high cost of data transfers between memories and processing units. At the same time, CMOS scaling seems more and more challenging and costly to afford, limiting the chips' performance due to power consumption issues.In this context, bringing the computation directly inside or near memories (I/NMC) seems an appealing solution. However, data-centric applications require an important amount of non-volatile storage, and modern Flash memories suffer from scaling issues and are not very suited for I/NMC. On the other hand, emerging memory technologies such as ReRAM present very appealing memory performances, good scalability, and interesting I/NMC features. However, they suffer from variability issues and from a degraded density integration if an access transistor per bitcell (1T1R) is used to limit the sneak-path currents. This thesis work aims to overcome these two challenges. First, the variability impact on read and I/NMC operations is assessed and new robust and low-overhead ReRAM-based boolean operations are proposed. In the context of neural networks, new ReRAM-based neuromorphic accelerators are developed and characterized, with an emphasis on good robustness against variability, good parallelism, and high energy efficiency. Second, to resolve the density integration issues, an ultra-dense 3D 1T1R ReRAM-based Cube and its architecture are proposed, which can be used as a 3D NOR memory as well as a low overhead and energy-efficient I/NMC accelerator
Bartholomé, Lenka [Verfasser], Vera [Akademischer Betreuer] Schellerer y Vera [Gutachter] Schellerer. "Komplikationen am Hebedefekt nach vertikaler Rektus-abdominis-Muskel (VRAM)-Lappenplastik -Erfahrungen bei 192 Patienten- / Lenka Bartholomé ; Gutachter: Vera Schellerer ; Betreuer: Vera Schellerer". Erlangen : Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), 2019. http://d-nb.info/1201886821/34.
Texto completoHsiung, W. C. y 熊玟清. "A Frame Store Designed with VRAM Approach to Radar Information". Thesis, 1995. http://ndltd.ncl.edu.tw/handle/00034741765688514060.
Texto completo義守大學
電機工程研究所
83
A non-interlaced raster scan display which has a screen resolution of 1280X1024 pixels with 256 colors is suitable to be used to display the sampled radar data. There are 1280X1024X8 bits data stored in an eight plane frame store. The frame store is constructed by ten video random access memory devices (VRAM) with size of 256kX4 bits each. Using 386/486 CPU's protected mode and IBM ISA bus architecture, the frame store can be accessed by the microprocessors and multiple radar scan converters to store and transfer the data to the raster scan radar display improving the disadvantages of traditional radar display (Plan Position Indicator: PPI). This makes the architecture of frame store central to the radar display system. So, the major purpose of this paper is to describe the design and construction of a frame store. The access rate of frame store is an important factor which affects the performance of the radar display system. The multipe I/O port VRAM device are chosen to make up the frame store. VRAM has dual ports, the DRAM port and SAM prot, which can be operated independently. This increases the access rate of frame store. The line scan rate is divided cyclely to three memory access cycles. There are update read, update write, and read tranfer cycle (DRAM tranfers data to SAM for next screen refresh). The screen read cycle is executed in active video time during line scan rate as the SAM port operates independently. Five bytes data is read parallelly from frame store transfered into screen processor in 41.7ns time period. During the screen read cycle, the 8 bit data is fed serially to D/A converter to generate the red, green, and blue analog signals respectively for raster scan display. The pixel rate is 119.843 Mhz.
Libros sobre el tema "Vrram"
Corporation, Toshiba. MOS memory (VRAM, SRAM). Tokyo: Toshiba Corporation, 1991.
Buscar texto completoCorporation, Toshiba. MOS memory (VRAM): Data book. Tokyo: Toshiba Corporation, 1993.
Buscar texto completoCapítulos de libros sobre el tema "Vrram"
Weik, Martin H. "VRAM". En Computer Science and Communications Dictionary, 1906. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/1-4020-0613-6_20965.
Texto completoFlügel, M. "VRAM-Lappen". En Fortschritte in der Chirurgie im letzten Jahrzehnt, 199. Berlin, Heidelberg: Springer Berlin Heidelberg, 1992. http://dx.doi.org/10.1007/978-3-662-07303-2_88.
Texto completoErdmann, D., A. Petracic, M. Sauerbier, H. Menke y G. Germann. "Der „Vertical/Transverse Rectus abdominis Muscle“ (VRAM/TRAM)-Lappen zur Deckung langstreckiger osteokutaner Defekte der Sternumregion". En Bilanz zur Jahrtausendwende, 1344–45. Berlin, Heidelberg: Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/978-3-642-60248-1_378.
Texto completoSilva, Jason, Amy Jackson y Justin Broyles. "Plastic Surgery and Flap Graft Management of Radial Forearm, VRAM, and TRAM Flaps in Critically Ill Cancer Patients". En Oncologic Critical Care, 1–9. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-74698-2_161-1.
Texto completoSilva, Jason, Amy Jackson y Justin Broyles. "Plastic Surgery and Flap Graft Management of Radial Forearm, VRAM, and TRAM Flaps in Critically Ill Cancer Patients". En Oncologic Critical Care, 1719–26. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-319-74588-6_161.
Texto completoLefèvre, Jérémie y Emmanuel Tiret. "VRAM flap". En Operative Surgery of the Colon, Rectum and Anus, Sixth Edition, 675–81. CRC Press, 2015. http://dx.doi.org/10.1201/b18337-78.
Texto completo"altenheim norra vram". En raumverloren, 114–17. Birkhäuser, 2014. http://dx.doi.org/10.1515/9783038210856.114.
Texto completo"Norra Vram Nursing Home". En lost in space, 114–17. Birkhäuser, 2014. http://dx.doi.org/10.1515/9783038211204-021.
Texto completoActas de conferencias sobre el tema "Vrram"
Piccolboni, G., G. Molas, D. Garbin, T. Werner, E. Vianello, B. DeSalvo, G. Ghibaudo y L. Perniola. "Investigation of variability in Vertical Resistive RAM (VRRAM): Physical Model". En 2016 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2016. http://dx.doi.org/10.7567/ssdm.2016.b-7-04.
Texto completoBaek, I. G., C. J. Park, H. Ju, D. J. Seong, H. S. Ahn, J. H. Kim, M. K. Yang et al. "Realization of vertical resistive memory (VRRAM) using cost effective 3D process". En 2011 IEEE International Electron Devices Meeting (IEDM). IEEE, 2011. http://dx.doi.org/10.1109/iedm.2011.6131654.
Texto completoPiccolboni, G., G. Molas, J. M. Portal, R. Coquand, M. Bocquet, D. Garbin, E. Vianello et al. "Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications". En 2015 IEEE International Electron Devices Meeting (IEDM). IEEE, 2015. http://dx.doi.org/10.1109/iedm.2015.7409717.
Texto completoZhang, Leqi, Stefan Cosemans, Dirk J. Wouters, Bogdan Govoreanu, Guido Groeseneken y Malgorzata Jurczak. "Analysis of vertical cross-point resistive memory (VRRAM) for 3D RRAM design". En 2013 5th IEEE International Memory Workshop (IMW). IEEE, 2013. http://dx.doi.org/10.1109/imw.2013.6582122.
Texto completoWu, T. Y., Y. S. Chen, P. Y. Gu, W. S. Chen, H. Y. Lee, P. S. Chen, K. H. Tsai et al. "Vertical resistive switching memory (VRRAM): A real 3D device demonstration and analysis of high-density application". En 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2014. http://dx.doi.org/10.1109/vlsi-tsa.2014.6839683.
Texto completoGong, Tiancheng, Qing Luo, Hangbing Lv, Xiaoxin Xu, Jie Yu, Peng Yuan, Danian Dong et al. "Switching and Failure Mechanism of Self-Selective Cell in 3D VRRAM by RTN-Based Defect Tracking Technique". En 2018 IEEE International Memory Workshop (IMW). IEEE, 2018. http://dx.doi.org/10.1109/imw.2018.8388852.
Texto completoHaitong Li, Tony F. Wu, Subhasish Mitra y H. S. Philip Wong. "Device-architecture co-design for hyperdimensional computing with 3d vertical resistive switching random access memory (3D VRRAM)". En 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA). IEEE, 2017. http://dx.doi.org/10.1109/vlsi-tsa.2017.7942490.
Texto completoLi, Haitong, Tony F. Wu, Abbas Rahimi, Kai-Shin Li, Miles Rusch, Chang-Hsien Lin, Juo-Luen Hsu et al. "Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition". En 2016 IEEE International Electron Devices Meeting (IEDM). IEEE, 2016. http://dx.doi.org/10.1109/iedm.2016.7838428.
Texto completoPark, Seong-Geon, Min Kyu Yang, Hyunsu Ju, Dong-Jun Seong, Jung Moo Lee, Eunmi Kim, Seungjae Jung et al. "A non-linear ReRAM cell with sub-1μA ultralow operating current for high density vertical resistive memory (VRRAM)". En 2012 IEEE International Electron Devices Meeting (IEDM). IEEE, 2012. http://dx.doi.org/10.1109/iedm.2012.6479084.
Texto completoWong, Tamar Hei Ting y Kee Ka Ki Wong. "VRgram". En SA '16: SIGGRAPH Asia 2016. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2996376.2996380.
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