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Artículos de revistas sobre el tema "VERILOG IMPLEMENTATION"

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Autor: Grafiati

Publicado: 11 de septiembre de 2023

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1

Koti, Mr Manjunath y Dr Basavaraj I. Neelgar. "CAN Tx Frame Implementation using Verilog". Journal of University of Shanghai for Science and Technology 23, n.º 07 (29 de julio de 2021): 1303–13. http://dx.doi.org/10.51201/jusst/21/07311.

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This article discusses the concept of CAN protocol and its implementation in verilog language. Initially the CAN protocol description is given in brief with the block diagram, later its design, implementation in verilog code is presented. The CAN transmission (Tx) data Frame is realized using verilog code, this is achieved by defining individual sub-blocks verilog codes and combining these to get the CAN transmission of data frame. In the year 1986, CAN data link layer protocol was introduced in SAE conference. In 1993, CAN protocol and high speed physical layer were internationally accredited as ISO 11898. As on today it has 11898-1 to 4 standard documents. The CAN 1.0, 2.0 versions were initially had fixed data rate for the entire frame. In 2012, CAN-FD (Flexible data rate) protocol was introduced. This will allow data phase a second higher bit rate, along with this restriction of 8 bytes is extended up to 64 bytes.In this paper CAN Tx data frame is realized using Xilinx 14.7 version using verilog language.

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2

Paramahamsa, Prof Mr YRK. "Implementation of Zigbee Transmitter using Verilog". International Journal for Research in Applied Science and Engineering Technology V, n.º III (28 de marzo de 2017): 1010–17. http://dx.doi.org/10.22214/ijraset.2017.3185.

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3

Shet, Ganesh Gopal, Jamuna V, Shravani S, Nayana H G y Pramod Kumar S. "Implementation of AES Algorithm using Verilog". JNNCE Journal of Engineering and Management 4, n.º 1 (30 de noviembre de 2020): 17. http://dx.doi.org/10.37314/jjem.2020.040103.

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4

Krishna, T. Rama, T. Krishna Murthy, N. Vilasrao Sarode, P. Srilakshmi y V. Geetha Sri. "Verilog HDL using LTE Implementation MAP Algorithm". International Journal of Innovative Research in Computer Science and Technology 10, n.º 2 (30 de marzo de 2022): 611–14. http://dx.doi.org/10.55524/ijircst.2022.10.2.115.

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In many communication systems, turbo coding Techniques for Encoding and Decoding are employed to repair errors. As compared to other error correction codes, turbo codes provide great error correcting capabilities. For the implementation of the Turbo decoder, a Very Large Scale Integration (VLSI) architecture is suggested in this study. The Maximum-a-Posteriori (MAP) algorithm is employed at the decoder side, where soft-in-soft-out decoders, interleaves, and deinterleavers are all used. The usage of the MAP algorithm reduces the quantity of iterations necessary to decode the information bits being transferred. This research employs a system for the encoder component that consists of two recursive convolutional encoders and a pseudorandom interleaver on the encoder side. Tools from Octave and Xilinx Vivado are used for the Turbo encoding and decoding. The system is synthesised and implemented using a specialised integrated circuit.

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5

Zheng, Li Kun, Ya Li Chen y Zhe Ying Li. "Design and Implementation of USB Transceiver with Verilog". Applied Mechanics and Materials 462-463 (noviembre de 2013): 604–8. http://dx.doi.org/10.4028/www.scientific.net/amm.462-463.604.

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The Universal Serial Bus Transceiver is one of the important functional blocks of USB controller, which can transmit and receive data to or from USB devices. In this paper, USB Transceiver is designed and implemented with Verilog HDL, This includes functions such as, data serialization, bit stuffing, NRZI encoding and NRZI decoding, bit destuffing, deserialization. The transceiver is simulated by the modelsim software and the simulation wave is gave.

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6

Perali, Sri Phanindra, Nithin Krishna Madadi y Rohith Reddy. "RTL Implementation of AMBA AHB Protocol using Verilog". International Journal for Research in Applied Science and Engineering Technology 11, n.º 4 (30 de abril de 2023): 4056–63. http://dx.doi.org/10.22214/ijraset.2023.51179.

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Abstract: The enactment of a computer system heavily depends on the design of its bus interconnect. A poorly designed system bus can hinder the transmission of instructions and data between the processor and memory or between peripheral devices and memory. To address these challenges, the Advanced Microcontroller Bus Architecture (AMBA) provides an open standard for connecting and managing functional blocks in a System-on-Chip (SoC). This architecture allows for developing multi-processor designs with many controllers and peripherals while ensuring the system is designed correctly the first time. Furthermore, the AMBA specifications are royalty-free and platform-independent. They can be used with any processor architecture. The project will provide an RTL view and an extracted design summary of the AMBA AHB module at the system-on-chip level. The AMBA High-performance Bus (AHB) is another part of the AMBA family of conventions. The AHB is designed to support highperformance, high-clock system modules and serves as the system's high-performance backbone bus. The AHB enables the efficient connection of low-power peripheral functions to processors, on-chip memories, and external off-chip memory interfaces. All signal transitions in the AHB relate only to the rising clock edge, allowing AHB peripherals to be easily integrated into any design flow. The project also describes the AMBA AHB design and implementation using Verilog, with read/write operations implemented using the Xilinx simulator.

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7

J, Padmini y V. Nanammal. "FPGA Implementation of Digital Modulation Schemes Using Verilog HDL". International Journal for Research in Applied Science and Engineering Technology 10, n.º 9 (30 de septiembre de 2022): 560–67. http://dx.doi.org/10.22214/ijraset.2022.46596.

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Abstract: This paper describes the design and development of an FPGA-based digital Modulation Scheme for high-resolution Communication Application. We are focusing on implementation of Verilog based code simulation for fundamental and widely used digital modulation techniques such as Binary Amplitude-shift keying (BASK), Binary Frequency-shift keying (BFSK), Binary Phase-shift keying (BPSK) and Quadrature Phase Shift Keying(QPSK). In this work the idea of sinusoidal signals that have been generated is plain sailing in nature and based on fundamentals of signal sampling and quantization. Such concept of sinusoidal signals generation is not unfamiliar but somehow simplified using sampling and quantization in time and amplitude domain, respectively. The whole simulation is done on Modelsim and Xilinx-ISE using VERILOG Hardware descriptive language. The work has been accomplished on Thirty two bit serial data transmission with self-adjustable carrier frequency and bit duration length.

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8

Sreekanth, P. "Verilog Implementation of Image Compression Using Discrete Wavelet Transform". CVR Journal of Science & Technology 9, n.º 1 (1 de diciembre de 2015): 21–25. http://dx.doi.org/10.32377/cvrjst0905.

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9

Balakrishna, J. "Design and Implementation of RFID Controller using Verilog HDL". International Journal for Research in Applied Science and Engineering Technology 9, n.º VI (30 de junio de 2021): 4335–42. http://dx.doi.org/10.22214/ijraset.2021.35942.

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Manual monitoring consumes more time, man power and shows inaccurate results. So, automation is the solution to cover the problems stated. Barcode and RFID are two different forms of automated technology that are used for reading and collecting data. The RFID (Radio Frequency Identification) technology is a well-known wireless application for traceability, logistics and access control. The RFID controller is constructed in to demonstrate access control through the use of low-frequency RFID tags. These tags contain identification number which is read by the reader, sent to a database where it is compared with stored values. It works on the principle that If the tag’s identification number is in the system database, it gives access. If the data is not in the system database, it doesn’t give access. To implement these various blocks, include RFID transmitter, RFID receiver, Baud clock generator, Database are designed. The RFID Controller is designed using Verilog HDL in Xilinx ISE tool.

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10

Pari, Kumar. "Implementation of reduced memory Viterbi Decoder using Verilog HDL". IOSR Journal of Electronics and Communication Engineering 8, n.º 4 (2013): 73–79. http://dx.doi.org/10.9790/2834-0847379.

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11

Kong, Lingxi, Qirui Niu y Pai Yang. "Design And Implementation of UART Based on Verilog HDL". Highlights in Science, Engineering and Technology 38 (16 de marzo de 2023): 949–55. http://dx.doi.org/10.54097/hset.v38i.5981.

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As a two-way transmission channel, Universal Asynchronous Receiver/Transmitter (UART) not only greatly improves the efficiency of information transmission between computers and external devices, but also ensures the accuracy and consistency of information by eliminating metastable state, setting baud rate and other means. In this paper, on the basis of fully understanding the definition and function of UART, based on Verilog HDL language to build UART, and through Modelsim simulation, image and data. The experimental results show that the receiving and sending module of this module works well and meets the requirements of full-duplex serial communication equipment. There is no doubt that the design of this paper has made a more detailed explanation of the basic operating principle of UART, which will contribute to its further development.

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12

B R, Vishwas y Dr Sowmya K B. "Design and Implementation of Advanced Extensible Interface using Verilog". International Journal for Research in Applied Science and Engineering Technology 11, n.º 8 (31 de agosto de 2023): 1709–14. http://dx.doi.org/10.22214/ijraset.2023.55446.

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Abstract: Advanced eXtensible Interface, is an interface protocol defined by ARM as part of the AMBA standard. They comprise of AXI4, AXI4 Lite, AXI4 Stream. The AXI specification describes a point-to-point protocol between two interfaces, a master and a slave. The AXI protocol uses 5 channels, 2 for read transactions and 3 for write transactions. One of the key features of AXI4 is its support for burst transactions, which allows for efficient transfer of multiple data items in a single transaction, enhancing data throughput. AXI4-Lite is designed to provide a lightweight and efficient interface for communication between a master device and simpler peripheral devices or memory-mapped registers in a digital system. AXI4-Stream is developed for highthroughput, unidirectional data transfer between different components in a digital system. The design is done in Verilog.

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13

Yang, Hui Jing, Hao Fan y Huai Guo Dong. "Design and Implementation of a RISC Processor on FPGA". Advanced Materials Research 981 (julio de 2014): 58–61. http://dx.doi.org/10.4028/www.scientific.net/amr.981.58.

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This paper targets the computer architecture courses and presents an Field Programmable Gate Array implementation of a RISC Processor via Verilog HDL design. It has 8-bit instruction words and 4 general purpose registers. It have two instruction formats. And it has been designed with Verilog HDL, synthesized using Quatus II 12.0, simulated using ModelSim simulator, and then implemented on Altera Cyclone IV FPGA that has 484 available Input/Output pins and 50MHz clock oscillator. The final overall simulation's experimental data verify the correctness of the processor.

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14

Kangralkar, Sonali y Rajashri Khanai. "Design and Implementation of 8 point FFT using Verilog HDL". International Journal of Computer Applications 177, n.º 11 (17 de octubre de 2019): 4–6. http://dx.doi.org/10.5120/ijca2019919440.

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15

Ghelani, Harsh H., Nilesh L. Jha, Rohan Naik y Pragya Gupta. "FPGA Implementation of Configurable Linear Feedback Shift Register using Verilog". International Journal of Computer Sciences and Engineering 6, n.º 4 (30 de abril de 2018): 143–46. http://dx.doi.org/10.26438/ijcse/v6i4.143146.

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16

KumarN, Naveen, Rohith S y H. Venkatesh Kumar. "FPGA Implementation of OFDM Transceiver using Verilog - Hardware Description Language". International Journal of Computer Applications 102, n.º 6 (18 de septiembre de 2014): 8–13. http://dx.doi.org/10.5120/17817-8752.

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17

pani, M. Chakra, J. S. S. Ramaraju y Ch N. L. Sujatha. "Implementation of Cordic Algorithm for FPGA Based Computers Using Verilog". International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 03, n.º 08 (20 de agosto de 2014): 11487–96. http://dx.doi.org/10.15662/ijareeie.2014.0308082.

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18

Rziga, Faten Ouaja, Khaoula Mbarek, Sami Ghedira y Kamel Besbes. "An efficient Verilog-A memristor model implementation: simulation and application". Journal of Computational Electronics 18, n.º 3 (7 de junio de 2019): 1055–64. http://dx.doi.org/10.1007/s10825-019-01357-9.

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19

PadmaSree, L., Bekkam Satheesh y N. Dhanalakshmi. "FPGA Implementation of Interrupt Controller (8259) by using Verilog HDL". International Journal of Computer Applications 48, n.º 6 (30 de junio de 2012): 12–19. http://dx.doi.org/10.5120/7350-0045.

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20

Ravindran, Ajith. "Workshop on Introduction to Verilog Modeling and FPGA Implementation [Chapters]". IEEE Solid-State Circuits Magazine 15, n.º 3 (2023): 111–12. http://dx.doi.org/10.1109/mssc.2023.3285330.

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21

Wisniewski, Remigiusz. "Design of Petri Net-Based Cyber-Physical Systems Oriented on the Implementation in Field Programmable Gate Arrays". Energies 14, n.º 21 (28 de octubre de 2021): 7054. http://dx.doi.org/10.3390/en14217054.

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Two design flows of the Petri net-based cyber-physical systems oriented towards implementation in an FPGA are presented in the paper. The first method is based on the behavioural description of the system. The control part of the cyber-physical system is specified by an interpreted Petri net, and is described directly in the synthesisable Verilog hardware language for further implementation in the programmable device. The second technique involves splitting the design into sequential modules. In particular, adequate decomposition and synchronisation algorithms are proposed. The resulting modules are further modelled within the Verilog language as the composition of sequential automata. The presented design flows are supported by theoretical background, and templates of Verilog codes. The proposed techniques are illustrated by a real-life example of a multi-robot cyber-physical system, where each step of the proposed flows is explained in detail, including modelling, description of the system in the Verilog language, and final implementation within the FPGA device. The results obtained during the verification and validation confirm the proper functionality of the system designed by both design flows.

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22

Noorbasha, Fazal, K. Hari Kishore, P. Phani Sarad, A. Renuka, SK Meera Mohiddin, K. Jagadeesh Babu, B. V S. Phanindra y M. Manasa. "A VLSI implementation of train collision avoidance system using Verilog HDL". International Journal of Engineering & Technology 7, n.º 2.8 (19 de marzo de 2018): 386. http://dx.doi.org/10.14419/ijet.v7i2.8.10468.

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Now a days we see many train accidents that occur in railways. These accidents occur mainly due to cracks in the track, human errors and not identifying the opposite train at the right time. When the train meets with the accident lot of people lose their lives and huge amount of railway property is destroyed and it also takes lot of time to hold back to the normal situations. Most of the accidents happen due to human error and due to lack of communication between the trains and irregularity of Train Traffic Control System. Normally to prevent these accidents we place sensors on either side of the platform to identify the train at right time and to receive traffic signals at the platform properly. Here we came with some different approach which is easy to manage and implement and cost effective. Normally collision occurs when two trains approaching in opposite directions on same track. So, if we manage to prevent two trains travel on the same track then collision can be avoided. Here in this project we have implemented Verilog code to solve this problem. The purpose of this project is to write a Verilog code to detect the opposite train and deviate the train based on priority of the trains thus avoiding collision. In this project we have chosen four different types of trains namely Goods, Passenger, Superfast, Express and we have implemented train collision avoidance using Verilog code by giving priority to each type of train and preference is given to one train to avoid collision.

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23

Qiu, Mo, Simin Yu, Yuqiong Wen, Jinhu Lü, Jianbin He y Zhuosheng Lin. "Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control". International Journal of Bifurcation and Chaos 27, n.º 03 (marzo de 2017): 1750040. http://dx.doi.org/10.1142/s0218127417500407.

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In this paper, a novel design methodology and its FPGA hardware implementation for a universal chaotic signal generator is proposed via the Verilog HDL fixed-point algorithm and state machine control. According to continuous-time or discrete-time chaotic equations, a Verilog HDL fixed-point algorithm and its corresponding digital system are first designed. In the FPGA hardware platform, each operation step of Verilog HDL fixed-point algorithm is then controlled by a state machine. The generality of this method is that, for any given chaotic equation, it can be decomposed into four basic operation procedures, i.e. nonlinear function calculation, iterative sequence operation, iterative values right shifting and ceiling, and chaotic iterative sequences output, each of which corresponds to only a state via state machine control. Compared with the Verilog HDL floating-point algorithm, the Verilog HDL fixed-point algorithm can save the FPGA hardware resources and improve the operation efficiency. FPGA-based hardware experimental results validate the feasibility and reliability of the proposed approach.

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24

Moubark, Asraf Mohamed, Mohd Alauddin Mohd Ali, Hilmi Sanusi y Sawal Md Ali. "FPGA Implementation of Low Power Digital QPSK Modulator Using Verilog HDL". Journal of Applied Sciences 13, n.º 3 (15 de enero de 2013): 385–92. http://dx.doi.org/10.3923/jas.2013.385.392.

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25

Rizvi, Navaid Zafar, Rajat Arora y Niraj Agrawal. "Implementation and Verification of Synchronous FIFO using System Verilog Verification Methodology". Journal of Communications Technology, Electronics and Computer Science 2 (21 de noviembre de 2015): 18. http://dx.doi.org/10.22385/jctecs.v2i0.19.

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Developing complex nature of patterns & concurrency of Integrated Circuits has made conventional coordinated test- benches an unworkable answer for testing. Nowadays, testing as a word has been substituted with check. Confirmation specialists need to guarantee what goes to the plant for assembling is an exact representation of the specification of configuration. Verification is the maximum time consuming stage in the whole design process, thus it has become a necessity to minimize the time required to encounter the confirmation necessities. The relentless growth in the complexity of the system, has led to the requirement of a more advanced, well organized and automated approach for creating verification environments. As the designs gets complex, the probability of occurrence of bugs increases. This nеcеssitatеd the introduction of the verification phase for verifying the functionality of the IC and to detect the bugs at an early stage. In this paper, the synchronous FIFO design is verified using System Verilog Verification Environment.

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26

Samsudin, Nooraisyah N., Dr Suhaila Isaak y Dr Norlina Paraman. "Implementation of Optimized Low Pass Filter for ECG filtering using Verilog". Journal of Physics: Conference Series 2312, n.º 1 (1 de agosto de 2022): 012049. http://dx.doi.org/10.1088/1742-6596/2312/1/012049.

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Abstract Electrocardiogram is a standard method used for the diagnosis of heart related disease. QRS complex plays an important role in Electrocardiogram signal processing since it is the prominent feature of Electrocardiogram signal. One of the important modules in the QRS detection algorithm is filtering. Electrocardiogram signal is processed to filter out unwanted signal through digital filtering. The main objective of this paper is to compare the resource utilization of hardware realization consumed between Direct Form I structure and Direct Form II structure. In this work, Infinite Impulse Response low pass filter to remove high frequency noise is designed with a passband frequency and stopband frequency of 5 and 25 Hz respectively. The designed filter is verified using Matlab Filter Design Analysis tool and realized in hardware using Verilog. Both the results show that the unwanted signals in the raw ECG signal are attenuated through the designed filter. The resource utilization result shows improvement with optimized Direct Form II implementation. The amount of look up tables, flip flop and digital signal processing used with Direct Form II structure shows a reduction to 0.26%, 0.12% and 2.50% respectively compared to 1.17%, 0.20%, 2.92% of utilization with Direct Form I structure.

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27

Kumari, U. Ratna y T. K. Rasagna. "Implementation of Pipelined Data Encryption Standard for Security Enhancement through Verilog". International Journal of Computer Applications and Technology 1, n.º 1 (10 de julio de 2012): 4–8. http://dx.doi.org/10.7753/2012.1002.

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28

Trivedi, Hardik, Rohit Kumar, Ronak Tank, Sundaresan C. y Madhushankara M. "Implementation of USB 3. 0 SuperSpeed Physical Layer using Verilog HDL". International Journal of Computer Applications 95, n.º 24 (18 de junio de 2014): 1–5. http://dx.doi.org/10.5120/16739-6571.

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29

Aswathy Krishnan, Nisha G. R,. "VIP Implementation for Mil-Std Manchester Encoder- Decoder Using System Verilog". International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 04, n.º 07 (20 de julio de 2015): 6010–25. http://dx.doi.org/10.15662/ijareeie.2015.0407027.

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30

Sajjad, Redwan N., Ujwal Radhakrishna y Dimitri A. Antoniadis. "A tunnel FET compact model including non-idealities with verilog implementation". Solid-State Electronics 150 (diciembre de 2018): 16–22. http://dx.doi.org/10.1016/j.sse.2018.09.001.

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31

Kumar, Manish, Priyanka Singh y Shesha Singh. "A VLSI Implementation of Four-Phase Lift Controller Using Verilog HDL". IOP Conference Series: Materials Science and Engineering 225 (agosto de 2017): 012137. http://dx.doi.org/10.1088/1757-899x/225/1/012137.

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32

Yuan, Jun, Quan Yuan Feng y Dan Wang. "Design of High-Precision FIR Filter Based on Verilog HDL". Advanced Materials Research 433-440 (enero de 2012): 5198–202. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.5198.

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This paper presents an optimized FIR filter implementation by using the method of improving coefficient precision at reasonable cost. The comparable results of traditional fix-point implementation and the optimization method show that the high-precision FIR filter design method is universal and easy to implement. Plus the employment of multi-stage pipelining and parallel structure, FIR filter performs higher operating frequency. Let’s take a 32-order lowpass FIR filter as an example, original coefficients are generated on MATLAB, and translated into optimized coefficients according to the optimization method. The functional simulations verify the effective performance, while the synthesis is carried out to analyze the utilization of resources and maximum frequency.

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33

Zhao, Lin Hui y Zhi Yuan Liu. "Vehicle State and Friction Force Estimation Based on FPGA". Applied Mechanics and Materials 336-338 (julio de 2013): 999–1002. http://dx.doi.org/10.4028/www.scientific.net/amm.336-338.999.

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In order to improve the computational performance of the nonlinear observer for vehicle state and friction force estimation, two novel implementation schemes in Verilog Hardware Description Language (HDL) and System on Programmable Chip (SoPC) is proposed based on Field Programmable Gate Array (FPGA). Firstly, the parallelism analysis of the vehicle state and friction force estimation algorithm is provided. Then, the Verilog HDL and SoPC implementation schemes are presented respectively based on the analysis results. Finally, a testing platform is built to evaluate the functionality and the computational performance of the implementation schemes. The experimental results show that the proposed schemes all have high precision and computational efficiency for vehicle state and friction force estimation.

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34

Tanawade, Neeta y Sagun Sudhansu. "FPGA Implementation of Digital Modulation Techniques BPSK and QPSK using HDL Verilog". International Journal of Computer Applications 165, n.º 12 (17 de mayo de 2017): 44–50. http://dx.doi.org/10.5120/ijca2017914106.

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35

Teja, K. Babu Ravi. "Design and Implementation of Neighborhood Processing Operations on FPGA using Verilog HDL". IOSR journal of VLSI and Signal Processing 4, n.º 1 (2014): 75–80. http://dx.doi.org/10.9790/4200-04127580.

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36

VenkataRao, P. y K. R. K. Sastry K.R.K.Sastry. "Implementation of Complex Matrix Inversion using Gauss-Jordan Elimination Method in Verilog". International Journal of Computer Applications 122, n.º 3 (18 de julio de 2015): 6–9. http://dx.doi.org/10.5120/21678-4768.

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37

M. Rane, Sonali, Mrs Trupti Wagh y Dr Mrs P. Malathi. "An Implementation of Double precision Floating point Adder & Subtractor Using Verilog". IOSR Journal of Electrical and Electronics Engineering 9, n.º 4 (2014): 01–05. http://dx.doi.org/10.9790/1676-09430105.

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38

Premalatha, G., J. Mohana, S. Suvitha y J. Manikandan. "Implementation of VLSI Based Efficient Lossless EEG Compression Architecture using Verilog HDL". Journal of Physics: Conference Series 1964, n.º 6 (1 de julio de 2021): 062048. http://dx.doi.org/10.1088/1742-6596/1964/6/062048.

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39

., NARAHARI BHARGAVI y B. NAGA RAJESH . "VLSI IMPLEMENTATION OF HIGH SPEED SINGLE PRECESSION FLOATING POINT UNIT USING VERILOG". International Journal of Engineering Technology and Management Sciences 6, n.º 1 (28 de enero de 2022): 16–23. http://dx.doi.org/10.46647/ijetms.2022.v06i01.003.

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Single-precision floating-point format is a computer number format that is used to represent a wide dynamic range of values. Floating point numbers representation has widespread dominance over fixed point numbers. Since the recent years, researchers are putting a lot of efforts in interfacing complex modules which are used in signal processing with processors for increasing the speed. In this work implementation of a floating point arithmetic unit which can perform addition, subtraction, multiplication, and division functions on 32-bit operands that use the IEEE 754-2008 standard is done using Verilog. The FPU of this work is a single precision IEEE754 compliant integrated unit. Pre-normalization of operands is employed for addition and subtraction, multiplication using bit pair recoding and division using non restoring division. It can handle not only basic floating point operations like addition, subtraction, multiplication and division but can also handle operations like transcendental functions like sine, cosine and tangential function. The logical method for Addition and Subtraction operation is expanded in order to decrease the no. of gates used.

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40

Noorbasha, Fazal, K. Hari Kishore, T. Naveen, A. Sai Anusha, Y. Manisha, K. Revathi y M. Manasa. "Implementation of modified Feistel block cipher for OTP generation using Verilog HDL". International Journal of Engineering & Technology 7, n.º 2.8 (19 de marzo de 2018): 392. http://dx.doi.org/10.14419/ijet.v7i2.8.10678.

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In this paper we modified feistel block cipher to generate OTP (One Time Password) and implement it using Verilog HDL. To perform any online transaction using debit or credit cards, an OTP is sent to the client via SMS for his mobile number registered at the bank, then the client enters this OTP to complete the transaction. This OTP is generated at Bank server and sent to the client mobile operator. Once the OTP is generated it should be protected during the transmission from cyber attacks such as phishing, malware Trojans, etc. before it reaches the client to maintain confidentiality and integrity of information. This algorithm uniquely specifies the steps to encrypt the plain text into cryptographic cipher and to decrypt this cipher text back into original form. The proposed modified method is for improving the security.

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41

Sanivarapu, Rambabu, Mallikarjuna Rao Y., Venkataiah C., Linga Murthy M.K., Laith H. Alzubaidi y Vyeshikha. "Design and Implementation of POSIT Based Adder and Multiplier in Verilog HDL". E3S Web of Conferences 391 (2023): 01184. http://dx.doi.org/10.1051/e3sconf/202339101184.

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Due to recent developments, the POSIT number system, winch has been planned as a successor for numbers that are expressed in IEEE floating-point, which are in the focus of advances in arithmetic. Although this format claims to deliver more precise outcomes with the same bit width as ordinary floating point, the duration of the operation fluctuation during posit field identification poses a hardware design problem. The POSIT-based MAC Unit is created using Verilog HDL in this study, and the designed architecture is evaluated for good operation before being implemented on an FPGA using Xilinx Vivado.

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42

M S, Harish M. S. y Jayadevappa D. "Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog". International Journal of Engineering & Technology 7, n.º 4.36 (9 de diciembre de 2018): 373. http://dx.doi.org/10.14419/ijet.v7i4.36.23809.

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As a part of my ongoing research on implementation of multi core hybrid processor on FPGA, I have developed data flow designs for most popularly used 20 processor instructions. I have made digital design, wrote code in Verilog HDL and simulated all the 20 instructions using Xilinx ISE 14.5. The data flow designs, symbolic representation and simulation results are explained in detail in this technical paper. This is partial implementation of Hybrid Processor & the other sub modules implementation on Xilinx FPGA will be published in my subsequent technical paper.

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43

M S, Harish M. S. y Jayadevappa D. "Design & Simulation Of 64-Bit Hybrid Processor Instruction Set Using Verilog". International Journal of Engineering & Technology 7, n.º 4.36 (9 de diciembre de 2018): 373. http://dx.doi.org/10.14419/ijet.v7i4.36.23810.

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As a part of my ongoing research on implementation of multi core hybrid processor on FPGA, I have developed data flow designs for most popularly used 20 processor instructions. I have made digital design, wrote code in Verilog HDL and simulated all the 20 instructions using Xilinx ISE 14.5. The data flow designs, symbolic representation and simulation results are explained in detail in this technical paper. This is partial implementation of Hybrid Processor & the other sub modules implementation on Xilinx FPGA will be published in my subsequent technical paper.

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44

Shaik, Samdhani y P. Balanagu. "Functional Verification Architecture Implementation for Power Optimized FIR Filter". International Journal of Engineering & Technology 7, n.º 2.20 (18 de abril de 2018): 287. http://dx.doi.org/10.14419/ijet.v7i2.20.14780.

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Digital-filters are having universal for audio applications. So that, great digital-filter execution ought to be taken as an imperative for outline of audio system Applications. The utilization of accuracy with limited in Digital filters for speaking to signals which likewise contrast from that of simple filters as computerized filters utilizing a limited exactness number juggling for registering the filter reaction. Here, FIR-filter has been actualized in Xilinx ISE utilizing VERILOG dialect. VERILOG coding for FIR-filter has been actualized here too waveforms are additionally seen in the reproduction.Viper comprises of less weight as contrasted and multipliers as far as silicon territory and this plays a profitable in FIR structure. This paper has picked multipliers as stall and Wallace and the taken the adders as convey spare and convey skip. In this paper it needs to build up a RTL in the purpose of structures and check the usefulness of structures contrasted and playing out the union utilizing Xilinx synthesizer. The outcomes were thought about regarding region (LUT'S), power, deferral and memory for different fir structures.

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45

Agarwal, Aman, Arjun J. Anil, Rahul Nair y K. Sivasankaran. "ASIC Implementation of DMA Controller". International Journal of Electrical and Electronics Research 4, n.º 1 (31 de marzo de 2016): 1–4. http://dx.doi.org/10.37391/ijeer.040101.

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Direct Memory Access is a method of transferring data between peripherals and memory without using the CPU. It is designed to improve system performance by allowing external devices to directly transfer information from the system memory. We generally use asynchronous type of DMA as they respond directly to input. The DMA controller issues signals to the peripheral device and main memory to execute read and write commands. In this paper DMA controller was designed using Verilog HDL and simulated in Cadence NC Launch. The design was synthesized using low power constraints. Through this design we have decreased the power consumption to 69%.

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46

Qian, Xiang Ping, Wei Ming Qiao, Zhong Zu Zhou, Xi Meng Chen y Lan Jing. "A Digital Regulator for FPGA Implementation". Advanced Materials Research 433-440 (enero de 2012): 4547–54. http://dx.doi.org/10.4028/www.scientific.net/amr.433-440.4547.

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A digital regulator architecture implemented in FPGA is described which is used in the accelerator power supply. To save the delay time, the device is based on combinational circuit and special data format. The multiplier uses the partial products generated by modified Booth algorithm, Carry look-ahead adder and Wallace tree. The regulator is written in Verilog, and is synthesized into FPGA. The synthesis results shows that the proposed regulator can run 200MHZ clock rate in FPGA EP3C25F256 and the whole feedback time is as short as 3 clock periods.

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47

K N, Hemalatha, Aishwarya Kamakodi, A. Soppia, A. Poornima y Sangeetha B G. "Design And Implementation Of 64-Bit Ripple Carry Adder And Ripple Borrow Subtractor Using Reversible Logic Gates". International Journal of Advanced Networking and Applications 13, n.º 06 (2022): 5215–19. http://dx.doi.org/10.35444/ijana.2022.13607.

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Minimal power design is desirable for a range of applications, including the Internet of Things (IoT), quantum computing, and so on. The reversible logic approach is at the foundation of a new technique for designing minimal power digital logic circuits for quantum computing applications. The reversible logic circuit offers a whole new approach to quantum computer processing. Reversible logic gates-based devices will be in high demand for future computer technologies since they require less power. Reversible logic gates were used to design a ripple carry adder (RCA) and a ripple borrow subtractor (RBS), which were simulated in Verilog 2018.3 and coded in Verilog HDL.

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48

Ibrahimy, Muhammad Ibn. "FPGA Implementation of Multiplier for Floating-Point Numbers Based on IEEE 754-2008 Standard". Journal of Communications Technology, Electronics and Computer Science 1 (22 de octubre de 2015): 1. http://dx.doi.org/10.22385/jctecs.v1i0.2.

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This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis etc. Implementation of floating-point multiplication is handy and easy for high level language. However it is a challenging task to implement a floating-point multiplication in hardware level/low level language due to the complexity of algorithm. A top-down approach has been applied for the prototyping of IEEE 754-2008 standard floating-point multiplier module using Verilog Hardware Description Language (HDL). Electronic Design Automation (EDA) tool of Altera Quartus II has been used for floating-point multiplier. The hardware implementation has been done by downloading the Verilog code onto Altera DE2 FPGA development board and found a satisfactory performance.

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49

Azhari, Zul Imran, Samsul Setumin, Emilia Noorsal y Mohd Hanapiah Abdullah. "Digital image enhancement by brightness and contrast manipulation using Verilog hardware description language". International Journal of Electrical and Computer Engineering (IJECE) 13, n.º 2 (1 de abril de 2023): 1346. http://dx.doi.org/10.11591/ijece.v13i2.pp1346-1357.

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A foggy environment may cause digitally captured images to appear blurry, dim, or low in contrast. This will impact computer vision systems that rely on image information. With the need for real-time image information, such as a plate number recognition system, a simple yet effective image enhancement algorithm using a hardware implementation is very much needed to fulfil the need. To improve images that suffer from low exposure and hazy, the hardware implementations are usually based on complex algorithms. Hence, the aim of this paper is to propose a less complex enhancement algorithm for hardware implementation that is able to improve the quality of such images. The proposed method simply combines brightness and contrast manipulation to enhance the image. In order to see the performance of the proposed method, a total of 100 vehicle registration number images were collected, enhanced, and evaluated. The evaluation results were compared to two other enhancement methods quantitatively and qualitatively. Quantitative evaluation is done by evaluating the output image using peak signal-to-noise ratio and mean-square error evaluation metrics, while a survey is done to evaluate the output image qualitatively. Based on the quantitative evaluation results, our proposed method outperforms the other two enhancement methods.

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50

Somashekhar, Vikas Maheshwari y R. P. Singh. "FPGA Implementation of Fault Tolerant Adder using Verilog for High Speed VLSI Architectures". International Journal of Engineering and Advanced Technology 9, n.º 4 (30 de abril de 2020): 549–51. http://dx.doi.org/10.35940/ijeat.d7062.049420.

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The main objective is to detect and reduce the faults in full adder design using self checking and self repairing adder block. The rate of chip failure is directly proportional to chip density. This fault tolerant adder has high speed (Delay is 6.236ns) & implemented on FPGA Spartan 3 using XC3S50 device. The source code is written in verilog. In this design faults are identified and repaired using self checking and self repairing full adder methodologies.

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