Artículos de revistas sobre el tema "VEDIC MULTIPLIERS"
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Eshack, Ansiya y S. Krishnakumar. "Pipelined vedic multiplier with manifold adder complexity levels". International Journal of Electrical and Computer Engineering (IJECE) 10, n.º 3 (1 de junio de 2020): 2951. http://dx.doi.org/10.11591/ijece.v10i3.pp2951-2958.
Texto completoKhubnani, Rashi, Tarunika Sharma y Chitirala Subramanyam. "Applications of Vedic multiplier - A Review". Journal of Physics: Conference Series 2225, n.º 1 (1 de marzo de 2022): 012003. http://dx.doi.org/10.1088/1742-6596/2225/1/012003.
Texto completoRashno, Meysam, Majid Haghparast y Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier". International Journal of Quantum Information 18, n.º 03 (abril de 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.
Texto completoBhairannawar, Satish s., Raja K B, Venugopal K R y L. M. Patnaik. "EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER". INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, n.º 5 (30 de enero de 2014): 3452–63. http://dx.doi.org/10.24297/ijct.v12i5.2915.
Texto completoNandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology". Asian Journal of Electrical Sciences 11, n.º 2 (15 de diciembre de 2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.
Texto completoCVS, Chaitanya, Sundaresan C, P. R. Venkateswaran, Keerthana Prasad y V. Siva Ramakrishna. "Design of High-Speed Multiplier Architecture Based on Vedic Mathematics". International Journal of Engineering & Technology 7, n.º 2.4 (10 de marzo de 2018): 105. http://dx.doi.org/10.14419/ijet.v7i2.4.11228.
Texto completoKuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan y Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques". Journal of Signal Processing 8, n.º 2 (22 de junio de 2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.
Texto completoCVS, Chaitanya, Sundaresan C y P. R Venkateswaran. "ASIC design of low power-delay product carry pre-computation based multiplier". Indonesian Journal of Electrical Engineering and Computer Science 13, n.º 2 (1 de febrero de 2019): 845. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp845-852.
Texto completoGanjikunta, Ganesh Kumar, Sibghatullah I. Khan y M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics". Journal of Low Power Electronics 15, n.º 3 (1 de septiembre de 2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.
Texto completoProf. Parvaneh Basaligheh. "Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device". International Journal of New Practices in Management and Engineering 6, n.º 01 (31 de marzo de 2017): 14–19. http://dx.doi.org/10.17762/ijnpme.v6i01.51.
Texto completoProf. Sharayu Waghmare. "Vedic Multiplier Implementation for High Speed Factorial Computation". International Journal of New Practices in Management and Engineering 1, n.º 04 (31 de diciembre de 2012): 01–06. http://dx.doi.org/10.17762/ijnpme.v1i04.8.
Texto completoC, Pradeepa S., Gowri G. Bennur, Hruthika G, Adithya M y Acharya Vinay Vasudeva. "Design and VLSI Implementation of Vedic Multiplier using 45nm Technology". International Journal for Research in Applied Science and Engineering Technology 11, n.º 5 (31 de mayo de 2023): 964–68. http://dx.doi.org/10.22214/ijraset.2023.51676.
Texto completoJoshi, Shubhangi M. "Modified Vedic Multipliers: A Review". International Journal of Advanced Research in Computer Science and Software Engineering 7, n.º 5 (30 de mayo de 2017): 421–26. http://dx.doi.org/10.23956/ijarcsse/sv7i5/0255.
Texto completoSafoev, Nuriddin y Jun-Cheol Jeon. "Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata". Electronics 9, n.º 6 (23 de junio de 2020): 1036. http://dx.doi.org/10.3390/electronics9061036.
Texto completoParadhasaradhi, Damarla, Bharinala Haridhar, A. V. Sreekanth Reddy, Dudipalli Sri Charan y Atyam Lekhaz. "Implementation of Fast Convolution using Robust Vedic Multiplier of Radix-2". International Journal of Engineering & Technology 7, n.º 2.7 (18 de marzo de 2018): 626. http://dx.doi.org/10.14419/ijet.v7i2.7.10895.
Texto completoEt. al., Srilakshmi Kaza,. "Performance Analysis of Adiabatic Vedic Multipliers". Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, n.º 5 (11 de abril de 2021): 1429–35. http://dx.doi.org/10.17762/turcomat.v12i5.2039.
Texto completoPradhan, Manoranjan y Rutuparna Panda. "Speed Comparison of 16x16 Vedic Multipliers". International Journal of Computer Applications 21, n.º 6 (31 de mayo de 2011): "12"—"19". http://dx.doi.org/10.5120/2516-3417.
Texto completoEshack, Ansiya y S. Krishnakumar. "Reversible logic in pipelined low power vedic multiplier". Indonesian Journal of Electrical Engineering and Computer Science 16, n.º 3 (1 de diciembre de 2019): 1265. http://dx.doi.org/10.11591/ijeecs.v16.i3.pp1265-1272.
Texto completoSharma, Tarunika, Rashi Khubnani y Chitiralla Subramanyam. "Study of mathematics through indian veda’s : A review". Journal of Physics: Conference Series 2332, n.º 1 (1 de septiembre de 2022): 012006. http://dx.doi.org/10.1088/1742-6596/2332/1/012006.
Texto completoGowreesrinivas, K. V., Sabbavarapu Srinivas y Punniakodi Samundiswary. "FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders". Engineering, Technology & Applied Science Research 13, n.º 3 (2 de junio de 2023): 10698–702. http://dx.doi.org/10.48084/etasr.5797.
Texto completoG., Suresh. "Approximate Compressors based Inexact Vedic Dadda Multipliers". HELIX 8, n.º 1 (1 de enero de 2018): 2683–90. http://dx.doi.org/10.29042/2018-2683-2690.
Texto completoHari Kishore, K., Fazal Noorbasha, Katta Sandeep, D. N. V. Bhupesh, SK Khadar Imran y K. Sowmya. "Linear convolution using UT Vedic multiplier". International Journal of Engineering & Technology 7, n.º 2.8 (19 de marzo de 2018): 409. http://dx.doi.org/10.14419/ijet.v7i2.8.10471.
Texto completoDeokate, Rajesh. "A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics". International Journal for Research in Applied Science and Engineering Technology 9, n.º VI (20 de junio de 2021): 1300–1303. http://dx.doi.org/10.22214/ijraset.2021.35242.
Texto completoMukkara, Lakshmi kiran y K. Venkata Ramanaiah. "Neuronal Logic gates Realization using CSD algorithm". International Journal of Reconfigurable and Embedded Systems (IJRES) 8, n.º 2 (1 de julio de 2019): 145. http://dx.doi.org/10.11591/ijres.v8.i2.pp145-150.
Texto completoGaur, F. Nidhi, S. Anu Mehra y T. Pradeep Kumar. "Power and Area Efficient Vedic Multipliers Using Modified CSLA Architectures for DSP". Journal of Advanced Research in Dynamical and Control Systems 11, n.º 10 (31 de octubre de 2019): 44–51. http://dx.doi.org/10.5373/jardcs/v11i10/20193004.
Texto completoMOHANA KANNAN, LOGANATHAN y DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION". DYNA 96, n.º 5 (1 de septiembre de 2021): 505–11. http://dx.doi.org/10.6036/10214.
Texto completoPoornima, Y. y M. Kamalanathan. "Design of Low Power Vedic Multiplier Based Reconfigurable Fir Filter for DSP Applications". International Journal of Advance Research and Innovation 7, n.º 2 (2019): 57–60. http://dx.doi.org/10.51976/ijari.721908.
Texto completoSreelakshmi, G., Kaleem Fatima y B. K. Madhavi. "Efficient Realization of Vinculum Vedic BCD Multipliers for High Speed Applications". Circuits and Systems 09, n.º 06 (2018): 87–99. http://dx.doi.org/10.4236/cs.2018.96009.
Texto completoP. VINAY, MALLIK y HEMACHANDRA G. "Design of 2D-DCT and Quantization Using Dadda and Vedic Multipliers". i-manager's Journal on Digital Signal Processing 4, n.º 3 (2016): 21. http://dx.doi.org/10.26634/jdp.4.3.8144.
Texto completoAnjana, S., C. Pradeep y Philip Samuel. "Synthesize of High Speed Floating-point Multipliers Based on Vedic Mathematics". Procedia Computer Science 46 (2015): 1294–302. http://dx.doi.org/10.1016/j.procs.2015.01.054.
Texto completoSavadi, Anuradha, Raju Yanamshetti y Shewta Biradar. "Design and Implementation of 64 Bit IIR Filters Using Vedic Multipliers". Procedia Computer Science 85 (2016): 790–97. http://dx.doi.org/10.1016/j.procs.2016.05.267.
Texto completoMehra, Anu, Vinay Verma, Rana Majumdar, Nidhi Gaur, Alok Kumar, Chanda Pandey y Ansh Awasthi. "Comparative analysis of different Vedic algorithms for 8 × 8 binary multipliers". International Journal of Industrial and Systems Engineering 33, n.º 2 (2019): 129. http://dx.doi.org/10.1504/ijise.2019.10024258.
Texto completoMehra, Anu, Vinay Verma, Rana Majumdar, Nidhi Gaur, Alok Kumar, Ansh Awasthi y Chanda Pandey. "Comparative analysis of different Vedic algorithms for 8 × 8 binary multipliers". International Journal of Industrial and Systems Engineering 33, n.º 2 (2019): 129. http://dx.doi.org/10.1504/ijise.2019.102466.
Texto completoS., Nagaraj. "Design and Analysis of 8-bit Array, Carry Save Array, Braun, Wallace Tree and Vedic Multipliers". International Journal of Psychosocial Rehabilitation 24, n.º 3 (30 de marzo de 2020): 2687–97. http://dx.doi.org/10.37200/ijpr/v24i3/pr2020305.
Texto completoBhargavi, Sandugari. "Design and Implementation of Area Efficient BIST Based Vedic and Wallace Tree Multipliers on FPGA". International Journal for Research in Applied Science and Engineering Technology 7, n.º 4 (30 de abril de 2019): 3650–55. http://dx.doi.org/10.22214/ijraset.2019.4612.
Texto completoFatima, Nashrah, Taha Tanveer y Brahmi Shrman. "Implementation for Minimization of Computation Time of Partial Products for Designing Multipliers using Tabulated Vedic Mathematics". International Journal of Computer Applications 128, n.º 10 (15 de octubre de 2015): 1–5. http://dx.doi.org/10.5120/ijca2015906638.
Texto completoNaveen, R. "Design and Analysis of Low Power Full Adders and 4*4 Vedic Multipliers Based on Urdhva Triyagbhyam". Asian Journal of Research in Social Sciences and Humanities 6, n.º 7 (2016): 950. http://dx.doi.org/10.5958/2249-7315.2016.00479.2.
Texto completoSM, Vijaya y Suresh K. "An Efficient Design Approach of ROI Based DWT Using Vedic and Wallace Tree Multiplier on FPGA Platform". International Journal of Electrical and Computer Engineering (IJECE) 9, n.º 4 (1 de agosto de 2019): 2433. http://dx.doi.org/10.11591/ijece.v9i4.pp2433-2442.
Texto completoSaraswathi, N., Lokesh Modi y Aatish Nair. "Complex Number Vedic Multiplier and its Implementation in a Filter". International Journal of Engineering & Technology 7, n.º 2.24 (25 de abril de 2018): 336. http://dx.doi.org/10.14419/ijet.v7i2.24.12078.
Texto completoJhamb, Mansi y Manoj Kumar. "Optimized vedic multiplier using low power 13T hybrid full adder". Journal of Information and Optimization Sciences 44, n.º 4 (2023): 675–87. http://dx.doi.org/10.47974/jios-1222.
Texto completoSharma, Vaishali. "Design, Implementation & Performance of Vedic Multiplier Based on Look Ahead Carry Adder for Different Bit Lengths". International Journal for Research in Applied Science and Engineering Technology 10, n.º 1 (31 de enero de 2022): 24–30. http://dx.doi.org/10.22214/ijraset.2022.39759.
Texto completoKunchigik, Vaijyanath, Linganagouda Kulkarni y Subhash Kulkarni. "Pipelined Vedic-Array Multiplier Architecture". International Journal of Image, Graphics and Signal Processing 6, n.º 6 (8 de mayo de 2014): 58–64. http://dx.doi.org/10.5815/ijigsp.2014.06.08.
Texto completoKivi Sona, M. y V. Somasundaram. "Vedic Multiplier Implementation in VLSI". Materials Today: Proceedings 24 (2020): 2219–30. http://dx.doi.org/10.1016/j.matpr.2020.03.748.
Texto completoPrabhu, E., H. Mangalam y P. R. Gokul. "A Delay Efficient Vedic Multiplier". Proceedings of the National Academy of Sciences, India Section A: Physical Sciences 89, n.º 2 (9 de febrero de 2018): 257–68. http://dx.doi.org/10.1007/s40010-017-0464-4.
Texto completoKumar, M. Siva, Sanath Kumar Tulasi, N. Srinivasulu, Vijaya Lakshmi Bandi y K. Hari Kishore. "Bit wise and delay of vedic multiplier". International Journal of Engineering & Technology 7, n.º 1.5 (31 de diciembre de 2017): 26. http://dx.doi.org/10.14419/ijet.v7i1.5.9117.
Texto completoYadav, Jatin, Anupam Kumar, Shaik Shareef, Sandeep Bansal y Navjot Rathour. "Comparative Analysis of Vedic Multiplier using Various Adder Architectures". Journal of Physics: Conference Series 2327, n.º 1 (1 de agosto de 2022): 012022. http://dx.doi.org/10.1088/1742-6596/2327/1/012022.
Texto completoBhavani, M., M. Siva Kumar y K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA". International Journal of Electrical and Computer Engineering (IJECE) 6, n.º 3 (1 de junio de 2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.9457.
Texto completoBhavani, M., M. Siva Kumar y K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA". International Journal of Electrical and Computer Engineering (IJECE) 6, n.º 3 (1 de junio de 2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.pp1205-1212.
Texto completoPrasad, M. V. Tejendra. "Development and Realization of a 4x4 Vedic Multiplier Utilizing Cadence Platform". Journal of VLSI Design and Signal Processing 9, n.º 2 (4 de agosto de 2023): 39–51. http://dx.doi.org/10.46610/jovdsp.2023.v09i02.004.
Texto completoManikrao, Kaustubh y Mahesh Shrikant. "Analysis of Array Multiplier and Vedic Multiplier using Xilinx". Communications on Applied Electronics 5, n.º 1 (24 de mayo de 2016): 13–16. http://dx.doi.org/10.5120/cae2016652140.
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