Artículos de revistas sobre el tema "VEDIC MULTIPLIER"
Crea una cita precisa en los estilos APA, MLA, Chicago, Harvard y otros
Consulte los 50 mejores artículos de revistas para su investigación sobre el tema "VEDIC MULTIPLIER".
Junto a cada fuente en la lista de referencias hay un botón "Agregar a la bibliografía". Pulsa este botón, y generaremos automáticamente la referencia bibliográfica para la obra elegida en el estilo de cita que necesites: APA, MLA, Harvard, Vancouver, Chicago, etc.
También puede descargar el texto completo de la publicación académica en formato pdf y leer en línea su resumen siempre que esté disponible en los metadatos.
Explore artículos de revistas sobre una amplia variedad de disciplinas y organice su bibliografía correctamente.
Eshack, Ansiya y S. Krishnakumar. "Pipelined vedic multiplier with manifold adder complexity levels". International Journal of Electrical and Computer Engineering (IJECE) 10, n.º 3 (1 de junio de 2020): 2951. http://dx.doi.org/10.11591/ijece.v10i3.pp2951-2958.
Texto completoKhubnani, Rashi, Tarunika Sharma y Chitirala Subramanyam. "Applications of Vedic multiplier - A Review". Journal of Physics: Conference Series 2225, n.º 1 (1 de marzo de 2022): 012003. http://dx.doi.org/10.1088/1742-6596/2225/1/012003.
Texto completoRashno, Meysam, Majid Haghparast y Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier". International Journal of Quantum Information 18, n.º 03 (abril de 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.
Texto completoKuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan y Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques". Journal of Signal Processing 8, n.º 2 (22 de junio de 2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.
Texto completoGanjikunta, Ganesh Kumar, Sibghatullah I. Khan y M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics". Journal of Low Power Electronics 15, n.º 3 (1 de septiembre de 2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.
Texto completoSafoev, Nuriddin y Jun-Cheol Jeon. "Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata". Electronics 9, n.º 6 (23 de junio de 2020): 1036. http://dx.doi.org/10.3390/electronics9061036.
Texto completoCVS, Chaitanya, Sundaresan C, P. R. Venkateswaran, Keerthana Prasad y V. Siva Ramakrishna. "Design of High-Speed Multiplier Architecture Based on Vedic Mathematics". International Journal of Engineering & Technology 7, n.º 2.4 (10 de marzo de 2018): 105. http://dx.doi.org/10.14419/ijet.v7i2.4.11228.
Texto completoC, Pradeepa S., Gowri G. Bennur, Hruthika G, Adithya M y Acharya Vinay Vasudeva. "Design and VLSI Implementation of Vedic Multiplier using 45nm Technology". International Journal for Research in Applied Science and Engineering Technology 11, n.º 5 (31 de mayo de 2023): 964–68. http://dx.doi.org/10.22214/ijraset.2023.51676.
Texto completoBhairannawar, Satish s., Raja K B, Venugopal K R y L. M. Patnaik. "EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER". INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, n.º 5 (30 de enero de 2014): 3452–63. http://dx.doi.org/10.24297/ijct.v12i5.2915.
Texto completoNandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology". Asian Journal of Electrical Sciences 11, n.º 2 (15 de diciembre de 2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.
Texto completoSaraswathi, N., Lokesh Modi y Aatish Nair. "Complex Number Vedic Multiplier and its Implementation in a Filter". International Journal of Engineering & Technology 7, n.º 2.24 (25 de abril de 2018): 336. http://dx.doi.org/10.14419/ijet.v7i2.24.12078.
Texto completoProf. Sharayu Waghmare. "Vedic Multiplier Implementation for High Speed Factorial Computation". International Journal of New Practices in Management and Engineering 1, n.º 04 (31 de diciembre de 2012): 01–06. http://dx.doi.org/10.17762/ijnpme.v1i04.8.
Texto completoSM, Vijaya y Suresh K. "An Efficient Design Approach of ROI Based DWT Using Vedic and Wallace Tree Multiplier on FPGA Platform". International Journal of Electrical and Computer Engineering (IJECE) 9, n.º 4 (1 de agosto de 2019): 2433. http://dx.doi.org/10.11591/ijece.v9i4.pp2433-2442.
Texto completoProf. Parvaneh Basaligheh. "Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device". International Journal of New Practices in Management and Engineering 6, n.º 01 (31 de marzo de 2017): 14–19. http://dx.doi.org/10.17762/ijnpme.v6i01.51.
Texto completoJhamb, Mansi y Manoj Kumar. "Optimized vedic multiplier using low power 13T hybrid full adder". Journal of Information and Optimization Sciences 44, n.º 4 (2023): 675–87. http://dx.doi.org/10.47974/jios-1222.
Texto completoCVS, Chaitanya, Sundaresan C y P. R Venkateswaran. "ASIC design of low power-delay product carry pre-computation based multiplier". Indonesian Journal of Electrical Engineering and Computer Science 13, n.º 2 (1 de febrero de 2019): 845. http://dx.doi.org/10.11591/ijeecs.v13.i2.pp845-852.
Texto completoGowreesrinivas, K. V., Sabbavarapu Srinivas y Punniakodi Samundiswary. "FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders". Engineering, Technology & Applied Science Research 13, n.º 3 (2 de junio de 2023): 10698–702. http://dx.doi.org/10.48084/etasr.5797.
Texto completoParadhasaradhi, Damarla, Bharinala Haridhar, A. V. Sreekanth Reddy, Dudipalli Sri Charan y Atyam Lekhaz. "Implementation of Fast Convolution using Robust Vedic Multiplier of Radix-2". International Journal of Engineering & Technology 7, n.º 2.7 (18 de marzo de 2018): 626. http://dx.doi.org/10.14419/ijet.v7i2.7.10895.
Texto completoSharma, Vaishali. "Design, Implementation & Performance of Vedic Multiplier Based on Look Ahead Carry Adder for Different Bit Lengths". International Journal for Research in Applied Science and Engineering Technology 10, n.º 1 (31 de enero de 2022): 24–30. http://dx.doi.org/10.22214/ijraset.2022.39759.
Texto completoKunchigik, Vaijyanath, Linganagouda Kulkarni y Subhash Kulkarni. "Pipelined Vedic-Array Multiplier Architecture". International Journal of Image, Graphics and Signal Processing 6, n.º 6 (8 de mayo de 2014): 58–64. http://dx.doi.org/10.5815/ijigsp.2014.06.08.
Texto completoKivi Sona, M. y V. Somasundaram. "Vedic Multiplier Implementation in VLSI". Materials Today: Proceedings 24 (2020): 2219–30. http://dx.doi.org/10.1016/j.matpr.2020.03.748.
Texto completoPrabhu, E., H. Mangalam y P. R. Gokul. "A Delay Efficient Vedic Multiplier". Proceedings of the National Academy of Sciences, India Section A: Physical Sciences 89, n.º 2 (9 de febrero de 2018): 257–68. http://dx.doi.org/10.1007/s40010-017-0464-4.
Texto completoKumar, M. Siva, Sanath Kumar Tulasi, N. Srinivasulu, Vijaya Lakshmi Bandi y K. Hari Kishore. "Bit wise and delay of vedic multiplier". International Journal of Engineering & Technology 7, n.º 1.5 (31 de diciembre de 2017): 26. http://dx.doi.org/10.14419/ijet.v7i1.5.9117.
Texto completoManikrao, Kaustubh y Mahesh Shrikant. "Analysis of Array Multiplier and Vedic Multiplier using Xilinx". Communications on Applied Electronics 5, n.º 1 (24 de mayo de 2016): 13–16. http://dx.doi.org/10.5120/cae2016652140.
Texto completoEshack, Ansiya y S. Krishnakumar. "Reversible logic in pipelined low power vedic multiplier". Indonesian Journal of Electrical Engineering and Computer Science 16, n.º 3 (1 de diciembre de 2019): 1265. http://dx.doi.org/10.11591/ijeecs.v16.i3.pp1265-1272.
Texto completoYadav, Jatin, Anupam Kumar, Shaik Shareef, Sandeep Bansal y Navjot Rathour. "Comparative Analysis of Vedic Multiplier using Various Adder Architectures". Journal of Physics: Conference Series 2327, n.º 1 (1 de agosto de 2022): 012022. http://dx.doi.org/10.1088/1742-6596/2327/1/012022.
Texto completoBhavani, M., M. Siva Kumar y K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA". International Journal of Electrical and Computer Engineering (IJECE) 6, n.º 3 (1 de junio de 2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.9457.
Texto completoBhavani, M., M. Siva Kumar y K. Srinivas Rao. "Delay Comparison for 16x16 Vedic Multiplier Using RCA and CLA". International Journal of Electrical and Computer Engineering (IJECE) 6, n.º 3 (1 de junio de 2016): 1205. http://dx.doi.org/10.11591/ijece.v6i3.pp1205-1212.
Texto completoPrasad, M. V. Tejendra. "Development and Realization of a 4x4 Vedic Multiplier Utilizing Cadence Platform". Journal of VLSI Design and Signal Processing 9, n.º 2 (4 de agosto de 2023): 39–51. http://dx.doi.org/10.46610/jovdsp.2023.v09i02.004.
Texto completo., Uttara Bhatt. "HIGH SPEED MULTIPLIER USING VEDIC MATHEMATICS". International Journal of Research in Engineering and Technology 03, n.º 01 (25 de enero de 2014): 548–52. http://dx.doi.org/10.15623/ijret.2014.0301092.
Texto completoHari Kishore, K., Fazal Noorbasha, Katta Sandeep, D. N. V. Bhupesh, SK Khadar Imran y K. Sowmya. "Linear convolution using UT Vedic multiplier". International Journal of Engineering & Technology 7, n.º 2.8 (19 de marzo de 2018): 409. http://dx.doi.org/10.14419/ijet.v7i2.8.10471.
Texto completoRamalakshmanna, Y., V. Yaswanth Varma, Phani Sai Kumar y T. Nalini Prasad. "Modified Vedic Multiplier Using CSLA Adders". Journal of Computational and Theoretical Nanoscience 16, n.º 4 (1 de abril de 2019): 1255–69. http://dx.doi.org/10.1166/jctn.2019.8028.
Texto completoSharma, Nitesh Kumar, Deepesh Kumar Gautam y M. R. Khan. "Vedic Mathematics Implementation in Multiplier Units". Journal of Computer and Mathematical Sciences 10, n.º 5 (30 de mayo de 2019): 997–1003. http://dx.doi.org/10.29055/jcms/1083.
Texto completoNivasA, Sree y Kayalvizhi N. "Implementation of Power Efficient Vedic Multiplier". International Journal of Computer Applications 43, n.º 16 (30 de abril de 2012): 21–24. http://dx.doi.org/10.5120/6188-8673.
Texto completoVikas, Om, Deepak Gupta, Aneesh Bhasin y Sonu Arora. "Vedic Multiplier with Fast Carry Optimization". IETE Journal of Research 51, n.º 4 (julio de 2005): 327–31. http://dx.doi.org/10.1080/03772063.2005.11416411.
Texto completoAriafar, Zahra y Mohammad Mosleh. "Effective Designs of Reversible Vedic Multiplier". International Journal of Theoretical Physics 58, n.º 8 (24 de mayo de 2019): 2556–74. http://dx.doi.org/10.1007/s10773-019-04145-0.
Texto completoEt. al., Srilakshmi Kaza,. "Performance Analysis of Adiabatic Vedic Multipliers". Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, n.º 5 (11 de abril de 2021): 1429–35. http://dx.doi.org/10.17762/turcomat.v12i5.2039.
Texto completoSharma, Sandesh y Vangmayee Sharda. "Design and Analysis of 8-bit Vedic Multiplier in 90nm Technology using GDI Technique". International Journal of Engineering & Technology 7, n.º 3.12 (20 de julio de 2018): 759. http://dx.doi.org/10.14419/ijet.v7i3.12.16496.
Texto completoKanda, Guard y Kwangki Ryoo. "Vedic Multiplier-based International Data Encryption Algorithm Crypto-Core for Efficient Hardware Multiphase Encryption Design". Webology 19, n.º 1 (20 de enero de 2022): 4581–96. http://dx.doi.org/10.14704/web/v19i1/web19304.
Texto completoDeokate, Rajesh. "A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics". International Journal for Research in Applied Science and Engineering Technology 9, n.º VI (20 de junio de 2021): 1300–1303. http://dx.doi.org/10.22214/ijraset.2021.35242.
Texto completoKunchigi, Vaijyanath, Linganagouda Kulkarni y Subhash Kulkarni. "Simulation of Vedic Multiplier in DCT Applications". International Journal of Computer Applications 63, n.º 16 (15 de febrero de 2013): 27–32. http://dx.doi.org/10.5120/10552-5744.
Texto completoM C, Pradeep y Dr Ramesh S. "Optimized high performance multiplier using Vedic mathematics". IOSR journal of VLSI and Signal Processing 4, n.º 5 (2014): 06–11. http://dx.doi.org/10.9790/4200-04510611.
Texto completoNittala, Vijay Bhaskar, Anisha Bomma y M. Ramana Reddy. "Energy Efficient Approximate 8-bit Vedic Multiplier". International Journal for Research in Applied Science and Engineering Technology 10, n.º 9 (30 de septiembre de 2022): 1453–65. http://dx.doi.org/10.22214/ijraset.2022.46861.
Texto completoRashno, Meysam, Majid Haghparast y Mohammad Mosleh. "Designing of Parity Preserving Reversible Vedic Multiplier". International Journal of Theoretical Physics 60, n.º 8 (13 de julio de 2021): 3024–40. http://dx.doi.org/10.1007/s10773-021-04903-z.
Texto completoSuryavanshi, Ravindra y Sweta Khare. "An Efficient High-Performance Vedic Multiplier: Review". INTERNATIONAL JOURNAL OF ADVANCED ENGINEERING AND MANAGEMENT 2, n.º 3 (1 de marzo de 2017): 60. http://dx.doi.org/10.24999/ijoaem/02030017.
Texto completoNarendra, K. y Sagara Pandu. "Low Power Area-Efficient Adiabatic Vedic Multiplier". International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 03, n.º 08 (20 de agosto de 2014): 11027–32. http://dx.doi.org/10.15662/ijareeie.2014.0308018.
Texto completoSahu, Satya Ranjan, Bandan Kumar Bhoi y Manoranjan Pradhan. "Fast signed multiplier using Vedic Nikhilam algorithm". IET Circuits, Devices & Systems 14, n.º 8 (1 de noviembre de 2020): 1160–66. http://dx.doi.org/10.1049/iet-cds.2019.0537.
Texto completoVadiraj, G., K. Shivanand, B. Sampat y G. Subramanya Nayak. "Implementation of High Speed Vedic Multiplier Using Vertical and Crosswise Algorithm". International Journal of Reconfigurable and Embedded Systems (IJRES) 6, n.º 1 (28 de mayo de 2018): 36. http://dx.doi.org/10.11591/ijres.v6.i1.pp36-40.
Texto completoKumar V G, Kiran y Shantharama Rai C,. "Low Power High Speed Arithmetic Circuits". International Journal of Recent Technology and Engineering (IJRTE) 8, n.º 2 (30 de julio de 2019): 807–13. http://dx.doi.org/10.35940/ijrte.a1064.078219.
Texto completoMOHANA KANNAN, LOGANATHAN y DHANASKODI DEEPA. "LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION". DYNA 96, n.º 5 (1 de septiembre de 2021): 505–11. http://dx.doi.org/10.6036/10214.
Texto completo