Literatura académica sobre el tema "VEDIC MULTIPLIER"
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Artículos de revistas sobre el tema "VEDIC MULTIPLIER"
Eshack, Ansiya y S. Krishnakumar. "Pipelined vedic multiplier with manifold adder complexity levels". International Journal of Electrical and Computer Engineering (IJECE) 10, n.º 3 (1 de junio de 2020): 2951. http://dx.doi.org/10.11591/ijece.v10i3.pp2951-2958.
Texto completoKhubnani, Rashi, Tarunika Sharma y Chitirala Subramanyam. "Applications of Vedic multiplier - A Review". Journal of Physics: Conference Series 2225, n.º 1 (1 de marzo de 2022): 012003. http://dx.doi.org/10.1088/1742-6596/2225/1/012003.
Texto completoRashno, Meysam, Majid Haghparast y Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier". International Journal of Quantum Information 18, n.º 03 (abril de 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.
Texto completoKuruvilla, Siya Susan, Stephani Sunil, Abisha Susan Alichan y Abraham K. Thomas. "Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques". Journal of Signal Processing 8, n.º 2 (22 de junio de 2022): 1–5. http://dx.doi.org/10.46610/josp.2022.v08i02.001.
Texto completoGanjikunta, Ganesh Kumar, Sibghatullah I. Khan y M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics". Journal of Low Power Electronics 15, n.º 3 (1 de septiembre de 2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.
Texto completoSafoev, Nuriddin y Jun-Cheol Jeon. "Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata". Electronics 9, n.º 6 (23 de junio de 2020): 1036. http://dx.doi.org/10.3390/electronics9061036.
Texto completoCVS, Chaitanya, Sundaresan C, P. R. Venkateswaran, Keerthana Prasad y V. Siva Ramakrishna. "Design of High-Speed Multiplier Architecture Based on Vedic Mathematics". International Journal of Engineering & Technology 7, n.º 2.4 (10 de marzo de 2018): 105. http://dx.doi.org/10.14419/ijet.v7i2.4.11228.
Texto completoC, Pradeepa S., Gowri G. Bennur, Hruthika G, Adithya M y Acharya Vinay Vasudeva. "Design and VLSI Implementation of Vedic Multiplier using 45nm Technology". International Journal for Research in Applied Science and Engineering Technology 11, n.º 5 (31 de mayo de 2023): 964–68. http://dx.doi.org/10.22214/ijraset.2023.51676.
Texto completoBhairannawar, Satish s., Raja K B, Venugopal K R y L. M. Patnaik. "EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER". INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 12, n.º 5 (30 de enero de 2014): 3452–63. http://dx.doi.org/10.24297/ijct.v12i5.2915.
Texto completoNandha Kumar, P. "Design of Accuracy Based Fixed-Width Booth Multipliers Using Data Scaling Technology". Asian Journal of Electrical Sciences 11, n.º 2 (15 de diciembre de 2022): 24–30. http://dx.doi.org/10.51983/ajes-2022.11.2.3524.
Texto completoTesis sobre el tema "VEDIC MULTIPLIER"
ANTONY, SAJI M. "DESIGN OF ENERGY EFFICIENT TRANSCEIVER BLOCKS FOR WIRELESS SENSOR NODES". Thesis, DELHI TECHNOLOGICAL UNIVERSITY, 2020. http://dspace.dtu.ac.in:8080/jspui/handle/repository/18771.
Texto completoZanchi, Chiara. "Multiple preverbs in ancient Indo-European languages: a comparative study on Vedic, Homeric Greek, Old Church Slavic and Old Irish". Doctoral thesis, Università degli studi di Bergamo, 2018. http://hdl.handle.net/10446/104992.
Texto completoZANCHI, CHIARA. "Multiple preverbs in ancient Indo-European languages: a comparative study on Vedic, Homeric Greek, Old Church Slavic and Old Irish". Doctoral thesis, Università degli studi di Pavia, 2018. https://hdl.handle.net/11571/1466705.
Texto completoJiang, CunHao y 蔣存皓. "An Efficient Vedic Multiplier Design". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/65n6nm.
Texto completo國立臺北科技大學
電子工程系研究所
105
Multiplier is one of core operations of the digital signal processing and microprocessor. the multiplier in the digital circuit needs to increase the speed, decrease the area and consume less memory. So an efficient multiplier is very important in nowadays. This paper is about designing traditional Vedic multiplier through the Urdhva-Tiryagbhyam sutra. Changing the adder from the traditional Vedic multiplier which designed with the sutra, it can become two kinds of efficient Vedic multipliers. After designing 4-bit, 8-bit, 16-bit, 32-bit traditional Vedic multiplier and two kinds of efficient Vedic multipliers, their time delay and areas are analyzed through the Quartus II. According to the results of the experiment, time delay of the original efficient Vedic multiplier decreases 5.88% but the area increases 37.298%. Besides, time delay of the resolved efficient Vedic multiplier decreases 7.4% but the area increases 21.6%. If the multiplier needs to be faster on work afterwards, 4-bit and 16-bit original efficient Vedic multiplier and 8-bit, 32-bit and 64-bit resolved efficient Vedic multiplier are suggested. If the multiplier needs to be smaller, traditional Vedic multiplier is suggested. If both delay time and chip area cost are considered comprehensively, 8-bit or 64-bit resolved efficient Vedic multiplier are suggested.
RUHELA, DIKSHA. "DESIGN AND IMPLEMENTATION OF EFFICIENT REVERSIBLE MULTIPLIER USING VEDIC MATHEMATICS TOOL". Thesis, 2016. http://dspace.dtu.ac.in:8080/jspui/handle/repository/14759.
Texto completoKUMAR, SHIVAM. "DESIGN AND IMPLEMENTATION OF EFFICIENT MATRIX MULTIPLICATION USING VARIOUS ARCHITECTURE". Thesis, 2023. http://dspace.dtu.ac.in:8080/jspui/handle/repository/19896.
Texto completoLibros sobre el tema "VEDIC MULTIPLIER"
Design of a High Speed Multiplier (Ancient Vedic Mathematics Approach) . Innovative Research Publications, 2013.
Buscar texto completoGeslani, Marko. Rites of the God-King. Oxford University Press, 2018. http://dx.doi.org/10.1093/oso/9780190862886.001.0001.
Texto completoCapítulos de libros sobre el tema "VEDIC MULTIPLIER"
Sudhamsu Preetham, J. V. R., Perli Nethra, D. Chandrasekhar, Mathangi Akhila, N. Arun Vignesh y Asisa Kumar Panigrahy. "Vedic Multiplier for High-Speed Applications". En Communication, Software and Networks, 349–56. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-4990-6_31.
Texto completoPavan Kumar, N. y K. Shashi Raj. "Delay Analysis of Hybrid Vedic Multiplier". En Advances in Intelligent Systems and Computing, 91–103. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7330-6_8.
Texto completoUdaya Kumar, N., K. Bala Sindhuri, U. Subbalakshmi y P. Kiranmayi. "Performance Evaluation of Vedic Multiplier Using Multiplexer-Based Adders". En Lecture Notes in Electrical Engineering, 349–56. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-1906-8_36.
Texto completoLachireddy, Dhanunjay y S. R. Ramesh. "Power and Delay Efficient ALU Using Vedic Multiplier". En Lecture Notes in Electrical Engineering, 703–11. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-5558-9_61.
Texto completoKumari, Sabita y Kanchan Sharma. "Implementation of Nobel Vedic Multiplier Using Arithmetic Adder". En Data Intelligence and Cognitive Informatics, 209–16. Singapore: Springer Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-6460-1_15.
Texto completoAwade, Anirudh, Prachi Jain, S. Hemavathy y V. S. Kanchana Bhaaskaran. "Design of Vedic Multiplier Using Reversible Logic Gates". En Lecture Notes in Electrical Engineering, 435–48. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-9019-1_38.
Texto completoSrimani, Supriyo, Diptendu Kumar Kundu, Saradindu Panda y B. Maji. "Implementation of High Performance Vedic Multiplier and Design of DSP Operations Using Vedic Sutra". En Computational Advancement in Communication Circuits and Systems, 443–49. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2274-3_49.
Texto completoThakare, Laxman P., A. Y. Deshmukh y Gopichand D. Khandale. "VHDL Implementation of Complex Number Multiplier Using Vedic Mathematics". En Proceedings of International Conference on Soft Computing Techniques and Engineering Application, 403–10. New Delhi: Springer India, 2013. http://dx.doi.org/10.1007/978-81-322-1695-7_46.
Texto completoKhan, Angshuman y Rupayan Das. "Novel Approach of Multiplier Design Using Ancient Vedic Mathematics". En Advances in Intelligent Systems and Computing, 265–72. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2247-7_28.
Texto completoGiridaran, S., Prithvik Adithya Ravindran, G. Duruvan Raj y M. Janarthanan. "Design of Low Power Vedic Multiplier Using Adiabatic Techniques". En Cognitive Informatics and Soft Computing, 403–15. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-8763-1_33.
Texto completoActas de conferencias sobre el tema "VEDIC MULTIPLIER"
Kahar, Dravik KishorBhai y Harsh Mehta. "High speed vedic multiplier used vedic mathematics". En 2017 International Conference on Intelligent Computing and Control Systems (ICICCS). IEEE, 2017. http://dx.doi.org/10.1109/iccons.2017.8250742.
Texto completoG, Shanthi K., Sandhiya G, Abinaya K, Akula Sangeetha, Aruna T y Aswini R. "Performance Analysis of Vedic Multiplier and Modified Vedic Multiplier in Direct Digital Synthesizer". En 2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC). IEEE, 2022. http://dx.doi.org/10.1109/icesc54411.2022.9885340.
Texto completoN., Noorja y Sujithamol S. "Convolution Using Modified Vedic Multiplier". En Proceedings of the Advances in Technology, Engineering and Computing A Multinational Colloquium - 2017. Singapore: Research Publishing Services, 2017. http://dx.doi.org/10.3850/978-981-11-0744-3_c66.
Texto completoKodali, Ravi Kishore, C. Sivakumar, Vishal Jain y Lakshmi Boppana. "Low-power modified Vedic multiplier". En 2015 International Conference on Control Communication & Computing India (ICCC). IEEE, 2015. http://dx.doi.org/10.1109/iccc.2015.7432939.
Texto completoPranav, K. y P. Pramod. "Pipelined convolution using Vedic multiplier". En 2015 IEEE Recent Advances in Intelligent Computational Systems (RAICS). IEEE, 2015. http://dx.doi.org/10.1109/raics.2015.7488384.
Texto completoRam, G. Challa, Y. Rama Lakshmanna, D. Sudha Rani y K. Bala Sindhuri. "Area efficient modified vedic multiplier". En 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT). IEEE, 2016. http://dx.doi.org/10.1109/iccpct.2016.7530294.
Texto completoPatel, Chiranjit R., Vivek Urankar, Vivek B. A y V. Keshav Bharadwaj. "Vedic Multiplier in 45nm Technology". En 2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC). IEEE, 2020. http://dx.doi.org/10.1109/iccmc48092.2020.iccmc-0004.
Texto completoHarish Babu N, Satish Reddy N, Bhumarapu Devendra y Jayakrishanan P. "Pipelined architecture for vedic multiplier". En 2014 International Conference on Advances in Electrical Engineering (ICAEE). IEEE, 2014. http://dx.doi.org/10.1109/icaee.2014.6838437.
Texto completoPichhode, Khushboo, Mukesh D. Patil, Divya Shah y B. Chaurasiya Rohit. "FPGA implementation of efficient vedic multiplier". En 2015 International Conference on Information Processing (ICIP). IEEE, 2015. http://dx.doi.org/10.1109/infop.2015.7489448.
Texto completoBansal, Malti y Jasmeet Singh. "Comparative Analysis of 4-bit CMOS Vedic Multiplier and GDI Vedic Multiplier using 18nm FinFET Technology". En 2020 International Conference on Smart Electronics and Communication (ICOSEC). IEEE, 2020. http://dx.doi.org/10.1109/icosec49089.2020.9215317.
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