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SAUTTO, MARCO. "ANALOG FRONT-END CIRCUITS FOR HIGHLY INTEGRATED ULTRASOUND IMAGING SYSTEMS." Doctoral thesis, Università degli studi di Pavia, 2017. http://hdl.handle.net/11571/1203280.
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Ultrasound imaging is a well-established medical diagnostic technique. Compared with other imaging modalities, such as for example X-ray, ultrasound is harmless to the patient and less expensive while providing real-time imaging capability with adequate resolution for most applications. Piezoelectric materials have dominated the ultrasound transducers technology for a long time but, thanks to the intense research activity in recent years, capacitive micromachined ultrasonic transducers (CMUT) are emerging as a competitive alternative for next generation imaging systems. The objective of the thesis is to analyze the ultrasound system, when a CMUT is used instead of a piezoelectric transducer, to identify and design the best integrated solution to optimize the front-end performance. After giving an overview of the ultrasound system and the Capacitive Micromachined Ultrasonic Transducer (CMUT) in Chapter 1, Chapter 2 presents a thorough comparison between RX amplifier alternatives. The impact on the pulse-echo frequency response and SNR is assessed. The study demonstrates that a capacitive-feedback stage provides a remarkable improvement in the noise-power performance compared to the very popular resistive-feedback amplifier, at the expense of a low-frequency shift of the pulse-echo response, making it suitable for integration of dense CMUT arrays for low and mid-frequency ultrasound imaging applications. Then, Chapter 3 proposes the design of a CMUT front-end circuits comprising a TX driver, T/R switch and RX amplifier. Realized in BCD8-SOI technology from STMicroelectronics, the TX delivers up to 100V pulses, while the RX shows 70dB dynamic range with very low noise at 1mW only power dissipation. Measurement results and imaging experiments are presented and discussed. In Chapter 4, the non-linear behavior of the CMUT is discussed and possible solution proposed. Experimental results demonstrate a significant reduction of the second-harmonic distortion, estimated to be lower than -30 dB, resulting in good linearization for typical nonlinear imaging operation. In addition, Chapter 5 shows a novel amplifier architecture exploiting the regeneration feature of the cross-coupled pair. It will be used as Programmable Gain Amplifier (PGA) in the ultrasound chain. A test-chip in 0.18 μm CMOS provides 15dB to 66dB gain over 50MHz bandwidth. With state-of-the-art noise and linearity performance, a record GBW up to 100GHz is demonstrated with only 420 μW power dissipation.
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Behnamfar, Parisa. "On the design of high-voltage analog front-end circuits for capacitive micromachined ultrasonic transducers (CMUT)." Thesis, University of British Columbia, 2014. http://hdl.handle.net/2429/50469.
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In ultrasound imaging, capacitive micromachined ultrasonic transducer (CMUT) technology has become a promising alternative to conventional piezoelectric- based technology. This work focuses on various aspects of CMUT-based imaging technologies. In the context of CMUT design and integration with associated electronics, flexible and reliable CMUT models that can be seamlessly simulated with the read-out circuits and provide insights in the system-level performance are of great importance. This work proposes a generic Verilog-AMS model for CMUT sensors that takes into account the non-linearities, dynamic behavior and harmonic resonances of the CMUT. This model is able to provide reliable estimations of the pull-in voltage as well as the resonance frequency and the spring softening effect.
To improve the signal-to-noise ratio (SNR), integrating the CMUT transducer with the front-end electronics is critical. Design and implementation of a comprehensive analog front-end system in a 0.8μm high-voltage CMOS technology which includes high-voltage and fast-switching transmitters as well as low-power variable-gain receivers is presented. Co-simulation of the front-end electronics and the CMUT model demonstrates full system functionality. Experimental results of the system at the transmit mode confirm the reliability of this co-simulation. An on-chip adaptive biasing unit (ABU) is also included in the design which aims to improve the CMUT receive sensitivity. The ABU consists of a DC-DC converter to generate a range of bias voltage levels and a digital control unit to select the desired voltage. Co- simulation of the ABU with the Verilog-AMS model confirms the increase in the CMUT sensitivity in receive mode.
In the context of CMUT super-resolution imaging, we present the design of a transceiver circuit in a 0.35μm high-voltage CMOS technology that supports both the fundamental and asymmetric modes of operation. The transmitter provides high- voltage pulses to the CMUT electrodes. The receiver includes transimpedance analog adders to add the fundamental mode in-phase signals as well as differential amplifiers to combine the out-of-phase signals of the asymmetric modes. Furthermore, low- power variable-gain stages are included to amplify the resulting signals and facilitate interfacing to the ultrasound imaging machine for additional processing and display. The design functionality is confirmed by experimental results.<br>Applied Science, Faculty of<br>Electrical and Computer Engineering, Department of<br>Graduate
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Qureshi, Muhammad Shakeel. "Integrated front-end analog circuits for mems sensors in ultrasound imaging and optical grating based microphone." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/29613.
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Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2009.<br>Committee Chair: Hasler, Paul; Committee Co-Chair: Degertekin, Levent; Committee Member: Anderson, David; Committee Member: Ayazi, Farrokh; Committee Member: Brand, Oliver; Committee Member: Hesketh, Peter. Part of the SMARTech Electronic Thesis and Dissertation Collection.
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Lebron, Agustin. "An analog front-end for powerline communications." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ63020.pdf.
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Theie, Øyvind Bjørkøy. "A Novel Analog Front-End For ECG Acquisition." Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2012. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-19547.
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A complete analog front-end for portable ECG systems in 65nm technology was modeled and simulated using Cadence Virtuoso. All the required components for the AFE was incorporated into the continuous-time loop filter of a 10-bit ADC. By varying the effective transconductance of the input OTA, preamplification of the input signal was achieved. The required filtering is achieved through the ADC's own loop filter and through digital post-filtering. The ADC meets the IEC60601-2-47 standard. This simple, minimal and digitally assisted converter achieve some attractive features by dynamically adapting the programmable signal gain of the first integrator to keep the output signal range at a more constant level where the SNDR is sufficiently high.The ADC has a 100Hz bandwidth, achieves an ENOB of over 9.4 bits at a power consumption of 3.6 uWatts. The input referred noise ranges from 2.7uV(RMS) to 18.7uV(RMS) depending on gain setting. The estimated area consumption is about 0.2mm2.
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Tavakoli, Dastjerdi Maziar 1976. "An analog VLSI front end for pulse oximetry." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/36184.
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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.<br>Includes bibliographical references (p. 210-216).<br>Pulse oximetry is a fast, noninvasive, easy-to-use, and continuous method for monitoring the oxygen saturation of a patient's blood. In modem medical practice, blood oxygen level is considered one of the important vital signs of the body. The pulse oximeter system consists of an optoelectronic sensor that is normally placed on the subject's finger and a signal processing unit that computes the oxygen saturation. It uses red and infrared LEDs to illuminate the subject's finger. We present an advanced logarithmic photoreceptor which takes advantage of techniques such as distributed (cascaded) amplification, automatic loop gain control, and parasitic capacitance unilateralization to improve the performance and ameliorate certain shortcomings of existing logarithmic photoreceptors. These improvements allow us to reduce LED power significantly because of a more sensitive photoreceptor. Furthermore, the exploitation of the logarithmic nonlinearity inherent in transistors eliminates the need of performing some of the mathematical operations which are traditionally done in digital domain to calculate oxygen saturation and allows for a very area-efficient all-analog implementation. The need for an ADC and a DSP is thus completely eliminated.<br>(cont.) We show that our analog pulse oximeter constructed with red and infrared LEDs and our novel photoreceptor at its front end consumes 4.8mW of power whereas a custom-designed ASIC digital implementation (employing a conventional linear photoreceptor) and the best commercial pulse oximeter are estimated to dissipate 15.7mW and 55mW, respectively. The direct result of such power efficiency is that while the batteries in this commercial oximeter need replacement every 5 days (assuming four "AAA" 1.5V batteries are used), our analog pulse oximeter allows 2 months of operation. Therefore, our oximeter is well suited for portable medical applications such as continuous home-care monitoring for elderly or chronic patients, emergency patient transport, remote soldier monitoring, and wireless medical sensing.<br>by Maziar Tavakoli Dastjerdi.<br>Ph.D.
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Uyar, Oğuzhan. "Front-end circuits for a photonic analog-to-digital converter." Thesis, Massachusetts Institute of Technology, 2011. http://hdl.handle.net/1721.1/68510.
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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (p. 79-80).<br>As the resolution of electrical ADCs gets limited at higher sampling rates due to sampling clock jitter, low-jitter mode-lock laser based photonic ADCs are starting to gain more attention. As well as low-jitter and high-linearity operation at very high speeds, photonic ADCs provide the opportunity to de-multiplex electrical signals to enable the parallel sampling of signals which increases the total sampling speed dramatically. However, even in photonic systems, a careful optimization between the degree of de-multiplexing, the optical non-linearities and receiver front-end noise has to be performed to enable resolution and sampling rate gains to materialize. Electrical components still constitute the bottleneck for a photonic ADC system. Photo-detector front-end, which is responsible for the current-voltage transformation of the samples, is one of the most critical components for the overall linearity, noise and jitter performance of photonic ADC systems. This work focuses on photo-detector front-ends and investigates the performance of several structures as well as evaluating the performance of photonic ADC systems depending on the amount of photo-detector current. Integrator and trans-impedance amplifier flavors of the front-end circuits are designed, implemented, simulated and laid out for 6 ENOB and 10 ENOB linearity and noise performance at 1GS/s. The circuits are implemented on 45 nm SOI process and integrated with on-chip photonic components which allow on-chip and off-chip ADC implementations.<br>by Oğuzhan Uyar.<br>S.M.
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Wang, Jiazhen. "Design of an Analog Front-end for Ambulatory Biopotential Measurement Systems." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-37216.
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A critical and important part of the medical diagnosis is the montioring of the biopotential signals. Patients are always connected to a bulky and mains-powered instrument. This not only restricts the mobility of the patients but also bring discomfort to them. Meanwhile, the measureing time can not last long thus affecting the effects of the diagnosis. Therefore, there is a high demand for low-power and small size factor ambulatory biopotential measurement systems. In addtion, the system can be configured for different biopotential applications.The ultimate goal is to implement a system that is both invisible and comfortable. The systems not onlyincrease the quality of life, but also sharply decrease the cost of healthcare delivery. In this paper, a continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biopsignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design of the critical transistors eliminates the need of chopping circuits. The front-end is pure analog without interference from digital parts like chopping and switch capacitor circuits. The chip is fabricated under SMIC 0.18 μm CMOS process. The input-referred noise of the system is only 1.19 μVrms (0.48-2000Hz).Although the power consumption is only 32.1 μW under 3V voltage supply, test results show that the chip can successfully extract biopotential signals.
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Razzaghpour, Milad. "Design and Optimization of an Analog Front-End for Biomedical Applications." Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-90236.
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The state-of-the-art analog front-end of implantable biosensors is the class of current-mirror-based circuits. Despite their superior noise performance, power consumption and area, they suffer from systematic and random errors causing offset, gain and linearity error in reading out the sensor data. In the first part of this thesis, a new analog front-end is proposed to eliminate the systematic error. The proposed topology is able to accurately copy the sensor current which will be converted into the proportional voltage for further processing. Additionally, a theoretical discussion regarding the functionality of the proposed topology is given and a thorough study on the effect of random error sources is carried out. In the second part of this thesis, in order to optimize the design of the proposed analog front-end, an optimization algorithm is proposed. The proposed optimization algorithm takes advantage of a modified Imperialist Competitive Algorithm. The original imperialist competitive algorithm shows a low search ability in high-dimensional search spaces which is the case in optimization of analog circuits. A thorough comparison between the original imperialist competitive algorithm, the proposed algorithm and genetic algorithm as a reference is carried out. It will be revealed that the proposed algorithm is capable of exploring the cost space more efficiently than the other two algorithms, thereby resulting in better trade-offs between design objectives to reach higher cost values. Furthermore, according to the mathematical benchmarks, the proposed algorithm is more than 1.5 times faster than the other algorithms in finding the global minimum, which is essential in simulation-based optimization procedures. The proposed optimization algorithm is used to design the proposed analog front-end. The results show an average of 25.8 times higher FoM when designed with the optimization algorithm as opposed to traditional design. The design and simulation is carried out in a commercial 150nm CMOS process. The optimally-designed analog front-end shows a highly-linear highly-accurate performance in a low-noise condition, while consuming only 32μW.
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Shah, Julin Mukeshkumar. "Compressive Sensing Analog Front End Design in 180 nm CMOS Technology." Wright State University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=wright1440381988.
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Malachowska, Julia, and Miko Nore. "Emulation of Analog Front-End isoSPI communication for Battery Management Systems." Thesis, KTH, Mekatronik, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-297789.
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This study aims to investigate how an emulator could be developed as a testing tool for Battery Management Systems (BMS) by emulating the Analog Frontend (AFE) circuit communicating with a control unit for monitoring of LithiumIon Batteries. All of the research was conducted in the context of the company Northvolt. By analysing data collected through a questionnaire, it was evident that an emulator testing tool could potentially make the BMS development process significantly more efficient. A demonstrator was developed as a part of the study. It fulfilled almost all of the requirements initially stated, but required the control unit to send commands in a fixed sequence, which the current BMS control unit did not. A fixed sequence would however enable the incorporation of the developed emulator, as well as introducing other advantages such as predictability. The study showed that the most important factor to consider for developing an AFE communication emulator for BMS testing was robustness and repeatability of the timings of the communication signals.<br>Syftet med denna studie var att undersöka hur ett testverktyg baserat på en emulator skulle kunna utvecklas för batteristyrsystem. Studien genomfördes på batteriföretaget Northvolt. Genom att analysera data insamlad via ett frågeformulär framgick det tydligt att ett testverktyg baserat på en emulator hade god potential att göra utvecklingsprocessen av batteristyrsystem mer effektiv. En prototyp utvecklades som en del av studien. Denna uppfyllde nästan alla de initialt uppsatta kraven, men var anpassad för kommunikation i en fix sekvens, till skillnad från det aktuella systemet hos företaget. Via studien fann man att implementationen av en fix kommunikationssekvens skulle medföra önskvärda egenskaper hos systemet såsom förutsägbarhet. Vidare visade studien att den viktigaste faktorn att ta i beaktning för utveckling av en emulator var robusthet och repeterbarhet hos timingen av kommunikationssignalerna. Detta eftersom kommunkationen mellan enheter förlitar sig på korrekt timing av varje skickad bit för korrekt inlästa meddelanden.
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MALACHOWSKA, JULIA, and MIKO NORE. "Emulation of Analog Front-End isoSPI communication for Battery Management Systems." Thesis, KTH, Skolan för industriell teknik och management (ITM), 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-299264.
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This study aims to investigate how an emulator could be developed as a testing tool for Battery Management Systems (BMS) by emulating the Analog Front-end (AFE) circuitcommunicating with a control unit for monitoring of Lithium-Ion Batteries. All of the research was conducted in the context of the company Northvolt. By analysing data collected through a questionnaire, it was evident that an emulator testing tool could potentially make the BMS development process significantly more efficient. A demonstrator was developed as a part of the study. It fulfilled almost all of the requirements initially stated, but required the control unit to send commands in a fixed sequence, which the current BMS control unit did not. A fixed sequence would however enable the incorporation of the developed emulator, as well as introducing other advantages such as predictability. The study showed that the most important factor to consider for developing an AFE communication emulator for BMS testing was robustness and repeatability of the timings of the communication signals.<br>Syftet med denna studie var att undersöka hur ett testverktyg baserat på en emulator skulle kunna utvecklas för batteristyrsystem. Studien genomfördes på batteriföretaget Northvolt. Genom att analysera data insamlad via ett frågeformulär framgick det tydligt att ett testverktyg baserat på en emulator hade god potential att göra utvecklingsprocessen av batteristyrsystem mer effektiv. En prototyp utvecklades som en del av studien. Denna uppfyllde nästan alla de initialt uppsatta kraven, men var anpassad för kommunikation i en fix sekvens, till skillnad från det aktuella systemet hos företaget. Via studien fann man att implementationen av en fix kommunikationssekvens skulle medföra önskvärda egenskaper hos systemet såsom förutsägbarhet. Vidare visade studien att den viktigaste faktorn att ta i beaktning för utveckling av en emulator var robusthet och repeterbarhet hos timingen av kommunikationssignalerna. Detta eftersom kommunkationen mellan enheter förlitar sig på korrekt timing av varje skickad bit för korrekt inlästa meddelanden.
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Leung, Matthew Chung-Hin. "CMOS RF SOC Transmitter Front-End, Power Management and Digital Analog Interface." Thesis, Georgia Institute of Technology, 2008. http://hdl.handle.net/1853/24664.
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With the growing trend of wireless electronics, frequency spectrum is crowded with different applications. High data transfer rate solutions that operate in license-exempt frequency spectrum range are sought. The most promising candidate is the 60 GHz multi-giga bit transfer rate millimeter wave circuit. In order to provide a cost-effective solution, circuits designed in CMOS are implemented in a single SOC.
In this work, a modeling technique created in Cadence shows an error of less than 3dB in magnitude and 5 degree in phase for a single transistor. Additionally, less than 3dB error of power performance for the PA is also verified. At the same time, layout strategies required for millimeter wave front-end circuits are investigated. All of these combined techniques help the design converge to one simulation platform for system level simulation.
Another aspect enabling the design as a single SOC lies in integration. In order to integrate digital and analog circuits together, necessary peripheral circuits must be designed. An on-chip voltage regulator, which steps down the analog power supply voltage and is compatible with digital circuits, has been designed and has demonstrated an efficiency of 65 percent with the specific area constraint. The overall output voltage ripple generated is about 2 percent.
With the necessary power supply voltage, gate voltage bias circuit designs have been illustrated. They provide feasible solutions in terms of area and power consumption. Temperature and power supply sensitivities are minimized in first two designs. Process variation is further compensated in the third design. The third design demonstrates a powerful solution that each aspect of variations is well within 10%.
As the DC conditions are achieved on-chip for both the digital and analog circuits, digital and analog circuits must be connected together with a DAC. A high speed DAC is designed with special layout techniques. It is verified that the DAC can operate at a speed higher than 3 Gbps from the pulse-shaping FIR filter measurement result.
With all of these integrated elements and modeling techniques, a high data transfer rate CMOS RF SOC operating at 60 GHz is possible.
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Amin, Farooq ul. "On the Design of an Analog Front-End for an X-Ray Detector." Thesis, Linköping University, Department of Electrical Engineering, 2009. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-21395.
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<p>Rapid development in CMOS technology has resulted in its suitability for the implementation of readout front-end systems in terms of high integration density, and low power consumption yet at the same time posing many challenges for analog circuits design like readout front-end. One of the significant challenges is the low noise design for high speed front-end systems, while at the same time minimizing the power consumption as much as possible.</p><p>A high speed, low noise, low power, and programmable readout front-end system is designed and implemented for an X-ray detector in CMOS 0.18 m technology in this thesis work. The front-end system has a peaking time of 10 ns, which is the highest speed ever reported in the published work. The front-end system is designed to achieve low noise in terms of ENC, and a low power consumption of 2.9 mW. The detector capacitance is the most dominating parameter to low noise, which in turn is directly related to the power consumption. In this thesis work an ENC of 435 electrons is achieved for a detector capacitance of 5 pF and an ENC of 320 electrons for a detector capacitance of 3 pF. Based on the comparison to related published work, a performance improvement of at least two times is achieved taking peaking time, power, ENC, and detector capacitance all into consideration. The output pulse after amplification has peak amplitude of 300 mV for a maximum injected charge of 40000 electrons from the detector.</p><p>The readout front-end system noise performance is strongly dependent on the input MOSFET type, size, and biasing. In this work a PMOS has been selected and optimized as the input device due to its smaller 1/f noise and high gain as compare to NMOS when biased at same currents. The architecture designed in this work consists of a folded cascode CSA with extra cascode in first stage, a pole-zero cancellation circuit to eliminate undershoot, a shaper amplifier, and integrators using Gm-C filter technique. All of these components are optimized for low power while meeting the noise requirements. The whole front-end system is programmed for peaking times of 10, 20, and 40 ns. The programmability is achieved by switching different capacitors and resistors values for all the poles and zeros in the front-end, and by switching parallel transconductance in the Gm-C filters. Finally fine tuning of all the capacitance, resistance, and transconductance values is done to achieve required performance.</p>
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Graham, David W. "A Biologically Inspired Front End for Audio Signal Processing Using Programmable Analog Circuitry." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11549.
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This research focuses on biologically inspired audio signal processing using programmable analog circuitry. This research is inspired by the biology of the human cochlea since biology far outperforms any engineered system at converting audio signals into meaningful electrical signals. The human cochlea efficiently decomposes any sound into the respective frequency components by harnessing the resonance nature of the basilar membrane, essentially forming a bank of bandpass filters. In a similar fashion, this work revolves around developing a filter bank composed of continuous-time, low-power, analog bandpass filters that serve as the core front end to this silicon audio-processing system. Like biology, the individual bandpass filters are tuned to have narrow bandwidths, moderate amounts of resonance, and exponentially spaced center frequencies. This audio front end serves to efficiently convert incoming sounds into information useful to subsequent signal-processing elements, and it does so by performing a frequency decomposition of the waveform with extremely low-power consumption and real-time operation. To overcome mismatch and offsets inherent in CMOS processes, floating-gate transistors are used to precisely tune the time constants in the filters and to allow programmability of analog components.
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Wilson, James Edward. "Design of a low-power, multi-resolution digital to analog converter for a W-CDMA analog front end." The Ohio State University, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=osu1342452928.
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PIPINO, ALESSANDRA. "Design of Analog Circuits in 28nm CMOS Technology for Physics Applications." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2017. http://hdl.handle.net/10281/158126.
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Il trend esponenziale delle tecnologie CMOS previsto dalla legge di Moore è stato ampiamento dimostrato nel corso degli ultimi tre decenni. Si è osservato uno scaling costante, caratterizzato da dispositivi sempre più piccoli, per soddisfare le esigenze delle applicazioni digitali in termini di velocità, complessità, densità circuitale e basso consumo di potenza. Ogni nodo tecnologico è rappresentato dalla minima lunghezza ottenibile, che corrisponde alla lunghezza del canale del più piccolo transistor che si può integrare.
Con l'arrivo delle tecnologie al di sotto dei 100nm, le performance dei circuiti digitali sono ulteriormente aumentate, a scapito dei progettisti analogici che si ritrovano ad affrontare nuove problematiche. Infatti, da una parte lo scaling tecnologico comporta dei vantaggi per i circuiti digitali: aumento della velocità, basso consumo di potenza, alto livello di integrazione. I circuiti analogici invece risentono negativamente dello scaling, a causa di un peggioramento del comportamento del transistor, soprattutto per le tecnologie ultra-scalate. In queste ultime infatti, effetti del secondo ordine, fino a prima del tutto trascurabili, diventano importanti e iniziano ad essere dominanti, influenzando il funzionamento e le performance dei dispositivi. Per esempio, basso guadagno intrinseco del MOS, swing ridotto, problemi di punto operativo e elevata variabilità dei parametri, sono solo alcune delle difficoltà derivanti dallo scaling. I progettisti analogici devono far fronte a questi problemi in diverse fasi della progettazione, sia circuitale che di layout. Nonostante ciò, la progettazione di circuiti analogici in tecnologie così scalate in molti casi è determinante. Per esempio, in molti sistemi mixed-signal, dove coesistono circuiti analogici e digitali e sono necessarie alte performance ad alta frequenza, l’uso di queste tecnologie anche per la parte analgica diventa una scelta obbligata. Oppure ci sono gli esperimenti di fisica ad alta energia, dove la scelta di tecnologie scalate è strategica. Infatti in queste applicazioni, i circuiti elettronici sono esposti ad alti livelli di radiazione con conseguente peggioramento delle performance e fenomeni di malfunzionamento. Dato che il danno da radiazione è proporzionale allo spessore dell'ossido, è evidente che per i dispositivi più piccoli, il danneggiamento è inferiore. In questa tesi, i trend e le principali problematiche derivanti dall'uso di tecnologie molto scalate sono analizzati nel primo capitolo, seguiti poi dalla presentazione di circuiti integrati in tecnologia CMOS 28nm. Il primo circuito presentato nel secondo capitolo è un Fast-Tracker front-end (FTfe) per la rilevazione di cariche. In particolare il sistema di read-out è stato implementato a partire dalle principali specifiche e soluzioni circuitali già usate per la rilevazione di muoni nell'esperimento ATLAS. Il front-end proposto è in grado di rilevare un evento e subito dopo resettare il sistema in maniera tale da rendere il FTfe già pronto per il prossimo evento, evitando lunghi tempi morti. Il secondo circuito, presentato nel terzo capitolo ed anch'esso integrato in tecnologia CMOS 28nm, è un amplificatore per strumentazione di tipo Chopper. Gli amplificatori per strumentazione sono elementi chiave nelle applicazioni per sensori, dove vengono usati per amplificare segnali tipicamente piccoli (dell'ordine dei mV) e a bassa frequenza. Per questo motivo risulta importante ridurre o addirittura eliminare l'offset e il rumore flicker in ingresso, segnali che si sovrappongono al segnale utile da rilevare ed introdotto dallo stesso circuito elettronico. L'amplificatore per strumentazione proposto usa una tecnica di modulazione, chiamata chopper, per ridurre i contributi di rumore flicker ed offset. Inoltre l'intero amplificatore è stato progettato per lavorare in regione di sottosoglia, dati i problemi dovuti alla tecnologia fortemente scalata.<br>The exponential trend of the complementary metal-oxide-semiconductor (CMOS) technologies predicted by Moores law has been successfully demonstrated over the last three decades. A constant downscaling of CMOS technologies with smaller and smaller device size has been developed, in order to comply with requirements on speed, complexity, circuit density and power consumption of advanced high performance digital applications. The minimum reachable length, which corresponds to the half the length of the channel of the smallest transistor that can be manufactured, represents every following technological node.
With the arrival of nanoscale (sub-100nm) CMOS technologies, digital performance improve further, but many new challenges have been introduced for analog designers. In fact, for the digital circuits CMOS scaling-down leads to several benefits: speed improvement, reduced power consumption, high integration and complexity level. The analog circuits, instead, strongly suffers from the ScalTech trend, because the MOS behavior dramatically changes through the different technological nodes and especially for the ultra-scaled ones, where second order effects, previously negligible, become very important and start to be dominant, affecting its performance. For instance, lower intrinsic DC-gain, reduced dynamic range, operating point issues and larger parameter variability are some of the problems due to scaling-down. Analog designers must face this problems at different phases of the design, circuital and layout. Despite that, the design of analog circuit in sub-nm technologies is mandatory in some cases or can be even helpful in others. For example, in mainly mixed-signal systems, the read-out electronic requires high frequency performance, so the choice of deep submicron technology is mandatory, also for the analog part. Other types of applications where using scaled technology is even strategical are the high-energy physics experiments, where read-out circuits are exposed to very high radiation levels with consequent performance degradation and breakdown events. Since radiation damage is proportional to gate oxide volume, smaller devices exhibit lower radiation detriment. It has been demonstrated in fact, that 28nm CMOS technology devices are capable to sustain 1Grad-TID exposure, not possible with previous technologies. In this thesis, the main key challenges in ultra-scaled technologies are analyzed in the first chapter, and then integrated circuits designed in 28nm CMOS technology are presented. The first circuit design, presented in the second chapter and integrated in 28nm CMOS technology, is a Fast-Tracker front-end (FTfe) for charge detection. The read-out system has been developed starting from the main specifications and circuital solutions already adopted for muon detection in ATLAS experiment. The proposed front-end is able to detect an event and soon after to reset the system in order to make the FTfe already available for the following event, avoiding long dead times. The architecture is analyzed in detail, followed by the layout choices and the performance results. The second circuit design presented in the third chapter and always integrated in 28nm CMOS technology, is a Chopper instrumentation amplifier. Instrumentation amplifiers are the key building blocks in sensor and monitoring applications, where they are used to sense and amplify usually very small (sub-mV) and low frequency signals. For this reason it is important to reduce or eliminate the input offset and flicker noise, which cover and disturb the main signal to be detected. The proposed amplifier use a modulation technique, called chopper, in order to meet the low offset and low flicker noise requirements. Moreover it has been modeled to operate in sub-threshold region, in order to address the scaling problems. After the architecture description, layout and results of the integrated prototype are shown.
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Björkqvist, Oskar. "Analog Front End Development for the Large Hadron Collider Interlock Beam Position Monitor Upgrade." Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-253207.
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The interlock Beam Position Monitor (BPM) system in the Large Hadron Collider(LHC) is responsible for monitoring the particle beam position at the point of thebeam dump kicker magnets and is part of the machine protection system. Thecurrent interlock BPM system has some limitations and because of this, an upgradeproject has been initiated. This master thesis describes the development of theanalog front end electronics of this system, consisting mainly of two parts: A delayline based microwave filter and a high isolation and highly balanced power combinercircuit.The filter has been validated with real LHC beam measurements and is found towork as expected. More work however needs to be done to ensure the effect that thefilter itself has on the beam measurements as the filter could introduce some ringingeffects on the signal. The highly balanced high isolation power combiner has beentested through lab measurements and also shows promising results but long-termtests need to be conducted to ensure the reliability of the component as it will needto endure very high signal levels over long periods of time.<br>Det system som mäter partikelstrålens position och ansvarar för att extraktion avdenna kan ske under säkra och pålitliga former i Large Hadron Collider (LHC) heterLHC interlock beam position monitor (BPM) och är en viktig del av LHC:s maskinskydd.Det nuvarande system som utför dessa mätningar har vissa begransningaroch till följd av detta har en uppgradering av systemet påbörjats. Detta examensarbetebeskriver utvecklingen av den elektronik som kommer att användas i systemetsanaloga signalkedja som består i huvudsak av ett filter samt en balanserad effektdelareför radiofrekvenser.Filtret har utvärderats genom verkliga mätningar av partikelstrålen och har konstateratsfungera som väntat. Mer arbete krävs dock för att bestämma påverkansom filtret självt har på positionsmätningarna då det introducerar en viss ringandeeffekt på signalerna. Den balanserade effektdelaren har testats i lab och visar ocksåpå lovande resultat men kräver tester över längre tid då denna komponent kommeratt behöva utstå höga signalnivåer under långa tidsperioder.
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Giannelli, Pietro. "A Testbench System for Structural Health Monitoring with Guided-Wave Ultrasound." Doctoral thesis, 2018. http://hdl.handle.net/2158/1125295.
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This dissertation covers the design of the transducers and electronics of a structural health monitoring (SHM) testbench system targeted at plate-like structures. The health inspection principle behind the system is the transmission and reception of guided-wave ultrasound along the structure under test, using piezoelectric transducers made of poled polyvinylidene fluoride (PVDF) film.
The aim of this work is the creation of a system with custom electronics that can serve as a versatile testbench for the research activities in the field of SHM of complex material, such as carbon and glass-fiber composites, and will eventually bridge the gap between research and the development of highly-integrated sensor networks to be used in industrial, automotive, and aerospace applications. While many guided-wave SHM techniques base their operation on monolithic elements, the proposed system moves in the direction of providing multichannel transmit/receive capabilities to each transducer, transforming them in small-scale phased arrays.
Since different SHM applications require different topologies and number of transducers to effectively cover a structure, the system architecture is designed around the vision of a (wired) sensor network: each transducer is connected to its own dedicated electronics, emulating a sensor node. Multiple identical nodes can thus be placed on the target structure and interact to perform the required health monitoring functions in a distributed fashion.
The transducers designed for this system are an improvement of the well-known interdigital transducer (IDT), where a few novelties are added: a circular sensor (intended for isotropic guided-wave reception) and a resistive temperature device. A different version of the IDT is also presented where every electrode (finger) has an independent connection that can be attached to different transmitters and receivers, thus creating an array.
The electronics are designed to include multichannel transmission and data acquisition tailored to the proposed transducers. Guided-wave generation is performed by high-voltage, 5-level, differential class D amplifiers that can generate arbitrary signals up to 1MHz with inter-channel synchronization. The signal reception circuitry includes two swappable pre-amplifier stages (charge-mode and voltage-mode) in addition to a standard data acquisition chain. The electronics are completed by a system-on-chip (FPGA plus ARM processor) that operates the various components, performs signal analysis, and exchanges data with other nodes.
The core contents of this dissertation include the development and testing of the transducers and a subset of the system electronics: the ultrasound transmission and reception modules. The remainder of the system is presented at the architectural level.
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Ou, Wei-Yang, and 歐威揚. "Analog Front End for Cable Modem." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/59192764917990177712.
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碩士<br>國立臺灣大學<br>電機工程學研究所<br>87<br>In this thesis, the design and implementation of analog front end for digital cable modem are introduced. A quantizer is utilized in the automatic gain control (AGC) to regulate its loop bandwidth, which can accomplish fast acquisition and low gain fluctuation simultaneously. Meanwhile, to achieve robustness against various variations and good programmability, mixed mode circuit architecture is adopted. Except for the inevitable analog circuits such as variable gain amplifier (VGA), receive bandpass filter (Rx BPF) and gain/buffer (G/B), the rest parts are realized in digital form. Careful design optimization and parameter assignment are performed before layout. Implemented in 0.6um N-well single poly triple metal (SPTM) digital CMOS technology, the analog front end provides 25dB dynamic range, 240Hz acquisition loop bandwidth and 3.8KHz steady-state loop bandwidth for both 64QAM and 8VSB signals. The passband ripple from 1.2MHz to 7MHz is less than 1dB, and the out-of-band attenuation at 600KHz and 7MHz are 19dB and 36dB, respectively. The analog forward path consumes 70mW under 3.3V supply voltage while the digital feedback path draws 24mW from 5V supply voltage.
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Ho, Hao-Chang, and 何浩彰. "ANALOG FRONT-END DESIGN FOR USB2.0 RECEIVER." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/60419153345556245395.
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碩士<br>大同大學<br>電機工程學系(所)<br>94<br>ABSTRACT
This thesis is to discuss the high-speed transmission technique under the USB2.0 (Universal Serial Bus Revision 2.0) specification compliant, and to implement the circuit design of USB2.0 physical layer analog front-end receiver by using the process and SPICE models of TSMC 0.18um CMOS 1P5M.
In the content, several frequently used circuit structures and techniques are introduced for high-speed transmission. In addition, a physical layer analog front-end receiver circuit design for USB2.0 that is backward compatible with USB1.1 is proposed. The design is composed of the high speed differential data receiver, the transmission envelope detector, the disconnection envelope detector, the full/low speed differential data receiver and two single-ended receivers for data bus (+) and data bus (�{). The role of the high speed differential data receiver is to receive high-speed signal with a data rate of 480Mbps. The transmission envelope detector has to sense and distinguish between high-speed signal and noise from the data bus. The disconnection envelope detector has to detect the state of connection between two devices. The full /low speed differential data receiver is for receiving the signal of full speed with a data rate of 12Mbps and low speed with a data rate of 1.5Mbps. The last are two single-ended receivers that are for receiving the signal from data bus (+) and data bus (�{), respectively. The signals on the data bus are processed by the circuits mentioned above to produce the outputs to the digital circuit. Then, the digital circuit decides the data flows of these outputs of the receivers. To save the power, a power down control circuit (PD) is added at each block.
HSPICE is used to verify the overall circuit, and simulated by using the SPICE models of TSMC 0.18um CMOS 1P5M process.
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Hsieh, Wei-Che, and 謝維哲. "Analog Front-End Circuit for Biomedical System." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/04069329228935694023.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>103<br>According to statistics of the Ministry of Health and Welfare, chronic disease is one of the leading causes of death, especially in the elderly population. Because of the aging society and the threat of chronic disease, there is a high demand for personal telehealth systems. The research and application in biomedical integrated circuit become a mainstream. Due to the development of semiconductor technology and the integrated circuit design, the analog and digital circuit can be combined into a same chip. A bio-signal sensing and monitoring SoC can be realized. It is possible to develop a bio-signal sensing SoC for telehealth systems.
In order to realize a bio-signal sensing system, an analog front-end circuit plays an important role in processing analog bio-signal. In this thesis, two analog front-end circuits for bio-signal sensing are fabricated in TSMC 0.35-μm process technology. An interface circuit for multi-sensor system and a readout circuit for alternating current (AC) impedance-type sensor are proposed.
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Lin, Wei-Ming, and 林韋名. "Analog Front End for CMOS RF Transmitter." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/26706916816453845552.
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碩士<br>輔仁大學<br>電子工程學系<br>91<br>This thesis described a RF transmitter used in wireless communication system. The transmitter has three main parts, included phase-locked loop, pulsewidth control loop and transmitter front-end circuits. It’s operating frequency range is 315~916MHz. The modulation are ASK and Audio (AM) mode. The signal output power is 100mW.
The architecture of phase-locked loop is integer and divided by 32 type. It was used to provide the center frequency of the transmitter. Due to use source follower as the internal power supply of the voltage-controlled oscillator making the operating voltage supply of the voltage-controlled oscillator core circuit under the standard power supply and then output a full-swing signal using level-shift. Therefore, the duty cycle of the center frequency of the phase-locked loop is away from 50%. Here proposed a novel mutual-correlated pulsewidth control loop circuit to adjust the duty cycle of the output signal of the phase-locked loop.
The transmitter front-end circuits utilized a mode-select circuit to determine operating at ASK or Audio mode. In ASK mode, the mode-select circuit outputs the large amplitude of the center frequency and was assigned digital logic signal to mixer making it operates at non-linear region (output saturation); in Audio mode, the mode-select circuit outputs the small amplitude of the center frequency and was assigned audio signal to mixer making it operates at linear region. The mixer executes the modulation and upconversion of the ASK or audio baseband signal and the center frequency. Finally, the power of the output signal was amplified and signal was transmitted by antenna.
The TSMC 0.35μm 1P4M CMOS process is used for the circuit designs and layout. The phase-locked loop and the pulsewidth control loop is the first chip layout, the area is 670×920μm2. The transmitter front-end circuits is the second chip layout, the area is 3762.1×1766.1μm2. Due to the performances of the transmitter front-end circuits is not good implemented using the 0.35μm CMOS process; only the first chip was fabricated. The charge pump output was found a possible short problem at the chip measurements and results the loop of the phase-locked loop does not converge. However, the voltage-controlled oscillator is still work and outputs a non-50% duty cycle signal to pulsewidth control loop. The pulsewidth control loop adjusts the duty cycle of the signal as 50%, the measured frequency is 900MHz and the peak to peak jitter is 42ps.
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Chung-Yuan, Chen. "Analog Front-end Circuits for DVD-ROM Application." 2003. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0009-0112200611295788.
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Yen-Yu, Lin, and 林彥宇. "Analog Front End for ADSL-1 CAP System." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/63900233281095776053.
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碩士<br>國立臺灣大學<br>電機工程學研究所<br>87<br>In this thesis, we propose an Automatic Gain Control (AGC) system using Barker code as its training sequence for Asynchronous Digital Subscriber Loop (ADSL). The advantage of this architecture is that Barker code has the characteristic of large Peak-Side-lobe Ratio (PSR). We can easily get the information of the amplitude and the channel delay. The amplitude information is useful for the convergence of the AGC system, and the channel delay information can be provided to the equalizer.
We adopt UMC 0.5um DPDM 3v CMOS technology to design and layout our circuits. The AGC mainly is composed of forward path, such as Variable Gain Amplifier (VGA), Band-Pass Filter (BPF), and Gain & Buffer stage as well as feedback path, like Barker code detector, DAC, and integrator.
In forward path, VGA is composed of a current squaring circuit and four stages of main amplifier. The gain dynamic range of the VGA is 58db and the bandwidth is up to 20 MHz in the worst case. Besides, the total harmonic distortion is less than -66db. BPF is composed of a fourth order Chebyshev high-pass filter as well as an eighth order Elliptic low-pass filter. The bandwidth of the BPF is from 100 kHz to 500 kHz and the ripple in the pass-band must be less than 1db. Double MOSFET resistors are employed instead of the resistors in the filters. In order to overcome the process variation and thermal drift, an additional double MOSFET resistor tuning circuit is adopted. From the simulation result, the variance of the two spectrum edge is less than 1.5% in the greatest process variation and the thermal drift from 0oC to 80oC. To amplify the output of the BPF and drive it out of the chip, we design a gain & buffer stage. The cut-off frequency is up to 10 MHz with the parasitic capacitance loads of the output pads, and the THD is better than -68db when the output voltage signal is 2vpp.
In feedback path, the barker code detector receives the digital signal from the external 10-bits ADC. The auto-correlation and maximum searching circuits generate the amplitude information. Then the digital signal is converted to an analogical one by 6-bits DAC. Via the integrator, we integrate the analog from DAC and feed to VGA to control the gain.
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Huang, Yu-Ting, and 黃瑜婷. "A multi-function biomedical analog front end IC." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/93407066082979072037.
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碩士<br>國立臺灣大學<br>電機工程學研究所<br>97<br>With the advancement and maturation of semiconductor technology, the digital and analog circuit has been integrated on the same chip. In recent years, because of the demand on biomedicine, CMOS bio-sensors have already realized successfully with CMOS technique, achieving miniature, low noise, low power and low cost biomedical systems. In addition, analog front-end circuit with the function of signal arrangement is a critical component in the biomedical system. In this thesis, the main three pieces of circuit are instrumentation amplifier (IA), second-order LPF and a programmable gain amplifier (PGA). They are fabricated in TSMC 0.35μm CMOS 2P4M process.
The first stage of the system is based on IA which had accomplished by our laboratory and through the digital control switch and feedback loop to carry out the circuit system with the function of adjusting different intensity signal. Then, using a two-order LPF ( Sallen-key circuit ) to suppress the spikes from the clock feedthrough and charge injection caused by nonideality of the chopper switches. Finally, the signal is further amplified by programmable gain amplifier in the last stage. In order to let the whole system to deal with a wide range of biomedical signals and attain appropriate adjustment according to different kind of small signal sources, the design relies on a switch on/off devise to achieve these multi-functions. The die area is 1.8mm x 1.35mm and the power consumption is 944.2uW from a 3V voltage supply.
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Chang, Long-Xi, and 張用璽. "Analog Front-End Circuits Design for IF Receiver." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/00982906530351560807.
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碩士<br>國立中央大學<br>電機工程研究所<br>91<br>The project of this thesis is analog front-end circuits design for IF receiver. It concludes two components — an automatic gain control system design and an analog-to-digital system design.
In the automatic gain control system design, this system is a feedback closed loop control system and its gain can be controlled by this feedback closed loop system. Because of this gain control mechanism, the output of the system has constant magnitude with different input magnitude swings, and the output signal will have lower distortion. When input signal is 100MHz, the gain control range of this system is 30dB and the input signal range is from 10mVpp to 300mVpp. The technology is UMC018 process, power supply is 1.8V, and power consumption is 21mW.
In the analog-to-digital converter system design, a 100MSs/s 10-bit pipelined analog-to-digital converter system is designed, and it will used in the cable modem communication system or HDTV. This converter utilizes pipelined architecture to have 100MS/s conversion rate. In sample-and-hold amplifier design, it utilizes the flip-around architecture to have best feedback closed loop factor, so the OP in the sample-and-hold amplifier will cost lower power. The coarse quantizer can tolerate 500mV comparator offset without overflow by digital error correction technique. The effect of process variation in the circuit will be estimated by Monte-Carlo simulation. The technology is TSMC018 process 3.3V CMOS model, power supply is 3.3V, and power consumption is 557mW.
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Chang, Yu-Jen, and 張毓仁. "10Mbps PPM IR Communication System Analog Front-End." Thesis, 1999. http://ndltd.ncl.edu.tw/handle/69460224552023055539.
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碩士<br>國立中央大學<br>電機工程研究所<br>87<br>In this thesis, the 10Mbps PPM infrared (IR) communication system is introduced, and
implemented the analog front-end for the IR communication. The analog front-end
consists of a magnitude control circuit and a 4th-order Bessel bandpass filter.
Various configurations of the magnitude control mechanisms are discussed and compared
on view of the IR communication system. The proposed dual loop AGC provides a wide loop
bandwidth at the initial acquisition-state and a narrow loop bandwidth at the steady-state. Since
the receiver absorbs all the optical signals which includes extra noises comes from the air, the system
would have a banpass filter to strain out the other optical interference sources that is induced
from the external environment and the internal high order harmonics. The 4th-order Bessel bandpass
filter is designed with 5.5 MHz central frequency and 10 MHz bandwidth. The achievement is based on
a second-order high pass filter and second-order low pass filter.
Finally, the overall circuits are verified from post-layout simulation using TSMC
0.6um SPTM CMOS digital technology. The circuits consume 88mW(include driving
buffer) at 10MHz input signal, and the chip area is 1.8 mm^2.
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Chen, Chung-Yuan, and 陳鐘沅. "Analog Front-end Circuits for DVD-ROM Application." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/81197461743105780125.
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碩士<br>元智大學<br>電機工程學系<br>91<br>In the thesis, analog front end circuits for high speed DVD-ROM application are proposed. It can be utilized in sixteen-folds or high speed DVD-ROM. The performance of the circuit can meet the rapid demand in the future (more than 16X). In the past years, the DVD system is almost realized by BiCMOS technology. In order to reduce its cost and increase density of transistors on the same chip, CMOS technology is chosen.
The compensation technology proposed in transimpedance amplifier can broaden its bandwidth without degrading its gain. And this method can be realized by digital CMOS process without reducing its influence. An offset-free, infinite DC gain integrator is established in a feedback loop about the uncompensated circuit, resulting in a high pass system output response. The “ideal” integrator is realized via the use of a counter resulting in the cancellation of the signal’s DC offset. In order to realize this integrator in the analog domain, binary counter together with a digital-to-analog converter as an “ideal” integrator is included. It is the simplest circuit to cancel the DC offset. The speed limitation of the AGC is dominated by the gain and buffer stage. This is because of the output pad capacitance loading (~25pF). If AGC does not have to drive the large capacitor pad loading, the bandwidth will become wider. The acquisition time of AGC can be adjusted by varying the dc bias point in loop filter and integrator to satisfy the requirement of different speed DVD-ROM.
Following the AGC, the type of ADC adopted is flash ADC. In order to compensate the performance of INL and DNL, averaging network method is included. Thanks this technology it also can reduce the influence of random offset caused by process.
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Chuang, Kai-Hsiang, and 莊凱翔. "Analog Front-End Circuit Design for 10GBASE-T Ethernet." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/65527640507815318659.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>95<br>Since the Internet expands rapidly, the data rate of the local area network reaches 10 Gb/s. The optical systems with the data rate of 10 Gb/s have been proposed and implemented a few years ago. However, for the cost point of view, it is desired to implement the system with data rate of 10 Gb/s on the copper twisted-pair.
In this thesis, an analog front-end circuit suitable for 10 GBASE-T Ethernet system has been designed and implemented using CMOS technology. The analog front-end circuit includes a baseline wander (BLW) cancellation loop, a programmable gain amplifier (PGA), a low-pass filter (LPF) and a gain amplifier. The baseline wander cancellation loop compensates the BLW by a feedback loop using a digital-to-analog converter (DAC). The programmable gain amplifier compensates the signal loss due to different channel length. The low-pass filter suppresses the alien crosstalk. The gain amplifier increases the overall gain of the entire analog front-end to satisfy the system requirement. Moreover, a frequency tuning loop which controls the frequency response of the low-pass filter is implemented in this design.
The chip is fabricated using 0.18μm 1P6M CMOS technology. According to the post-layout simulations, this AFE has gain range from 4.9dB to 13.9dB with 1.5dB gain step and 293MHz bandwidth. The chip area is 0.88 x 0.82 mm2. The power consumption is 48mW under 1.8 V supply voltage. The chip is designed and verified with post-layout simulations. Testing considerations and experimental results are also presented.
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Kuo, Han-Jen, and 郭瀚仁. "Fabrication of RFID Analog Front-End and Antenna Design." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/87414767769543381841.
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碩士<br>樹德科技大學<br>電腦與通訊研究所<br>94<br>RFID System is one kind of Radio Frequency techonolog which can be used in identification system. It comprises RFID Tag and RFID Reader, which comunicate with each other by electromagnetic coupling. The advantages of RFID are long distance transfering, light, fast speed, and penetration ability. A complete RFID system has three basic components; RFID Tag, RFID Reader, and Antenna. RFID Tag and RFID Reader can be separated into RF Analog Front-End circuit and Digital Format Function circuit. About the antenna designs, there are diffent frequencies with different radio radiation techonolog. It can be Inductive coupling radiation or Backscatter coupling radiation design. This article will focus on discussing about RFID RF Analog Front-End circuit and Antenna design, the Digital Format Function will not be included in our research. Another research point is how to design the RFID antenna that can be used in microwave frequency. The microwave frequency is with International Standard in 2.45GHz ISM bands and in 5.8GHz ISM bands. In this article, we will talk about the new substrate of patch antenna, which has multiple frequencies combination, tiny architectonic, easy manufacture, and convenient integration. The new substrate of patch antenna has very high value of economy because of its low costing to manufacture, easy to produce and simple structure. Also, in this antenna's measure parameters, the new substrate of patch antenna has the best impedance matching, radiation pattern and the highest antenna gain in every frequency ranges. Please follow our article and you will see the new technology of antenna world.
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"A CMOS Analog Front-End IC for Gas Sensors." Doctoral diss., 2011. http://hdl.handle.net/2286/R.I.8911.
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abstract: This thesis presents a gas sensor readout IC for amperometric and conductometric electrochemical sensors. The Analog Front-End (AFE) readout circuit enables tracking long term exposure to hazardous gas fumes in diesel and gasoline equipments, which may be correlated to diseases. Thus, the detection and discrimination of gases using microelectronic gas sensor system is required. This thesis describes the research, development, implementation and test of a small and portable based prototype platform for chemical gas sensors to enable a low-power and low noise gas detection system. The AFE reads out the outputs of eight conductometric sensor array and eight amperometric sensor arrays. The IC consists of a low noise potentiostat, and associated 9bit current-steering DAC for sensor stimulus, followed by the first order nested chopped £U£G ADC. The conductometric sensor uses a current driven approach for extracting conductance of the sensor depending on gas concentration. The amperometric sensor uses a potentiostat to apply constant voltage to the sensors and an I/V converter to measure current out of the sensor. The core area for the AFE is 2.65x0.95 mm2. The proposed system achieves 91 dB SNR at 1.32 mW quiescent power consumption per channel. With digital offset storage and nested chopping, the readout chain achieves 500 fÝV input referred offset.<br>Dissertation/Thesis<br>Ph.D. Electrical Engineering 2011
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Chuang, Kai-Hsiang. "Analog Front-End Circuit Design for 10GBASE-T Ethernet." 2007. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2307200720031100.
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CHANG, HAO-SHUN, and 章豪順. "Automatic Gain Control for VDSL Receiver Analog Front End." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/29298378404664587316.
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碩士<br>國立臺灣大學<br>電機工程學研究所<br>90<br>The broadband access technologies, such as various kinds of digital subscriber loops (xDSL) have been implemented with a mixture of IC technologies. They provide robust transport of data on twisted pair without interfering with classical telephone service. However, to overcome high attenuation and large echo of the copper wire, the analog front end circuit (AFE) should possess low noise enhancement, low signal distortion, accurate channel filtering and high dynamic range characteristics.
This thesis presents the design and implementation of a low-voltage dual-loop mixed-signal automatic gain control (AGC) for Very High Speed Digital Subscriber Loop (VDSL) system. The AGC consists of an analog forward signal path and a digital feedback control path. Applied to VDSL system for up/down stream, the AGC calls for its analog parts operating in tens of Mega-hertz frequency. To robustly control the gain of the AGC, the control path takes advantage of digital circuitry that is less susceptible to process and temperature variations. The control path is configured as a dual-loop structure that switches the loop bandwidth to 12kHz in the acquisition state and 5.6kHz in the steady state. This facilitates a faster acquisition process and a noise-insensitive control. Implemented in 0.35um TSMC 1P4M digital CMOS technology, the AGC occupies 1.9mm X 2.1mm chip area. According to the simulation, it provides constant magnitude output for input signal strength from 20mVpp to 400mVpp. The acquisition time is less than 0.5ms. The analog forward path consumes 36mW under 2V supply voltage and the digital feedback path draws 3.35 mA from 3.3V supply voltage.
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Su, Wen-Hong, and 蘇文鴻. "Analog Front-End Circuit Design for Digital Image Processing." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/79283557582856335583.
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碩士<br>輔仁大學<br>電子工程學系<br>98<br>With the proliferation of digital cameras and multi-functional printers, document scanning has become much more easily. Image processor IC’s have been popular consumer electronic products. The core image processor IC’s can be classified two catalogs: one is based on CMOS technologies and the other is with CCD architecture.
The two factors, price and resolution actually determine the applications of the two image processor IC’s. The CCD based image IC’s have the advantages of high S/N and large dynamic range, which therefore are employed in the products of high resolution and high scan speed. By contract, CMOS based image IC’s are used in low-resolution and low-speed products.
In this thesis, we present the analog front-end readout circuit design specifications of CMOS image IC’s. Meanwhile, we also propose a novel architecture of the readout circuits to improve the S/N of CMOS based image IC’s, which we expect the proposed architecture can be applied in high-resolution and high-speed image circuits.
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Kao, Min-Sheng, and 高旻聖. "CMOS Analog Front-end Transceiver IC for Wireline Communications." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/68305604504950596777.
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博士<br>國立清華大學<br>通訊工程研究所<br>99<br>This study proposes several circuit design techniques to achieve high performance CMOS transceiver chipset for wire-line communication. The circuit concepts are demonstrated by a 20-Gb/s CMOS 0.13-μm laser/modulator driver design and a 10-Gb/s CMOS 0.18-μm limiting amplifier design. The performance evaluation are as good as the advanced expensive III-V compound technology and the fabricated CMOS circuits are suitable for further integration with SERDES, CDR, and CODEC ICs for wire-line communication due to the small die size and low power consumption. The proposed 20-Gb/s laser/modulator driver is fabricated in 0.13-µm mixed-signal 1.2/2.5V 1P8M CMOS process. This work consists of a shunt-series inductor peaking pre-driver stage and a pre-emphasis output driver stage with source de-generation configuration including inductive local feedback network to enhance the operation bandwidth. The data rate is measured up to 20-Gb/s with 3.5VPP S.E. output amplitude in driving 50-Ω output load when the input amplitude is less than 0.15VPP and the rise/fall time of output waveform is less than 22-ps. The total power consumption is 900-mW with 1.2/4.0V dual supply and the chip die size is 900×800-µm2. The proposed 10-Gb/s current mode logic (CML) limiting amplifier is fabricated in 0.18-µm 1P6M CMOS process. This work consists of input equalizer, CML output buffer and gain stages with active-load inductive peaking, duty cycle correction (DCC) and gain control features. The circuit techniques include active load inductive peaking, source de-generation peaking and active feedback with current buffer in Cherry-Hooper topology to enhance operation bandwidth. The proposed design provides 600-mVpp differential voltage swing in driving 50-Ω output loads, 40-dB input dynamic range, 40-dB voltage gain and 8-mVpp input sensitivity. The total power consumption is 85-mW with 1.8V supply and the chip die size is 700×400-µm2.
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Huang, Ming-Yang, and 黃名揚. "An Analog Front-end Circuit For Biomedical SignalAcquisition Systems." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/19257404964821234072.
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碩士<br>國立中正大學<br>電機工程研究所<br>100<br>The ones of the top ten causes of the death in the world are including Ischaemic heart disease as well as Stroke and other cerebrovascular disease. However, the diagnosis of disease usually requires long time to monitor the related bio-signals, eg. EEG or ECG. A wireless biomedical signal acquisition systems with low power consumption and high resolution is necessary for monitoring effectively and carrying conveniently.
In this thesis, an analog front end circuit for wireless biomedical signal acquisition systems is implemented. Different from the tradition acquisition systems, the proposed analog front end circuit with a signal bandwidth of 200 Hz, Effective number of bits ( ENOB) of 12 bits is simpler to save on the power consumption.
The circuits with chopper stabilization preamplifier and high-pass sigma-delta modulator are implemented in TSMC 0.18μm 1P6M CMOS process. The measured results reveal the SFDR is 72dB.The total power consumption is 28.5μW under the supply voltage of 1.2V.
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Chen, Yu-Junk, and 陳鈺融. "A New Analog Front-End Circuit for Biomedical Applications." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/g69wqe.
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碩士<br>國立臺北科技大學<br>電腦與通訊研究所<br>96<br>This thesis is focused on investigating the low power consumption in biomedical front-end circuit; besides, performance of the circuit has been raise. The development of low power and low noise design has become the focus of biomedical applications. The performance of biomedical recording system depends on the instrumentation amplifier, such as Electrocardiogram or Electroencephalogram recording. It is to amplify very small voltage signal to large voltage amplitudes; nonetheless, the system is sensitively associated with noise and common-mode voltage because of these signals are usually greater than input signal. In traditional circuits, the current-mode instrumentation amplifier (CMIA) has the advantage for high CMRR performance, but it exhibits high significantly 1/f noise. On the other hand, the current mirror of the CMIA is mismatch and will be lower the CMRR.
In this thesis, CMIA using differential difference current conveyor, the interference of noise from 1/f noise can be removed by chopper-stabilized technology. The interference of common-mode voltage is reduced by the current-mode circuit that uses the cascode current mirror. Besides, the load effect is reduced by the high input impedance of the CMIA. The signal outside the bandwidth is removed by second order low-pass filter using switched-capacitor circuit, and the inner bandwidth counterpart is processed by second order sigma-delta modulator. For three circuits above, whose power supplies are ±0.9V, is implemented using TSMC 0.35um process.
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Tahmoureszadeh, Tina. "Analog Front-end Design for 2x Blind ADC-based Receivers." Thesis, 2010. http://hdl.handle.net/1807/29988.
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This thesis presents the design, implementation, and fabrication of an analog front-end (AFE) targeting 2x blind ADC-based receivers. The front-end consists of a combination of an anti-aliasing filter (AAF) and a 2-tap feed-forward equalizer (FFE)
(AAF/FFE), the required clock generation circuitry (Ck Gen), 4 time-interleaved
4-b ADCs, and DeMUX. The contributions of this design are the AAF/FFE and the Ck Gen. The overall front-end optimizes the channel/filter characteristics for data-rates of 2-10 Gb/s. The bandwidth of the AAF is scalable with the data-rate
and the analog 2-tap feed-forward equalizer (FFE) is designed without the need for
noise-sensitive analog delay cells. The test-chip is implemented in 65-nm CMOS and
the AAF/FFE occupies 152×86 μm2 and consumes 2.4 mW at 10 Gb/s. Measured frequency responses at data-rates of 10, 5, and 2 Gb/s confirm the scalability of the front-end bandwidth. FFE achieves 11 dB of high-frequency boost at 10 Gb/s.
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Chen, Yu-chih, and 陳昱誌. "Analog Front-end Integrated Circuit Design for Bio Signal Processing." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/67072861512365413562.
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碩士<br>國立中正大學<br>電機工程所<br>94<br>This thesis has two parts including the design of microstimulator for neuromuscular stimulation and the analog front-end circuit for hearing aid system. The microstimulator includes three circuits: Regulator, Controller, Microstimulator. And the hearing aid frond-end system includes two circuits: Preamplifier, lowpass filter. In the part one, the necessary power and data of microstimulator utilize the RF coupling to be transmit to the inside circuit. By way of supply voltage to internal circuit, voltage regulator the DC signal can be obtained to provide. In addition, the clock and data can be extracted by the Manchester decoder, and the series data will be transferred to parallel for microstimulator. In order to reach the function of the muscle nerve stimulation, the microstimulator with 8-bit digital-to-analog converter is required. In the part two, the input signal through microphone will be converted to voltage signal. Because the converted voltage signal of microphone is very small in several hundred uV to several mV. So we need a preamplifier to amplify the signal to the required range of the ADC. The frequency range for the ears of people is from 20Hz to 20KHz, and the obvious characteristic frequency of human speech is 0.5KHz to 8KHz. Therefore, we need a lowpass filter to filter out of frequency of 10KHz to avoid the aliasing as the output signal of filter is processing in the ADC. The preamplifier and lowpass filter adopt switched-capacitor technique for circuit design. This chip use TSMC 0.35um 2P4M process. The feature of microstimulator is illustrated as follows: 1.Regulator can change 5V to 3V 2.The decoder adopts Manchester code technique 3.Two kinds of stimulated frequency, 20Hz and 2KHz, are adopted and the stimulated current is from 0mA to 1mA. The features of analog front-end circuit for digital hearing aid is described as follows: 1.Preamplifier variable gains 42db, 54db, 66db, and respectively sample frequency is 250KHz. 2.The sample frequency of lowpass filter is 250KHz, cutoff frequency is 10KHz,operation voltage is 3V.
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Chen, Yi-Huei, and 陳宜惠. "2V CMOS Analog Front-End Circuit Designs for Pager Receiver." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/27206890014835830823.
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碩士<br>國立中央大學<br>電機工程學系<br>86<br>With the progress of digital signal processing, many
complicate functions can be realized by modern VLSI technology.
However, for analog signal processing, many existing
solutions are still not cost and power effective. The main
objective of thisthesis is to develop the low-voltage low-power
circuit design techniques for analog front-end application.
The proposed circuits are based on the heterodyne receiver
architecture. RF/IF analog-front-end functions are included
for pager receiver applications. Since they are for wireless
communication requirements, power dissipation is a determinant
factor on exploring and developing the circuit structures.
At RF stage, a 280MHz low-noise amplifier and a 280MHz to
10.7MHz mixer are introduced. A shunt-feedback type
amplifier followed by an open-drain buffer is proposed as
LNA. It provides moderate gain of 18dB S21 and 3.65dB NF with
power consumption of 4.6mW. For mixer design, a single-balanced
structure is employed. It provides 9.4dB conversion gain
while dissipates 3mW power for 2-V supply operation.
In 455KHz IF signal processor, a 3-stage limiting amplifier and
a quadrature demodulation are included. A feedforward type
offset cancellation structure is proposed to eliminate the
need of external capacitors. A quadrature with external phase
shifting network and an on-chip phase detector shows a good
frequency discrimination performance under low voltage
operation. The input dynamic range is 72dB and the
demodulation constant is 20mV/KHz. The total circuits
consume 2.3mW.
For 10.7MHz IF signal processing, a seven-stage limiting
amplifier and a RSSI areinvolved. The seven-stage structure gets
a good compromise between speed and power performance.
Each gain stage is a source-coupled pair with a folded diode
load. It can meet the DC-coupled requirements for 2-V operation.
The proposed limiting amplifier can achieve smaller than
-78dBm sensitivity. For logarithmic RSSI stage, a current
mode rectification and summation are proposed to achieve the
required linear approximation. The measured results indicate
that the dynamic range can be wider than 70dB. The power
consumption is 6.2mW. The
proposed circuits are all implemented using a 0.6um digital CMOS
technology. The power supply is 2-V. Measured results
demonstrate good agreements with the original design concepts.
Although the proposed circuit structures are mainly for
pager system, it is believed that many techniques can be applied
to otherwireless RF/IF signal processings that need low-voltage
low-power operations.
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Hsueh, Jen-Chieh, and 薛人傑. "A Three-channel True-time delay Beamforming Analog Front-end." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/93274771829790793271.
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碩士<br>國立臺灣大學<br>電子工程學研究所<br>102<br>Beamforming is a signal processing technique used in sensor arrays. After specific time delay, signal will be constructive interference or destructive interference. Beamforming used in many applications, ex: biomedical ultrasound imaging system, communication transmit system, sonar detection system, etc. By using 0.18-μm CMOS process, two circuits are implemented in this thesis. The first chapter introduces the fundamentals of a true-time delay beamforming system. Chapter 2 illustrates the basics and challenges in true-time delay beamforming design and the link budget calculation is demonstrated for system optimization.
In Chapter 3, an analog beamforming front-end circuit, including amplifiers, an adder and an analog-to-digital converter, is implemented by using a 0.18-μm CMOS process.
In Chapter 4, a power saving and rotatable beamforming analog front-end is implemented by using a 0.18-μm CMOS process. Finally, a conclusion of this thesis is made in Chapter 5.
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Li, Chien-Ting, and 黎建廷. "Design of CMOS Image Sensor Digital Analog-Front-End Circuits." Thesis, 2013. http://ndltd.ncl.edu.tw/handle/85646041997919655199.
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碩士<br>中華科技大學<br>電子工程研究所在職專班<br>101<br>This thesis presents design of a 10-bit CMOS image sensor analog front-end (AFE) circuit. The front-end circuit consists of a photodiode array of 256, a three-time sening amplification circuit for each photodiode, and a 10-bit pipelined analog-to-digital converter (ADC) as readout circuit.
Among the CMOS image sensor architectures, the active type is the most popular compared to the passive one. The active CMOS image sensors has higher sensitivity, lower power consumption, and is highly integrated. In addition, use of the pipelined ADC can achieve moderate resolution for higher speed applications such as image processing.
This thesis compares three kinds of CMOS image AFE circuits to obtain the best architecture among them. The TSMC 0.18 um, 1P/6M, mixed-signal/RF, 1.8V/3.3V process is used for design. HSPICE simulation results show that, the architecture with a CMOS image sensor array of 64 by 4 and four 10-bit pipelined ADCs has the best result for area and power consumption. With a sampling frequency of 64MHz and input frequency of 19.53125KHz and the SFDR is 50dB and the power consumption is 312mA. The total chip area is estimated to be 4.381mm . The future work is to enhance the speed, to reduce the circuit area, the supply voltage, and the power consumption.
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Tung, Cheng-Wei, and 董鈞瑋. "Analog Front-End Circuit Design for the ECG Acquisition System." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/73791390117504859206.
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碩士<br>國立臺灣大學<br>電機工程學研究所<br>92<br>Abstract
A monolithic analog front-end circuit for ECG acquisition system is described in this thesis. The system includes the instrumentation, which is based on the current balancing technique that ensures this type of circuit to achieve high immunity to common mode signals as first stage, gain amplifier stage and the switched capacitor low pass filter. In order to obtain good performance of the circuit, the non-ideal effect like offset voltage has been analyzed in this thesis. The circuit was implemented in TSMC 0.35μm , 2p4m mixed-signal CMOS technology and it operates at 3.3V power supply .Full custom design flow has been used in this research. Before the fabrication of chips, these circuits had simulated by HSPICE. Good agreement has been found in computer simulation performance.
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Mo, Chu-Yuan, and 莫居緣. "Design of Analog Front-End Circuit for ECG Measurement System." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/78181569204289054667.
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碩士<br>逢甲大學<br>電子工程學系<br>103<br>The present study proposes an analog front-end (AFE) circuit used in electrocardiogram (ECG) monitoring devices to achieve low-power common-mode rejection ratio (CMRR). The overall AFE circuit comprises an instrumentation amplifier (IA) to amplify the received ECG signals in the first stage, a fourth-order high-pass filter (HPF) to exclude ECG signals below 2 mHz in the second stage, a finite-gain low-pass filter (LPF) to provide a 40 dB gain and filter out signals over 300 Hz in the third stage, and a notch filter to block the 60 Hz noise interferences generated by the power supply system in the fourth stage.
A differential-type IA was employed in the overall AFE circuit, which was combined with a common mode feedback (CMFB) circuit to further enhance CMRR.
For the filter, the researchers adopted the common differential amplifier that uses a current mirror circuit as an active load. Subsequently, the bias current for the differential amplifier was maintained at below 300 nA to reduce power consumption. The overall differential mode gain was boosted to over 67 dB, enabling the CMRR to achieve over 170 dB.
The AFE circuit designed in the present study was simulated and verified using the SiGe 180nm BiCMOS processing technology developed by the Taiwan Semiconductor Manufacturing Company (TSMC). The simulations were controlled at a voltage of 1.8 V, for an overall power consumption less than 9 µW.
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Chen, Ming-Huai, and 陳明輝. "Design of Analog Front-End Circuit for EEG Measurement System." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/11788057126613548876.
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碩士<br>逢甲大學<br>電子工程學系<br>103<br>ABSTRACT
This paper presents an analog front-end (AFE) circuitry of an electroencephalogram (EEG) measurement system with a high common-mode rejection ratio (CMRR). The whole AFE circuit includes a first-stage AC coupling circuit to filter out low frequency noise, a second-stage instrumentation amplifier with a high CMRR of three op amp to provide 53.9 dB differential-mode gain and 128.2 dB CMRR, a third-stage notch filter to filter out 60 Hz mains noise, and a fourth-stage low-pass filter (LPF) to filter out signals above 250 Hz.
The instrumentation amplifier in the whole AFE circuit is a three op amp with an AC coupling circuit added to the front to achieve high CMRR at low frequencies and an amplifier to the rear as a feedback to further enhance the gain of instrument amplifier.
The amplifier used in the filter is the differential amplifier with active current mirror load. The differential-mode gain of the whole AFE circuit can reach 59.9 dB or more with CMRR achieving 96.3 dB or more.
The proposed AFE circuit is simulated and validated by the Taiwan Semiconductor Manufacturing Company Limited (TSMC) Silicon Germanium (SiGe) 180 nm BiCMOS process technology with an operating voltage of ±1 V. The power consumption of the whole AFE circuit is less than 9.02 μW.
Keywords：EEG, AC-coupling circuit, instrumentation amplifier
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Shih, Hung-Yu, and 施泓宇. "Low-Power Reconfigurable Analog Front-End Circuits for Biomedical Applications." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/28424217475741955330.
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碩士<br>國立臺灣科技大學<br>電機工程系<br>103<br>This thesis presents a novel fully reconfigurable low-power filter and an integrated reconfigurable analog front-end channel suitable for wearable or implantable biomedical and sensor applications. Floating-gate transistors are employed as analog memories that can be reconfigured to change circuit characteristics.
The proposed reconfigurable filter consists a cascade of floating-gate transistor-capacitor (FGT-C) biquadratic sections that provide either lowpass or bandpass outputs. In the proposed biquadratic filter, all filter parameters including the gains, quality factor, natural frequency, and input and output DC levels can be adjusted by programming charges on floating gates. The filter topology exhibits good modularity so the biquadratic sections can be cascaded and scaled up to implement high-order frequency responses easily with efficient area and power consumption. Each FGT-C biquadratic filter occupies an area of 0.0313mm^2. From measurement results, the filter consumes 118.4 nW of power with a dynamic range of 45.5 dB while operating at 1.8V power supply with a 10kHz bandwidth.
A floating-gate based low-power reconfigurable analog front-end channel, including a low-noise amplifier (LNA), a variable gain amplifier (VGA), and two reconfigurable low-power Gm-C biquadratic filters, for biomedical and sensor applications is also designed and proposed in this thesis. The analog sensing frond-end circuits are integrated in a 0.35um CMOS process and occupy an area of 0.62mm^2. The bandwidth and the gain of proposed analog sensing circuits can be adjusted by programming the charge in floating gates. The prototype chip is programmed to different configurations to sense electrooculography (EOG), electrocardiography (ECG) and electromyography (EMG) signals. The total current consumption in these three configurations is 0.13μA, 0.22μA, and 0.84μA,respectively. The measured total input referred noise in these bandwidth settings are 2.67uVrms, 3.25uVrms, and 3.8uVrms, respectively. The measured noise efficiency factors in these three settings are 3.72, 3.73, and 4.26 respectively.
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"A CMOS Analog Front-End Circuit for Micro-Fluxgate Sensors." Master's thesis, 2013. http://hdl.handle.net/2286/R.I.18818.
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abstract: Fluxgate sensors are magnetic field sensors that can measure DC and low frequency AC magnetic fields. They can measure much lower magnetic fields than other magnetic sensors like Hall effect sensors, magnetoresistive sensors etc. They also have high linearity, high sensitivity and low noise. The major application of fluxgate sensors is in magnetometers for the measurement of earth's magnetic field. Magnetometers are used in navigation systems and electronic compasses. Fluxgate sensors can also be used to measure high DC currents. Integrated micro-fluxgate sensors have been developed in recent years. These sensors have much lower power consumption and area compared to their PCB counterparts. The output voltage of micro-fluxgate sensors is very low which makes the analog front end more complex and results in an increase in power consumption of the system. In this thesis a new analog front-end circuit for micro-fluxgate sensors is developed. This analog front-end circuit uses charge pump based excitation circuit and phase delay based read-out chain. With these two features the power consumption of analog front-end is reduced. The output is digital and it is immune to amplitude noise at the output of the sensor. Digital output is produced without using an ADC. A SPICE model of micro-fluxgate sensor is used to verify the operation of the analog front-end and the simulation results show very good linearity.<br>Dissertation/Thesis<br>M.S. Electrical Engineering 2013
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SHEN, DING-HONG, and 沈定宏. "Integrated Circuit Layout Implementation of ECG Analog Front-end Circuits." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/w8d58k.
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碩士<br>中華大學<br>電機工程學系<br>107<br>This thesis complete pre-layout simulations and circuit layouts of a single-lead and a multi-lead ECG analog front-end circuits. Our proposed ECG analog front-end circuit includes an instrumentation amplifier, a band-pass filter, and a post-amplifier. Besides, we use a driving right Leg (DRL) circuit to filter out common mode interference.
At first, we create an operational amplifier (OPA). Subsequently, we based on this OPA to construct a single-lead and a multi-lead ECG analog front-end circuit. We used the UMC 0.18um 2P6M CMOS process provided by National Applied Research Laboratories (NAR Labs) / Taiwan Semiconductor Research Institute (TSRI) to complete our proposed ECG analog front-end circuits. At present, pre-layout simulations and layout designs of single-lead and three-lead ECG analog front-end integrated circuits have completed.
Integrating multi-lead ECG analog front-end integrated circuit components and embedded microcontrollers with built-in analog-to-digital converters to construct multi-lead ECG measurement systems can significantly reduce the volume of the systems. The results of our work will be a part of multi-lead ECG measurement system-on-chip (SoC) in the future.
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Hung, Chih-Chien, and 洪誌謙. "Analog Front End Design for Gigabit Ethernet On Copper Wire." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/45529963901347631122.
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碩士<br>國立臺灣大學<br>電機工程學研究所<br>90<br>Ethernet has been the most successful media interface for local area networks(LANs) over the past decades. Recently, 100Mbits/s Ethernet is known as the most popular LAN. The next generation of local area networks(LANs) operates at a data rate of several hundred megabits, or gigabits per second. In order to minimize the cost, the use of the existing unshielded twisted-pair cable is desirable. However, to relax the complexity of ADC and digital signal processing circuits, the analog front end should provide coarse equalization under large echo of the copper wire.
This thesis presents the design and implementation of the front end circuits with digital control. Due to the high data rate transmission, circuits operate in tens of Mega-hertz frequency. The chip is implemented in 0.35µm 1P4M digital
CMOS technology and occupies 1.7mm X 1.7mm chip area (1.1mm X 1.1mm active) .The analog path consumes 72mW under 3.3V supply voltage with 25p load capacitance and the digital feedback path draws 2.0 mA from 3.3V supply voltage.