Bibliografías temáticas / Turbo-product-code decoder

Literatura académica sobre el tema "Turbo-product-code decoder"

Autor: Grafiati
Publicado: 14 de marzo de 2023

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Artículos de revistas sobre el tema "Turbo-product-code decoder"

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Boudaoud, A., M. El Haroussi y E. Abdelmounim. "VHDL Design and FPGA Implementation of a High Data Rate Turbo Decoder based on Majority Logic Codes". International Journal of Electrical and Computer Engineering (IJECE) 7, n.º 4 (1 de agosto de 2017): 1824. http://dx.doi.org/10.11591/ijece.v7i4.pp1824-1832.

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This paper presents the electronic synthesis, VHDL design and implementation on FPGA of turbo decoders for Difference Set Codes (DSC) decoded by the majority logic (ML). The VHDL design is based on the decoding equations that we have simplified, in order to reduce the complexity and is implemented on parallel process to increase the data rate. A co-simulation using the Dsp-Builder tool on a platform designed on Matlab/Simulink, allows the measurement of the performance in terms of BER (Bit Error Rate) as well as the decoder validation. These decoders can be a good choice for future digital transmission chains. For example, for the Turbo decoder based on the product code DSC (21.11)² with a quantization of 5 bits and for one complete iteration, the results show the possibility of integration of our entire turbo decoder on a single chip, with lower latency at 0.23 microseconds and data rate greater than 500 Mb/s.
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Zhou, Li, Hengzhu Liu y Botao Zhang. "Flexible and high-efficiency turbo product code decoder design". IEICE Electronics Express 9, n.º 12 (2012): 1044–50. http://dx.doi.org/10.1587/elex.9.1044.

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Dong, Jie, Yong Li, Rui Liu, Taolin Guo y Francis C. M. Lau. "Efficient Decoder for Turbo Product Codes Based on Quadratic Residue Codes". Electronics 11, n.º 21 (3 de noviembre de 2022): 3598. http://dx.doi.org/10.3390/electronics11213598.

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In this letter, we study turbo product codes with quadratic residue codes (called QR-TPCs) as the component codes. We propose an efficient decoder based on Chase-II algorithm with two convergence conditions for the iterative decoding of QR-TPCs. For each row and column, the Chase-II decoder will stop immediately when one of the conditions is met. The simulation results show that the proposed algorithm has a lower computational complexity compared with existing decoding methods. Moreover, a comparison with 5G low-density parity-check codes shows that the proposed turbo product codes have better performance for short code lengths.
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Ghaith, Alaa. "Improvement Of Block Product Turbo Coding By Using A New Concept Of Soft Hamming Decoder". European Scientific Journal, ESJ 12, n.º 18 (29 de junio de 2016): 167. http://dx.doi.org/10.19044/esj.2016.v12n18p167.

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The block product turbo code (BPTC) is classified as one of block turbo code concatenation forms. The Hamming code can detect two-bit error and correct one-bit error. The BPTC uses two Hamming codes for "column" coding and "row" coding, it has improved the Hamming code correcting only one error. In addition, the BPTC carries out block interleaving coding for disorganizing the transmission sequence before transmission, so as to avoid burst errors when the signal meets multi-path channel in the channel. This paper will discuss the decoding mechanism of the BPTC and analyze the efficiency of using a soft decoding algorithm in the decoding process. The soft Hamming Decoder is based on error patterns which belong to the same syndrome. It is shown that it is sufficient to investigate error patterns with one and two errors to gain up to 1.2 dB compared to hard decision decoding. Here, we will consider also the error patterns with three errors which belong to the determined syndrome, which increases the gain and improves the quality of the soft-output due to the increased number of comparisons with valid code words, in despite that, it will increase the complexity of the decoding process. The system is based on two Hamming block channel code combinations, which can be similar or different, a block interleaving to construct a BPSK modulation and BPTC coding system in the concept of feedback encoding in turbo code over an AWGN channel. To observe its coding improvement, we present the simulation results for the soft decoding of the BPTC codes of a code word length from 49 bits (using two (7,4) codes) up to 1440 bits (using two (127,120) codes).
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Leroux, Camille, Christophe Jego, Patrick Adde, Deepak Gupta y Michel Jezequel. "Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture". Journal of Signal Processing Systems 64, n.º 1 (14 de abril de 2010): 17–29. http://dx.doi.org/10.1007/s11265-010-0478-5.

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He, Yejun, Francis C. M. Lau y Chi K. Tse. "Study of bifurcation behavior of two-dimensional turbo product code decoders". Chaos, Solitons & Fractals 36, n.º 2 (abril de 2008): 500–511. http://dx.doi.org/10.1016/j.chaos.2006.06.101.

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Le Bidan, Raphaël, Camille Leroux, Christophe Jego, Patrick Adde y Ramesh Pyndiah. "Reed-Solomon Turbo Product Codes for Optical Communications: From Code Optimization to Decoder Design". EURASIP Journal on Wireless Communications and Networking 2008, n.º 1 (8 de mayo de 2008). http://dx.doi.org/10.1155/2008/658042.

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Tesis sobre el tema "Turbo-product-code decoder"

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Bade, Peter. "A 1Mbps 0.18μm CMOS Soft-output Decoder for Product Turbo Codes". Thesis, 2009. http://hdl.handle.net/1807/17493.

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A product turbo code (PTC) decoder application specific integrated circuit (ASIC) is designed in 0.18μm 1P6M CMOS with embedded SRAM. From simulation, an operating frequency of 73.1 MHz at typical conditions is obtained, yielding a throughput of 3.8 Mbps with 4 decoding iterations, while consuming 103.4 mW. The total area is 5.13 mm2. Assuming the ASIC would be used as a hard macro, the area could be reduced to 1.7 mm2. The ASIC was tested at 20 MHz under typical conditions, which resulted in a throughput of 1.0 Mbps at 1.8V supply while consuming 36.6 mW. By making a slight modification, this design can be easily scaled to support IEEE 802.16d WiMAX. Allow for this, and moving to a 45nm process an estimated throughput of 9.44 Mbps with 4 iterations can be obtained. Total macro area would be approximately 0.11 mm2.
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Capítulos de libros sobre el tema "Turbo-product-code decoder"

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Nair, Gana C., B. Yamuna, Karthi Balasubramanian y Deepak Mishra. "Hardware Design of a Turbo Product Code Decoder". En Lecture Notes in Electrical Engineering, 249–55. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-4866-0_31.

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Shivanna, Gautham, B. Yamuna, Karthi Balasubramanian y Deepak Mishra. "Design of High-Speed Turbo Product Code Decoder". En Lecture Notes in Electrical Engineering, 175–86. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-6977-1_15.

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Khavya, S., Karthi Balasubramanian, B. Yamuna y Deepak Mishra. "Design and Analysis of a Secure Coded Communication System Using Chaotic Encryption and Turbo Product Code Decoder". En Lecture Notes in Electrical Engineering, 657–66. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-33-6977-1_48.

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Actas de conferencias sobre el tema "Turbo-product-code decoder"

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Wu, Xiaoxiao, Yejun He y Guangxi Zhu. "Performance of Improved Three-Dimensional Turbo Product Code Decoder". En 2007 IEEE International Conference on Integration Technology. IEEE, 2007. http://dx.doi.org/10.1109/icitechnology.2007.4290380.

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Kuang, Wen, Renzhong Zhao y Zhu Juan. "FPGA implementation of a modified turbo product code decoder". En 2017 IEEE 9th International Conference on Communication Software and Networks (ICCSN). IEEE, 2017. http://dx.doi.org/10.1109/iccsn.2017.8230081.

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Leroux, Camille, Christophe Jego, Patrick Adde, Michel Jezequel y Deepak Gupta. "A highly parallel Turbo Product Code decoder without interleaving resource". En 2008 IEEE Workshop on Signal Processing Systems (SiPS). IEEE, 2008. http://dx.doi.org/10.1109/sips.2008.4671728.

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Wang, Yaqi, Jun Lin y Zhongfeng Wang. "A 100 Gbps Turbo Product Code Decoder for Optical Communications". En 2019 IEEE 5th International Conference on Computer and Communications (ICCC). IEEE, 2019. http://dx.doi.org/10.1109/iccc47050.2019.9064204.

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Kishore, J. Hari, B. Yamuna y Karthi Balasubramanian. "Design of a Fast Chase Algorithm based High Speed Turbo Product Code Decoder". En 2021 10th International Conference on Advances in Computing and Communications (ICACC). IEEE, 2021. http://dx.doi.org/10.1109/icacc-202152719.2021.9708201.

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Nageen, Nitin, Subhashini y Vikas Bhatia. "An Efficient FPGA implementation of Turbo Product Code decoder with single and double error correction". En 2020 National Conference on Communications (NCC). IEEE, 2020. http://dx.doi.org/10.1109/ncc48643.2020.9055995.

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