Bibliografías temáticas / Tunable bandpass delta sigma ADC

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Literatura académica sobre el tema "Tunable bandpass delta sigma ADC"

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Publicado: 25 de mayo de 2024

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Artículos de revistas sobre el tema "Tunable bandpass delta sigma ADC"

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Cardelli, L., L. Fanucci, V. Kempe, F. Mannozzi y D. Strle. "Tunable bandpass sigma delta modulator using one input parameter". Electronics Letters 39, n.º 2 (2003): 187. http://dx.doi.org/10.1049/el:20030146.

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Kim, Jae-Bung, Nam-Hee Yoo y Seong-Ik Cho. "Tunable Bandpass 4th Order SC Sigma-delta Modulator with Novel Structure". Transactions of The Korean Institute of Electrical Engineers 60, n.º 2 (1 de febrero de 2011): 446–50. http://dx.doi.org/10.5370/kiee.2011.60.2.446.

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Sobot, R., S. Stapleton y M. Syrzycki. "Tunable continuous-time bandpass /spl Sigma//spl Delta/ modulators with fractional delays". IEEE Transactions on Circuits and Systems I: Regular Papers 53, n.º 2 (febrero de 2006): 264–73. http://dx.doi.org/10.1109/tcsi.2005.857085.

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Witte, Pascal, John G. Kauffman, Joachim Becker y Maurits Ortmanns. "A Correlation-Based Background Error Estimation Technique for Bandpass Delta–Sigma ADC DACs". IEEE Transactions on Circuits and Systems II: Express Briefs 58, n.º 11 (noviembre de 2011): 748–52. http://dx.doi.org/10.1109/tcsii.2011.2168021.

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Molina-Salgado, Gerardo, Alonso Morgado, Gordana Jovanovic Dolecek y Jose M. de la Rosa. "LC-Based Bandpass Continuous-Time Sigma-Delta Modulators With Widely Tunable Notch Frequency". IEEE Transactions on Circuits and Systems I: Regular Papers 61, n.º 5 (mayo de 2014): 1442–55. http://dx.doi.org/10.1109/tcsi.2013.2289412.

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Raghavan, G., J. F. Jensen, J. Laskowski, M. Kardos, M. G. Case, M. Sokolich y S. Thomas. "Architecture, design, and test of continuous-time tunable intermediate-frequency bandpass delta-sigma modulators". IEEE Journal of Solid-State Circuits 36, n.º 1 (2001): 5–13. http://dx.doi.org/10.1109/4.896223.

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Maurino, R. y P. Mole. "A 200-MHz IF 11-bit fourth-order bandpass /spl Delta//spl Sigma/ ADC in SiGe". IEEE Journal of Solid-State Circuits 35, n.º 7 (julio de 2000): 959–67. http://dx.doi.org/10.1109/4.848204.

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Xu, Yang, Xinwang Zhang, Zhihua Wang y Baoyong Chi. "A Flexible Continuous-Time $\Delta \Sigma $ ADC With Programmable Bandwidth Supporting Low-Pass and Complex Bandpass Architectures". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, n.º 3 (marzo de 2017): 872–80. http://dx.doi.org/10.1109/tvlsi.2016.2611518.

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Kaplan, T. S., J. F. Jensen, C. H. Fields y M. C. F. Chang. "A 2-GS/s 3-bit /spl Delta//spl Sigma/-modulated DAC with tunable bandpass mismatch shaping". IEEE Journal of Solid-State Circuits 40, n.º 3 (marzo de 2005): 603–10. http://dx.doi.org/10.1109/jssc.2005.843708.

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Afifi, M., Y. Manoli y M. Keller. "A study of excess loop delay in tunable continuous-time bandpass delta–sigma modulators using RC-resonators". Analog Integrated Circuits and Signal Processing 79, n.º 3 (10 de abril de 2014): 555–68. http://dx.doi.org/10.1007/s10470-014-0294-0.

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Tesis sobre el tema "Tunable bandpass delta sigma ADC"

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Badran, Tamer. "Balayage de spectre utilisant les récepteurs radio logicielle". Electronic Thesis or Diss., Sorbonne université, 2020. https://accesdistant.sorbonne-universite.fr/login?url=https://theses-intra.sorbonne-universite.fr/2020SORUS264.pdf.

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L'architecture conventionnelle utilisée par toutes les publications précédentes pour le récepteur de balayage de spectre est basée sur le CAN en BB, donc il a une consommation d'énergie élevée, une complexité plus élevée et souffre d'inadéquations de circuits et de non-linéarité. Dans ce travail, nous proposons d'utiliser un récepteur RF basé sur CAN delta-sigma en PB. Les CAN PB DS ajustables précédemment signalés implémentée de manière complexe. Nous présentons une implémentation efficace du CAN PB DS accordable. Un récepteur de détection de spectre, basé sur l'architecture frontale RF à faible consommation d'énergie proposée dans cette thèse, est également proposé. Le récepteur complet proposé ne souffre pas d'un déséquilibre 1/Q. Les résultats de simulation pour montrer l'impact de la non-linéarité du circuit sur les performances sont présentés. Une implémentation de circuit d'un backend numérique du système proposé est présentée. Cette implémentation comprend un mélangeur à conversion descendante efficace, un filtre de décimation, un bloc FFT et un module de détection d'énergie. L'implémentation a été validée à l'aide l'outil SignalTab. Des études, ne présentent que des résultats analytiques ou de simulation, visant à montrer l'impact du déséquilibre 1/Q sur les performances de détection du spectre ont déjà été publiées. Dans ce travail, nous présentons la première mesure matérielle du déséquilibre I/Q sur les performances de détection du spectre. Dans le domaine médical, nous présentons pour la première fois une étude de l'effet de l'exposition aux RF-EMF sur les nouveau-nés via une acquisition simultanée de signaux RF et de paramètres physiologiques
Spectrum sensing applications cover wide variety, such as efficient utilization of frequency spectrum, and in medical applications. The conventional architecture used by all the previous publications for spectrum sensing receiver is based on baseband ADC, hence it has high power consumption, higher complexity, and suffers from circuit mismatches and nonlinearity. In this work, we propose using an RF receiver based on bandpass delta-sigma ADC. It is much more convenient to have a tunable BP ΔΣ ADC to simplify the spectrum sweeping task. The previously reported tunable BP ΔΣ ADC’s are implementing tunability in a complex manner. We present an efficient implementation of tunable BP ΔΣ ADC with fixed ratio between the sampling frequency and center frequency. That fixed ratio further simplifies the implementation of the down conversion mixer and decimation filter which serve as the digital backend of the receiver. A spectrum sensing receiver, based on the power-efficient RF front end architecture proposed in this thesis, is also proposed. The proposed complete receiver does not suffer from I/Q imbalance that highly affect the spectrum sensing performance. Simulation results to show the circuit nonlinearity impact on the performance are presented. A circuit implementation of a digital backend of the proposed system is presented. This implementation comprises an efficient down conversion mixer, decimation filter, custom FFT block, and energy detection module. The implementation was validated on Altera FPGA using the on-chip logic analyzer via the SignalTab tool.Studies to show the impact of I/Q imbalance on spectrum sensing performance were previously published. Nevertheless, those publications presented only either analytical or simulation results. In this work, we present the first hardware measurement of the I/Q imbalance on spectrum sensing performance using a commercial SDR transceiver platform.In the medical field, we also present for the first time a study of the effect of RF-EMF exposure on neonates by performing a simultaneous acquisition of RF signals along with recording the physiological parameters of neonates. Using R-Studio, the stationarity of the signals to be correlated was checked, a transformation was performed on the non-stationary signals. Finally, cross correlation between the acquired RF signal (average of the whole spectrum or in a specific band) and each of the recorded physiological parameters did not show an observable impact of RF-EMF exposure on neonates
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Svensson, Hanna. "Study on a second-order bandpass Σ∆-modulator for flexible AD-conversion". Thesis, Linköping University, Department of Electrical Engineering, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-12105.

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An important component in many communication system is the digital to analog converter. The component is needed in order to convert real world analog quantities to digital quantities which are easier to process. As the market for hand held devices with wireless communication with the outer world has increased new approaches for sharing the frequency spectrum are needed. Therefore it would be interesting to look at the possibility to design an analog to digital converter that, in runtime, can change the frequency band converted, and hence the used standard. This thesis study one of the possibilities to design such an ADC, as a Σ∆ modulator, and more precise the structure called Cascade of resonators with distributed feedback and input (CRFB). The order of the modulator in this study is two.

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McGinnis, Ryan Edward. "Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter". Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1152542196.

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Thandri, Bharath Kumar. "Design of RF/IF analog to digital converters for software radio communication receivers". Texas A&M University, 2003. http://hdl.handle.net/1969.1/5774.

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Software radio architecture can support multiple standards by performing analogto- digital (A/D) conversion of the radio frequency (RF) signals and running reconfigurable software programs on the backend digital signal processor (DSP). A slight variation of this architecture is the software defined radio architecture in which the A/D conversion is performed on intermediate frequency (IF) signals after a single down conversion. The first part of this research deals with the design and implementation of a fourth order continuous time bandpass sigma-delta (CT BP) C based on LC filters for direct RF digitization at 950 MHz with a clock frequency of 3.8 GHz. A new ADC architecture is proposed which uses only non-return to zero feedback digital to analog converter pulses to mitigate problems associated with clock jitter. The architecture also has full control over tuning of the coefficients of the noise transfer function for obtaining the best signal to noise ratio (SNR) performance. The operation of the architecture is examined in detail and extra design parameters are introduced to ensure robust operation of the ADC. Measurement results of the ADC, implemented in IBM 0.25 µm SiGe BiCMOS technology, show SNR of 63 dB and 59 dB in signal bandwidths of 200 kHz and 1 MHz, respectively, around 950 MHz while consuming 75 mW of power from ± 1.25 V supply. The second part of this research deals with the design of a fourth order CT BP ADC based on gm-C integrators with an automatic digital tuning scheme for IF digitization at 125 MHz and a clock frequency of 500 MHz. A linearized CMOS OTA architecture combines both cross coupling and source degeneration in order to obtain good IM3 performance. A system level digital tuning scheme is proposed to tune the ADC performance over process, voltage and temperature variations. The output bit stream of the ADC is captured using an external DSP, where a software tuning algorithm tunes the ADC parameters for best SNR performance. The IF ADC was designed in TSMC 0.35 µm CMOS technology and it consumes 152 mW of power from ± 1.65 V supply.
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Liu, Xuemei. "Design of a 125 mhz tunable continuous-time bandpass modulator for wireless IF applications". Texas A&M University, 2004. http://hdl.handle.net/1969.1/3257.

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Bandpass sigma-delta modulators combine oversampling and noise shaping to get very high resolution in a limited bandwidth. They are widely used in applications that require narrowband high-resolution conversion at high frequencies. In recent years interests have been seen in wireless system and software radio using sigma-delta modulators to digitize signals near the front end of radio receivers. Such applications necessitate clocking the modulators at a high frequency (MHz or above). Therefore a loop filter is required in continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime circuits (e.g., using switched capacitors) where the maximum clocking rate is limited by the bandwidth of Opamp, switch’s speed and settling-time of the circuitry. In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the modulator. The continuous-time loop filter is based on Gm-C resonators. A novel transconductance amplifier has been developed with high linearity at high frequency. Qfactor of filter is enhanced by tunable negative impedance which cancels the finite output impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal standard analog CMOS technology. Postlayout simulation in CADENCE demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1 MHz bandwidth. The modulator’s power consumption is 302 mW from supply power of ± 1.65V.
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6

Mariano, André Augusto. "Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications". Thesis, Bordeaux 1, 2008. http://www.theses.fr/2008BOR13644/document.

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La chaîne de réception des téléphones mobiles de dernière génération utilisent au moins deux étages de transposition en fréquence avant d'effectuer la démodulation en quadrature. La transposition en fréquence augmente la complexité du système et engendre de nombreux problèmes tels que la limitation de l'échelle dynamique et l'introduction de bruit issu de l'oscillateur local. Il est alors nécessaire d'envisager une numérisation du signal le plus près possible de l'antenne. Cette dernière permet la conversion directe d'un signal analogique en un signal numérique à des fréquences intermédiaires. Elle simplifie ainsi la conception globale du système et limite les problèmes liés aux mélangeurs. Pour cela, des architectures moins conventionnelles doivent être développées, comme la conversion analogique-numérique utilisant la modulation Sigma-Delta à temps continu. La modélisation comportementale de ce convertisseur analogique-numérique, ainsi que la conception des principaux blocs ont donc été l'objet de cette thèse. L'application d'une méthodologie de conception avancée, permettant la simulation mixte des blocs fonctionnels à différents niveaux d'abstraction, a permis de valider aussi bien la conception des circuits que le système global de conversion. En utilisant une architecture à multiples boucles de retour avec un quantificateur multi-bit, le convertisseur Sigma-Delta passe bande à temps continu atteint un rapport signal sur bruit (SNR) d'environ 76 dB dans une large bande de 20MHz
Wireless front-end receivers of last generation mobile devices operate at least two frequency translations before I/Q demodulation. Frequency translation increases the system complexity, introducing several problems associated with the mixers (dynamic range limitation, noise injection from the local oscillator, etc.). Herein, the position of the analog-to-digital interface in the receiver chain can play an important role. Moving the analog-to-digital converter (ADC) as near as possible to the antenna, permits to simplify the overall system design and to alleviate requirements associated with analog functions (filters, mixers). These currently requirements have led to a great effort in designing improved architectures as Continuous-Time Delta-Sigma ADCs. The behavioural modeling this converter, although the circuit design of the main blocks has been the subject of this thesis. The use of an advanced design methodology, allowing the mixed simulation at different levels of abstraction, allows to validate both the circuit design and the overall system conversion. Using a multi-feedback architecture associated with a multi-bit quantizer, the continuous-time Bandpass Delta-Sigma converter achieves a SNR of about 76 dB in a wide band of 20MHz
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Akram, Waqas. "Tunable mismatch shaping for bandpass Delta-Sigma data converters". Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-05-3575.

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Oversampled digital-to-analog converters typically employ an array of unit elements to drive out the analog signal. Manufacturing defects can create errors due to mismatch between the unit elements, leading to a sharp reduction in the effective dynamic range through the converter. Mismatch noise shaping is an established technique for alleviating these effects, but usually anchors the signal band to a fixed frequency location. In order to extend these advantages to tunable applications, this work explores a series of techniques that allow the suppression band of the mismatch noise shaping function to have an adjustable center frequency. The proposed techniques are implemented in hardware and evaluated according to mismatch shaping performance, latency and hardware complexity.
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Chang-Huan, Chen. "A Double Sampling Bandpass Delta-Sigma Modulator with Tunable Center Frequency". 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0002-1407200502291100.

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Chen, Chang-Huan y 陳昌煥. "A Double Sampling Bandpass Delta-Sigma Modulator with Tunable Center Frequency". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/80729274422072133405.

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碩士
淡江大學
電機工程學系碩士班
93
A Bandpass ∆Σ modulators are widely used in inter-mediate frequency (IF) and radio frequency (RF) communication systems. In order to avoid the low frequency noise in zero IF receiver and prevent the mismatch of the circuits from degrading the receiver performance, the single IF architecture is a good candidate. Since the signal, which is received and down-converted, may be varied due to process variations, a tunable bandpass ∆Σ modulator is required to improve the performance of the receiver. There are so many efforts are devoted in tunable continuous-time (CT) ∆Σ modulator by the modifying the transconductance of OTA in the resonator. However, an elaborate tuning scheme and an additional cost are demanded in the tunable continuous-time ∆Σ modulator. Since the mismatch among capacitors is very small, the SC ∆Σ modulators are popular in narrow band data converter. In this paper, a tunable bandpass ∆Σ modulator by one parameter only is adopted to optimize modulator performance. To achieve a tunable resonator in the modulator, a multiple path SC scheme is applied for the adjustments of the center frequency. A wide tuning range from 5MHz to 30MHz is preformed to demonstrate the flexibility of the modulator. Furthermore, a double sampling technique is used to relax the requirements of opamp performance. A tunable switched-capacitor (SC) bandpass delta sigma (∆Σ) modulator using double sampling by one input parameter is proposed. The center frequency of the modulator can be varied from 5MHz to 30MHz at a sampling frequency of 70MHz. Its performance can be hence improved by fine tuning the center frequency. The purposed modulator was implemented in 0.35-µm 2P4M CMOS standard technology with the core area of 2.8×1.5 mm2. The measured dynamic range of 68dB within 200 kHz bandwidth can be achieved. Its power consumption is 58mW under a 3.3-V supply voltage.
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Chalvatzis, Theodoros. "Tunable RF bandpass delta-sigma digital receivers with millimetre-wave sampling clocks". 2008. http://link.library.utoronto.ca/eir/EIRdetail.cfm?Resources__ID=742559&T=F.

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Actas de conferencias sobre el tema "Tunable bandpass delta sigma ADC"

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Flemming, Jesko, Bernhard Wicht y Pascal Witte. "Stability Analysis for Frequency Tunable Bandpass Delta-Sigma ADC Architectures". En 2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD). IEEE, 2023. http://dx.doi.org/10.1109/smacd58065.2023.10192145.

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Akram, Waqas y Earl E. Swartzlander. "Tunable mismatch shaping for quadrature bandpass delta-sigma data converters". En 2010 IEEE Workshop On Signal Processing Systems (SiPS). IEEE, 2010. http://dx.doi.org/10.1109/sips.2010.5624787.

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Sakr, Khaled, Mohamed Dessouky y Abd-El Halim Zekry. "Design of tunable continuous-time quadrature bandpass delta-sigma modulators". En 2011 IEEE 6th International Design and Test Workshop (IDT). IEEE, 2011. http://dx.doi.org/10.1109/idt.2011.6123110.

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Schreier, R., H. Shibata, P. Hendriks, M. Aliroteh, V. Kozlov, H. K. Tong, A. Del Muro et al. "An IF digitizer IC employing a continuous-time bandpass delta-sigma ADC". En 2012 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2012. http://dx.doi.org/10.1109/rfic.2012.6242291.

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Huang, Shu-Chuan y Chia-Te Fu. "A tunable SC bandpass delta-sigma modulator for multi-standard applications". En APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS). IEEE, 2008. http://dx.doi.org/10.1109/apccas.2008.4746230.

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Akram, Waqas y Earl E. Swartzlander. "Tunable N-path mismatch shaping for multibit bandpass delta-sigma modulators". En 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers. IEEE, 2009. http://dx.doi.org/10.1109/acssc.2009.5469938.

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Afifi, M., M. Keller, Y. Manoli y M. Ortmanns. "Excess loop delay compensation technique for tunable bandpass delta sigma modulators". En 2009 52nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2009. http://dx.doi.org/10.1109/mwscas.2009.5236078.

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Huang, Shu-Chuan y Ting-Yen Wang. "A tunable SC bandpass delta-sigma modulator with noise-coupled architecture". En 2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS). IEEE, 2011. http://dx.doi.org/10.1109/mwscas.2011.6026518.

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Guelaz, Rachid, Patricia Desgreys y Patrick Loumeau. "A sigma-delta bandpass ADC modelling in superconducting RSFQ technology with VHDL-AMS". En Design Languages (FDL). IEEE, 2008. http://dx.doi.org/10.1109/fdl.2008.4641427.

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Afifi, Mohamed, Ahmed Shahein, Michael Maurer, Matthias Keller y Yiannos Manoli. "A self calibration technique for tunable continuous-time bandpass delta-sigma modulators". En 2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012. IEEE, 2012. http://dx.doi.org/10.1109/iscas.2012.6271943.

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