Tesis sobre el tema "Technologies analogiques"
Crea una cita precisa en los estilos APA, MLA, Chicago, Harvard y otros
Consulte los 50 mejores tesis para su investigación sobre el tema "Technologies analogiques".
Junto a cada fuente en la lista de referencias hay un botón "Agregar a la bibliografía". Pulsa este botón, y generaremos automáticamente la referencia bibliográfica para la obra elegida en el estilo de cita que necesites: APA, MLA, Harvard, Vancouver, Chicago, etc.
También puede descargar el texto completo de la publicación académica en formato pdf y leer en línea su resumen siempre que esté disponible en los metadatos.
Explore tesis sobre una amplia variedad de disciplinas y organice su bibliografía correctamente.
Laurent, Joël. "Recherches expérimentales artistiques sur l'hybridation des technologies analogiques avec les technologies numériques tridimensionnelles : la vidéographie tridimensionnelle". Paris 8, 1997. http://www.theses.fr/1997PA081389.
Texto completoThe aim of this thesis is to provide matter for thought on using the three-dimensional computer graphic as a creative tool and give answers through experimentation. It is all about thinking and feeling about pictures differently, thanks to numeric technologies, so that the picture develops further into new directions. The film by the body of the earth, creation and procreation, produced during the past four years of research, uses the body as its sole material and is the basis of the whole thesis. A new strategy for creating images has been developed, which made possible the development of a new process of three-dimensional dynamic post-treatment of pictures: threedimensional video-graphics. This process is based on the hybridisation of analogous tecnologies with three-dimensional digital technologies (also based on hybridisation ). The aesthetics of hybradisation directs the three-dimensional computer graphic towards a dynamic art. Hybridisation therefore appears as a new way of thinking, doing, perceiving and finally, experiencing a picture
Filiol, Hubert. "Méthodes d'analyse de la variabilité et de conception robuste des circuits analogiques dans les technologies CMOS avancées". Phd thesis, Ecole Centrale de Lyon, 2010. http://tel.archives-ouvertes.fr/tel-00560610.
Texto completoJosse, Stève. "Transportabilité de fonctions analogiques en technologies CMOS submicroniques : application : contrôle du retard des fronts d'horloges d'un imageur CCD". Toulouse, INPT, 2003. http://www.theses.fr/2003INPT029H.
Texto completoMegherbi, Souhil. "Etude comparative de technologies silicium et arseniure de gallium. Application a la conception de circuits integres analogiques ultra-rapides. Conception d'un convertisseur analogique-numerique 3 bits, 1 gech/s". Paris 11, 1992. http://www.theses.fr/1992PA112046.
Texto completoParthasarathy, Chittoor Ranganathan. "Etude de la fiabilité des technologies CMOS avancées : application à la simulation de la fiabilité de conception des circuits numériques et analagiques". Aix-Marseille 1, 2006. http://www.theses.fr/2006AIX11057.
Texto completoBuffeteau, David. "Représentation et traitement des signaux analogiques dans le domaine temporel, pour répondre aux défis des technologies CMOS très avancées". Thesis, Université Grenoble Alpes (ComUE), 2018. http://www.theses.fr/2018GREAT105/document.
Texto completoAdvanced CMOS nodes trend to reduce the size of transistors hence reducing the power supply voltages and consequently available dynamics for the representation of analog signals. This work aims at proposing a data representation alternative which is usually done by an amplitude value. The chosen solution is to use a time-domain representation.In this thesis, we study both the use of a VCO-based ADC to convert an analog data into a time-domain one and a calculating method using data already encoded into the time domain.The three pillars of this thesis are a method to digitize a time-domain data so as to do more complex calculations, a method with a « residue extraction » allowing us to improve VCO-based ADCs performance in terms of resolution for a given bandwidth and an innovative architecture of a hybrid ADC which can adjust its operation switching between an asynchronous low-performance mode (which is a low power mode) and a synchronous high-performance mode (which is more energy consuming). The potential of these methods is pointed out by means of simulations that mimic the behavior of the 28 nm FDSOI CMOS technology
Roig, Fabien. "Etude et modélisation des effets de synergie issus de l’environnement radiatif spatial naturel et intentionnel sur les technologies bipolaires intégrées". Thesis, Montpellier 2, 2014. http://www.theses.fr/2014MON20205.
Texto completoThe space environment is a radiative concern that affects on board electronic systems, leading to failures. It is possible to distinguish two types of effects: the cumulative effects due to continuous deposition of energy throughout the space mission and the transient effects due to the single energetic particle crossing a sensitive area of the component or deposition of energy in a very short time in the specific context of an exo-atmospheric nuclear explosion. During qualification procedures for space mission, these effects are studied separately. However, the probability that they occur simultaneously in flight is significant. As a consequence, this work is about the study of the synergy between both cumulative and transient effects on various integrated bipolar technologies. The present results are used to provide some answers about potential changes of test methods. This work also evaluates the predictive capability of the previously developed model to reproduce accurately both the fast and the long lasting components of transients in circuitry and so to model transients' effects. This simulation methodology is extended to an operational amplifier from different manufacturers and for three different synergistic effects. The comparison between transients obtained experimentally during heavy ions, pulse laser and flash X experiments and the predicted transients validates the investigated methodology. The cumulative effects are taken into account by injecting the internal electrical parameters variations using irradiation exposure
VAUTRIN, Florent. "Contribution a l'optimisation des memoires analogiques rapides et bas bruit dans les technologies submicroniques. Application aux chaines d'acquisition des trajectometres de la physique des particules". Phd thesis, Université Louis Pasteur - Strasbourg I, 2000. http://tel.archives-ouvertes.fr/tel-00006340.
Texto completoVAUTRIN, FLORENT. "Contribution a l'optimisation des memoires analogiques rapides et bas bruit dans les technologies submicroniques. Application aux chaines d'acquisition des trajectometres de la physique des particules". Université Louis Pasteur (Strasbourg) (1971-2008), 2000. http://www.theses.fr/2000STR13199.
Texto completoLosch, Flora. "Technopolitiques post-coloniales : radiotélévisions, archives audiovisuelles et retour du passé en Afrique (XXe-XXIe siècles)". Electronic Thesis or Diss., Paris, EHESS, 2024. http://www.theses.fr/2024EHES0024.
Texto completoAt a time of debates on digital imperialism, the decolonization of heritage organizations, and the renewal of the relations between European and African states, this thesis seeks to survey a “slow-moving history” with lasting historiographic and cultural impacts: that of media technopolitics and of the accumulation of an audiovisual “documentary mass” by contemporary states.During the first 20th century, audiovisual technologies were introduced to Africa to serve imperial projects. Expanded to television during the decolonization, this techno-imperial investment was redeployed in the post-colonial context through cooperation between European and African states. Over the century, these technologies have generated a mass of analogue audiovisual archives. Produced exclusively by the former, and then by the latter after their independence, these archives are subject to obsolescence and destruction. Since the turn of the 21st century, they have been saved thanks to digital technologies, which radically change the terms and conditions of their preservation. Holding a monopoly on the continent’s audiovisual past, European states have assisted those of Africa, and this assistance, like that provided for their digital migration, forms part of the same post-colonial technopolitics.Lying at the intersection of relational histories, science studies, critical archival studies and critical heritage studies, this thesis reconstructs this puzzle using paper and audiovisual archives, semi-directive interviews and technical audits. It makes these media archives, which have remained outside of the reflection on the colonial archive and the “archive-subject”, an object of research in their own right. Centered on the analysis of the French imperial project and the agency of African actors, particularly in Côte d’Ivoire and Senegal, it consists of two volumes, the first of which, “Rewinding time to understand the collections (20th century)”, situates these archives in a long-term history. This volume studies the structuring of radio networks during the colonial period and their reconfiguration after the introduction of television and the coeval independence, post-1960 (part 1). By following two actors, it shows the intertwining of humans and non-humans in these socio-technical networks while also highlighting the polycentric nature of audiovisual technologies (part 2). By reconstructing the concomitant production of a legal instrument within UNESCO, it analyzes the standardization of audiovisual heritage preservation while retracing the first, now largely forgotten, debates on the restitution of the audiovisual heritage accumulated by the imperial states (part 3).These histories converge in the contemporary period, explored in the second volume “New issues in African audiovisual archives (21st century)”. This volume analyzes the implications of the change in the technical system on the audiovisual archives of the Ivorian and Senegalese public broadcasters and on the international preservation activity (part 4). Part 5 focuses on the reconfiguration of Franco-African cooperation and French investment in the safeguarding of African audiovisual archives. It also studies the African collections held on French territory, especially in the Institut national de l’audiovisuel, one of the main organizations holding African audiovisual past, bringing out the need for their restitution. At the end of these developments, it appears that the preservation activity is historically situated and a space where resources of the past, technologies, states, markets, knowledge and powers intermingle, this question being thus brought back into the field of politics
Joubert, Antoine. "Neurone analogique robuste et technologies émergentes pour les architectures neuromorphiques". Phd thesis, Université de Grenoble, 2013. http://tel.archives-ouvertes.fr/tel-00935178.
Texto completoBraham, Ahmed. "Simulateur analogique temps réel des systèmes électrotechniques : apport des nouvelles technologies". Toulouse, INPT, 1997. http://www.theses.fr/1997INPT012H.
Texto completoZhang, Ming. "Auto-compensation des dispersions technologiques dans les circuits integres analogiques cellulaires". Paris 11, 1994. http://www.theses.fr/1994PA112054.
Texto completoKLISNICK, GEOFFROY. "Etude et realisation en technologie cmos de circuits d'acquisition de signaux analogiques". Paris 6, 1995. http://www.theses.fr/1995PA066638.
Texto completoPiccin, Yohan. "Durcissement par conception d'ASIC analogiques". Thesis, Bordeaux, 2014. http://www.theses.fr/2014BORD0145/document.
Texto completoThe purpose of this thesis work is to investigate circuit design techniques to improve the robustness to Total Ionizing Dose (TID) of analog circuits within electronic systems embedded in space probes, satellites and vehicles. Such circuits often contain bipolartransistor components which are quite sensitive to cumulated radiation dose. However highly integrated CMOS technology has been shown to exhibit better natural TDI hardening.The approach proposed here is a hardening by design using a full CMOS semiconductor technology commercially available from ST Microelectronics calledHCMOS9A. The proposed generic hardening design methods will be seen to be compatibleand applicable to other existing or future process technologies. Furthermore this approach addresses the issue of ever-increasing development cost and access to hardened technologies.The first TID hardening technique proposed is applied to a full-CMOS voltage reference. This technique does not involve p-n junctions nor any particular layout precaution but instead is based on the subtraction of two different threshold voltages which allows the cancellation of TDI effects. While the use of advanced commercial CMOS technologies for specific radiation hardened applications is becoming more common, these technologies suffer from larger inputoffs et voltage drift than their bipolar transistor counterparts, which can impact system performance. The second technique studied is that of auto-zeroing, which is an efficient method to reduce the complex offset voltage drift mechanisms of operational amplifiers due to temperature. The purpose here is to prove that this technique can also cancel input offset voltage drift due to TID.Index term : hardening, cumulated dose, CMOS technology, voltage reference,operational amplifier
Gal, Stéphan. "Conception assistée de blocs analogiques pour capteurs intelligants". Montpellier 2, 1998. http://www.theses.fr/1998MON20230.
Texto completoTarabbia, Marc. "Caractérisation physico-chimique, simulation et modélisation d'une technologie analogique avancée BICMOS". Lyon, INSA, 1993. http://www.theses.fr/1993ISAL0003.
Texto completoThe goal of this study is to understand the physico-chemical phenomenon induced by the manufacturing of bipolar analogue integrated circuits. This study helps us to introduce new structures on the process flow. The electrical characteristics of new cells supply more freedom to designers and simplify the layout of circuits. The process modelization (SUPREM and SUPRA) and device simulation (SEDAN and PISCES) were done by improving default parameters and checking links between each of them. New steps introduce with in to process flow to make MOS structures were monitored by simulation. It checks the conservative basic bipolar cells performances. SIMS profiles and electrical measurements verify the simulation results. The feasibility of the integration of NMOS and PMOS on the bipolar process flow is done. We have introduce an isolated vertical PNP to simplify integrated circuit design and to get full complementary bipolar structures. Some process options remain to be defined
Premont, Christophe. "Etude et conception d'un composant analogique programmable en technologie CMOS standard". Lyon, INSA, 1998. http://www.theses.fr/1998ISAL0028.
Texto completoThis thesis is concerned with the study and the design of a field-programmable analogue array with a CMOS standard process. This circuit is an analogue cells based array. Each cell is programmable and can achieve various analogue functions with specific performance. Beside, the interconnections between the cells have to be programmable. The array configuration is achieved using a digital or an analogue interface circuitry to implement a particular function. For a flexible programmability and high-electrical performance, a new approach based and a transresistor amplifier using current conveyors have been developed to control full-differential transconductances. This report falls into six chapters. The first one deals with the concept of field programmable analogue array. The second chapter presents a methodology for describing analogue circuits. The array architecture is studied according to the requirements for such a programmable circuit. The main feature of the third chapter is to introduce the current-mode approach with the current conveyor. The fourth chapter presents the programmable analogue cell designed during the project. The structure of the analogue array and the proposed solutions are thoroughly described in the fifth chapter. The last chapter presents some application examples and it focuses on future works
Dong, Yan Hua. "Etude et realisation d'un convertisseur analogique-numerique rapide en technologie cmos". Rennes 1, 1988. http://www.theses.fr/1988REN10077.
Texto completoLlaser, Nicolas. "Interaction entre architecture et technologie pour la conception de cellules analogiques ultra-rapides". Paris 11, 1999. http://www.theses.fr/1999PA112152.
Texto completoAubert, Alain. "Contribution à la conception d'un circuit analogique programmable en technologie CMOS : conception et caractérisation d'une cellule de calcul analogique". Lyon, INSA, 2001. http://theses.insa-lyon.fr/publication/2001ISAL0074/these.pdf.
Texto completoThe development of an analogue application is long and often requires multiple iterations. However, electronics requires products with short time-to-market: short design and production cycle. In front of this challenge, the analogue designer is deprived of methodologies and tools contrary to the digital designer who benefits a broad range of programmable logic devices. This thesis exposes the contribution to the design of a programmable analogue circuit which integrates configurable cells for analogue computation targeting applications of sensor conditioning, carrying out operations of linearization. In most cases, the response curve of the sensor is not linear or the sensor conditioner introduces a non-linearity. This application is related to an industrial need with conditions of reduce cycle and development cost. After a state of the art in the field of analogue programmable devices both at the university level and the industrial level, the specifications of the required cell are exposed. The analogue computation cell must fulfill the functions of amplification, addition, substraction, multiplication, division and square root. This cell is completely differential at input and output. Thereafter, the cell of computation based on multipliers and inverting amplifiers, is described and characterised in simulation and experiment. The experimental characterisation highlights offsets, all related to problems of componant matching. This is why, a second cell was developed allowing to compensate for these offsets. Results show that the performances of the multiplier are improved in term of linearity and offset. Lastly, a network of eight computation cells was designed for the validation of the cell performances through the example of a resistive sensor linearization
Aubert, Alain Chante Jean-Pierre. "Contribution à la conception d'un circuit analogique programmable en technologie CMOS conception et caractérisation d'une cellule de calcul analogique /". Villeurbanne : Doc'INSA, 2005. http://docinsa.insa-lyon.fr/these/pont.php?id=aubert.
Texto completoLavaure, de Graffanaud Alain. "Conception de blocs analogiques et mixtes dédiés à un capteur intégré de rayonnement". Limoges, 2000. http://www.theses.fr/2000LIMO4044.
Texto completoLe, Bras Jean-Luc. "Contribution a l'étude des multiplicateurs de fréquence en ondes millimétriques. Application aux multiplicateurs en technologie quasi-optique". Brest, 1999. http://www.theses.fr/1999BRES2031.
Texto completoDoom, François. "Mise en oeuvre de la technologie HIGFET autoalignée sur GaAs pour applications analogiques hyperfréquences". Lille 1, 1998. https://pepite-depot.univ-lille.fr/LIBRE/Th_Num/1998/50376-1998-245.pdf.
Texto completoDarfeuille, Sébastien. "Conception de filtres actifs analogiques radiofréquences récursifs et channélisés en technologie monolithique BiCMOS Silicium". Limoges, 2006. https://aurore.unilim.fr/theses/nxfile/default/78642b46-a1bc-4f8d-92b0-add95991a926/blobholder:0/2006LIMO0001.pdf.
Texto completoThe main topic of this work is the design of original radiofrequency active filter topologies in Silicon BiCMOS technology. In a first part, the state of the art of the different existing integrated technologies is described. In a second part, we present the design of the two active filters based on recursive principles. The first circuit, non-tunable, uses a differential amplifier in order to achieve signal summation. The second circuit, based on a cellular approach of recursive filters, can be tuned independently in terms of gain, bandwidth and central frequency. In a third part, we propose two original solutions for the realisation of integrated reconfigurable channelized filters. With such topologies, and using low-order filters, excellent performances can be achieved in terms of selectivity thanks to the generation of transmission zeros
Sarkissian, Jean-Claude. "Analyse non linéaire de diviseurs de fréquences analogiques conçus en technologie monolithique. Comportement en bruit". Limoges, 1996. http://www.theses.fr/1996LIMO0050.
Texto completoLajmi, Rania. "Caractérisation et modélisation du vieillissement des circuits analogiques et RF en technologie 28 nm FDSOI". Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT088.
Texto completoReliability of analog and mixed signal circuits fabricated using complementary metaloxide semiconductor technologies in the deep-submicrometer technology nodes is significantly affected by process, voltage and temperature (PVT) variations. Degradationinduced due to aging mechanisms like bias temperature instability, hot carrier injection leads to additional challenges in design of reliable circuits. PVT variations and aging mechanisms together lead to lifetime degradation of device and circuit performance.There are many studies in the literature of the reliability of MOS transistors. Few studies have been conducted on the impact of their reliability on circuits.This research will study the impact of the deterioration of the MOS transistors on the performance of the developed circuits for analog and mixed applications (low dropout voltage regulator LDO, phase locked loop PLL, voltage controlled oscillator VCO, digital to analog converter CAN, power amplifier PA).Degradation lifetime induces the degradation of the threshold voltage and the drain. The surveys are conducted using aging simulations supporting models of aging mechanisms developed by our team and measurements of circuits implemented in 28nmFDSOI technology. Accelerated tests were used to evaluate the aging effect. Appropriate correction techniques for overcoming aging-induced degradation of circuit performance are proposed and studied.The DC and AC performances of LDO were analyzed before and after aging. The stress induces a degradation of these performances because of the effect of the mechanism of injection of hot carriers (HCI) on the transistors and the Matching induced in the pair of transistors responsible for the regulation. The LDO was oversized to avoid severe damage. A survey of the evolution of yield before and after aging was done using Mundea WICKED tool.The jitter noise and lock time of the PLL are not affected by aging and the PLL itself corrects any degradations and deviations of its output parameters. For this, an investigation of one of its important blocks, the VCO, was made. Measurement results at 125 ° C show that the oscillation frequency of the VCO has undergone significant degradation. While the relative phase noise has not been impacted.The aging effect on the digital analog converter SAR-ADC consisting of 16 TI-ADCs has occurred. Extraction of static and dynamic performances showed a significant degradation of the SNR. In order to identify the block responsible for this degradation, simulations of a single ADC were made. Aging has negligible impact on the switches while the comparator was identified as the most sensitive block. Aging impacts the time windows for each sub-block of the comparator which gives rise to a false decision of one of these blocks, hence a false signal at the output of the comparator, resulting in a code error and a degradation in the performance of the ADC.Investigation of the aging effect on the power amplifier has shown a significant degradation of the PA figures of merit under the effect of RF stress. These impairments are due to the degradation of transistor parameters such as transconductance gm and resistor rds. A solution for improving these degradations has been proposed. Based on the principle of detection and adaptive polarization, this technique makes it possible to change the polarization of the PA in order to bring the degraded performances to their fresh value.Based on this research, it is possible to conclude that the aging mechanisms of the 28nmFDSOI CMOS technology are not a major obstacle to the development of analogue and mixed signal systems. However, a careful analysis of the effects of aging at the circuit level, from the design phase, using the models developed at the transistor level and included in the simulators, is necessary.The incorporation of effective detection and performance enhancement solutions is possible for the implementation of extremely precise circuits
Youssef, Stéphanie. "Aide au concepteur pour la génération de masques analogiques, réutilisables et optimisés, en technologie CMOS nanométrique". Paris 6, 2012. http://www.theses.fr/2012PA066645.
Texto completoElectronics and semiconductor are evolving at an ever-increasing rate. New technologies are also introduced to extend CMOS into nano/molecular scale MOSFET structures. Tighter time-to-market needs are pressing the need for an automated reliable analog design flow. Automatic layout generation is a key ingredient of such flow whose design challenges are drastically exacerbated when more complex circuits and newer technologies must be hosted. The thesis presents a designer-assisted, reusable and optimized analog layout generation flow that addresses the challenges facing the automation of analog circuits. It is part of CHAMS project developed in LIP6. It has been developed in 3 phases. Firstly, we designed a library of analog Smart Devices that are parameterized, reusable, and with different layout styles. A generic language was used to describe these Devices to ease the technology migration and the layout-induced parameters calculation. Secondly, we developed the tools to generate the layout of complex circuits using the library of Smart Devices, the technology files and the designer's geometrical placement constraints needed to guarantee a certain performance. An intelligent topological representation was used to efficiently place the circuit modules given the designer's set of constraints. Thirdly, we created algorithms to optimize the layouts for different aspect ratios to minimize the area and the routing parasitic. In parallel the algorithm directly calculates and back-annotates the layout-dependent parasitic parameters. This work provides a reliable and efficient solution to allow a fast, optimized and parasitic effects-aware layout generation of complex analog circuits
Sebeloue, Martine. "Modélisation comportementale paramétrée de fonctions analogiques pour la simulation des systèmes de transmission, en technologie bipolaire". Toulouse, INPT, 2000. http://www.theses.fr/2000INPT014H.
Texto completoTourneur, Gilles. "Conception d'un convertisseur numerique analogique en technologie mos pour le traitement de signaux video". Rennes 1, 1996. http://www.theses.fr/1996REN10058.
Texto completoPrenat, Guillaume. "Conception d'une architecture de BIST analogique et mixte programmable en technologie CMOS très submicronique". Grenoble INPG, 2005. http://www.theses.fr/2005INPG0135.
Texto completoThis phd thesis presents a BIST technique for harmonic testing of Analogue and Mixed-Signal (AMS) circuits. The interface of the BIST is fully digital. This approach is aimed at facilitating low-cost test techniques for System-on-Chip (SoC) devices, rendering the test of mixed-signal cores compatible with the use of a low-cost digital tester. Analogue test signal generation is performed on-chip by low pass filtering a Sigma Delta encoded bit-stream. Analogue harmonic test response analysis is also performed on-chip using square wave modulation and Sigma Delta modulation. Since both analog signal generation and circuit under test response analysis are digitally programmable on-chip, compatibility with a low-cost digital tester is ensured. Optimisation of test signatures is discussed in detail as a trade-off between test time and test quality
Decoopman, Thibaut Vanbésien Olivier Lippens Didier. "Multiplicateurs de fréquences et métamatériaux en technologie finline". Villeneuve d'Ascq : Université des sciences et technologies de Lille, 2007. https://iris.univ-lille1.fr/dspace/handle/1908/517.
Texto completoN° d'ordre (Lille 1) : 3515. Titre provenant de la page de titre du document numérisé. Bibliogr. p. [213]-223. Liste des publications.
Ruby, Cédric. "Etude d'un composant analogique programmable destiné aux applications d'interfaces pour capteurs". Lyon, INSA, 2002. http://www.theses.fr/2002ISAL0109.
Texto completoAnalog counterpart of an FPGA, an FPAA can firstly simplify the development flow of analog resources, in order to reduce the time-to-market of electronic applications, and can secondly be a cost effective integration solution compared to the expensive ASIC technology. The goal of this study is to develop an FPAA realizing non-linear calculus operations for the applications of sensors interface. Two versions of an analog cell using two analog multipliers were developed and tested during this thesis. The first one permitted to highlight the requirement to control internal offsets; a study of the matching in the structure was then leaded and an offset cancellation scheme was designed; finally, improvements of the performances were achieved with the second version of the cell. Nevertheless, an automatic offset cancellation must be integrated within the FP AA, and such a study could conclude about the possible industrialization of this integrated circuit
Bernal, Olivier. "Conception de Convertisseurs Analogique-Numérique en technologie CMOS basse tension pour chaînes Vidéo CCD Spatiales". Phd thesis, Toulouse, INPT, 2006. http://oatao.univ-toulouse.fr/7495/1/bernal.pdf.
Texto completoAGON, FRANCOIS. "Etude d'une cellule universelle de conversion analogique-numerique par redistribution de charges en technologie cmos". Paris 6, 1995. http://www.theses.fr/1995PA066496.
Texto completoMorche, Dominique. "Conception de codeurs sigma-delta en technologie CMOS pour la conversion analogique-numérique haute résolution". Grenoble INPG, 1994. http://www.theses.fr/1994INPG0065.
Texto completoBernal, Olivier Lescure Marc. "Conception de convertisseurs analogique-numérique en technologie CMOS basse tension pour chaînes vidéo CCD spatiales". Toulouse : INP Toulouse, 2006. http://ethesis.inp-toulouse.fr/archive/00000349.
Texto completoWei, Zhaopeng. "Auto-polarisation de la grille arrière pour auto-calibration de cellules analogiques et mixtes en technologie UTBB-FDSOI". Thesis, Université Côte d'Azur (ComUE), 2019. http://www.theses.fr/2019AZUR4033.
Texto completoIn the competition of the miniaturization of integrated electronic circuits, UTBB-FDSOI technologies are better adapted to nanometric sizes, because they can limit the problems due to the random doping variations used in conventional “bulk” transistors and bring a significant improvement in terms of performance and low power design. This thesis is a contribution to the development of novel building blocks for PLL using complementary logic in 28nm UTBB-FDSOI technology. Using this technology, we proposed a complementary inverter based on a pair of back-gate cross-coupled inverters offering a fully symmetrical operation of complementary signals. This design concept can be extended to any digital cells to generate more stable, symmetrical and resilient output signals. First, we designed a fast and efficient ring oscillator composed by four complementary inverters delivering quadrature clocks which oscillation frequency is 7.3GHz. Then using complementary logic and back-gate control structure, we proposed an efficient solution to produce novel structures of VRCO, PFD, Charge pump, divisor etc., which are the key building blocks of high-speed low noise PLLs. All these designs have been simulated and verified using Cadence. Moreover, a test chip of RO, current mirror and VCRO have already been realized in silicon and tested
Gervais-Ducouret, Stéphane. "Etat de l'art de la technologie BiCMOS et de son utilisation : conception et optimisation de circuits analogiques BiCMOS". Bordeaux 1, 1994. http://www.theses.fr/1994BOR1A664.
Texto completoGervais-Ducouret, Stéphane. "Etat de l'art de la technologie BiCMOS et de son utilisation : conception et optimisation de circuits analogiques BiCMOS". Bordeaux 1, 1994. http://www.theses.fr/1994BOR10680.
Texto completoMas, Alexandre. "Convertisseur analogique-numérique large bande avec correction mixte". Thesis, Université Paris-Saclay (ComUE), 2018. http://www.theses.fr/2018SACLC054/document.
Texto completoData transmission requirements are ever more stringent, with respect to more throughput, less power consumption and reduced cost. The cable TV market is where broadband transceivers must continuously innovate to meet these requirements. In these transceivers, the analog front-end part must be adapted to meet the increasingly tighter specifications of the newest standards. A key bottleneck is the Analogto- Digital Converter (ADC), which must reach a sampling rate of several Gigasamples per second at effective conversion resolutions in the range of 10 to 14 bits. Among the possible choices, converters based on Time-Interleaving (TI-ADC) are experiencing remarkable growth, and today they appear to be the best candidates to rmeet the two constraints set out above. However, TI-ADCs are hampered by mismatches between its different conversion channels, which result in degraded performance due to the appearance of mismatch spurs in the frequency domain, arising both from static errors (gain and offset mismatch) and dynamic (skew and bandwidth) errors. To reduce these errors, we have investigated a mixeddomain calibration strategy for TI-ADCS in 28nm FDSOI technology. We strongly focused the analog compensation of dynamic errors. This report begins with a review of the state-of-theart w.r.t. the mismatch reduction and analog compensation techniques for both dynamic errors. Based on these results, we then introduce a variety of analog techniques aimed at compensating the bandwidth and skew mismatches. In order to compensate for the skew, we make the most of the FD-SOI technology by tightly regulating the voltage of the back gate of one or several sampling transistors. For the bandwidth error, we recommend that the T/H equivalent resistor be adjusted, adapting the on-resistor of the sampling transistors using up to five different techniques. Once the most appropriate skew and bandwidth compensations were identified, we ultimately implemented a mixed calibration of static and dynamic errors along with a digital calculation based upon the "Least- Squares" method
Decoopman, Thibaut. "Multiplicateurs de fréquences et métamatériaux en technologie finline". Lille 1, 2004. https://pepite-depot.univ-lille.fr/LIBRE/Th_Num/2004/50376-2004-127-128.pdf.
Texto completoBertrand, Géraldine. "Conception et modélisation électrique de structures de protection contre les décharges électrostatiques en technologies BICMOS et CMOS analogique". Toulouse, INSA, 2001. http://www.theses.fr/2001ISAT0037.
Texto completoThe sensitivity of modern integrated circuits to ElectroStatic Discharges (ESD) increases with the technology shrink and the introduction of new process techniques. To move towards a "first pass success", ESD must be taken into account at an early stage of a project development which requires capability to predict efficiency of ESD protection strategies. The availability of an ESD protection library including both optimized layouts and electrical models is part of the solution. However, ESD protection structures operate in avalanche breakdown and high current regimes, which cannot be simulated with standard SPICE models. In this thesis, a methodology to extend classical models to these regimes is first developed for the vertical bipolar NPN transistor widely used in BiCMOS technologies. This methodology is then applied to the NMOS transistor in an analog CMOS process, with the modeling of its parasitic lateral NPN transistor. Physics-based compact models are provided thanks to 2D device simulation, TLP characterization and photoemission experiments (EMMI)
DESGREZ, Simon. "Conception de diviseurs de fréquence analogiques réalisés en technologie monolithique à base de transistors pseudomorphiques à haute mobilité électronique". Phd thesis, Université Paul Sabatier - Toulouse III, 1997. http://tel.archives-ouvertes.fr/tel-00010077.
Texto completoDesgrez, Simon. "Conception de diviseurs de fréquence analogiques réalisés en technologie monomithique à base de transistors pseudomorphiques à haute mobilité électronique". Toulouse 3, 1997. http://www.theses.fr/1997TOU30138.
Texto completoBianchi, Raul-Andrés. "Techniques de conception des circuits intégrés analogiques pour des applications en haute température, en technologie sur substrat de silicium". Grenoble INPG, 1999. http://www.theses.fr/1999INPG0113.
Texto completoFreitas, Philippe. "Apports et limitations de la technologie MOS double grille à grilles à grilles indépendantes sub-45nm pour la conception analogique basse fréquence". Thesis, Bordeaux 1, 2009. http://www.theses.fr/2009BOR13987/document.
Texto completoThe aim of this thesis is to study the contributions and the limitations of Independently Driven Double Gate MOS transistors in regard of the low frequency analog design. This device is one of the candidates for the replacement of the current bulk MOS technology since the gate length of the transistors cannot be efficiently decreased under 30nm. Even if the IDGMOS technology is mainly designed for digital and radio frequency applications, the independent drive of the gates should also improve the design of analog circuits ant it would provide solutions to the future circuits issues. First, this work focuses upon the IDGMOS’s behaviour, going a little deeper into the effects of the coupling that exists between its interfaces. Using the electrical characteristics of the transistor and simplifying its model, this report then reviews the static and dynamic laws of the component in order to extract a simple description of its operation modes. Secondly, a state of the art concerning both the future environment and issues is presented, followed by the solutions which currently exist using the standard MOS technology. A brief comparison between an advanced MOS technology and an IDGMOS model fitted on the ITRS parameters is given. However, these ideal parameters prevent this work from establishing a practical conclusion whereas the aforementioned theoretical studies can be used for providing a better understanding of the IDGMOS contributions. Those are reviewed just before the last part of the report which presents some basic analog circuits and their enhancement using double gate transistors. This chapter first emphasizes each important aspect of the device operating within the circuits and it thus concludes on an interesting comparison between two complete low supply voltage amplifiers, the first one designed using IDGMOS transistors and the other one based on bulk driven MOS devices
Petit, Hervé. "Simulation comportementale pour la synthèse de convertisseurs analogique-numérique CMOS rapides". Phd thesis, Télécom ParisTech, 2004. http://pastel.archives-ouvertes.fr/pastel-00000868.
Texto completoPillet, Nicolas. "Conception et intégration de convertisseurs analogique/numérique, compacts, à bas bruit, adaptés aux capteurs CMOS destinés à la détection de particules chargées". Strasbourg, 2010. https://publication-theses.unistra.fr/public/theses_doctorat/2010/PILLET_Nicolas_2010.pdf.
Texto completoDevelopment of CMOS sensors has grown exponentially in the world of instrumentation in the past years because of their ability to integrate a sensitive element and the associated readout electronics on the same substrate at a low price. The CMOS-ILC team of IPHC has developed matrix of CMOS pixels for detectors used in particle physics for the last ten years. While using this kind of detectors for trajectometry, it could be interesting to raise the spatial resolution of the detectors. It could be fulfilled by implementing analog to digital converter (ADC) in the bottom of the column’s matrix. These ADCs must response to very strong constraint in term of dimension, conversion speed and power consumption. Three prototypes of ADCs with different architectures have been developed in order to respond to these specifications. The first one is a double numerical ramp ADC, the second one is a successive approximation ADC and the last one is an ADC with a progressive resolution. Three chips with these different architectures have been submitted and tested. The results have led to a comparison of the different technics in use in this particular field