Artículos de revistas sobre el tema "TCAD TOOL"
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Lee, YongJae. "Simulations of Proposed Shallow Trench Isolation using TCAD Tool". Journal of the Korea Society for Simulation 22, n.º 4 (31 de diciembre de 2013): 93–98. http://dx.doi.org/10.9709/jkss.2013.22.4.093.
Texto completoLandowski, Matthew M. y Z. John Shen. "TCAD Based Power Semiconductor Device e-Learning Tool". Journal of Power Electronics 10, n.º 6 (20 de noviembre de 2010): 643–46. http://dx.doi.org/10.6113/jpe.2010.10.6.643.
Texto completoSakai, Atsushi, Katsumi Eikyu, Kenichi Hisada, Yasuhiro Yamashita, Koichi Arai, Hiroyuki Arie, Yutaka Akiyama y Tomohiro Yamashita. "Inverse Modeling of 4H-SiC Trench Gate MOSFETs Validated with Electrical and Physical Characterization". Materials Science Forum 963 (julio de 2019): 609–12. http://dx.doi.org/10.4028/www.scientific.net/msf.963.609.
Texto completoRuey-Sing Wei y A. Sangiovanni-Vincentelli. "PLATYPUS: A PLA Test Pattern Generation Tool". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, n.º 4 (octubre de 1986): 633–44. http://dx.doi.org/10.1109/tcad.1986.1270233.
Texto completoHongmei Li, C. E. Zemke, G. Manetas, V. I. Okhmatovski, E. Rosenbaum y A. C. Cangellaris. "An automated and efficient substrate noise analysis tool". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, n.º 3 (marzo de 2006): 454–68. http://dx.doi.org/10.1109/tcad.2005.854628.
Texto completoRiente, Fabrizio, Giovanna Turvani, Marco Vacca, Massimo Ruo Roch, Maurizio Zamboni y Mariagrazia Graziano. "ToPoliNano: A CAD Tool for Nano Magnetic Logic". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, n.º 7 (julio de 2017): 1061–74. http://dx.doi.org/10.1109/tcad.2017.2650983.
Texto completoOikonomakos, P. y M. Zwolinski. "An Integrated High-Level On-Line Test Synthesis Tool". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, n.º 11 (noviembre de 2006): 2479–91. http://dx.doi.org/10.1109/tcad.2006.882120.
Texto completoTulunay, GÜlin y Sina Balkir. "A Synthesis Tool for CMOS RF Low-Noise Amplifiers". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, n.º 5 (mayo de 2008): 977–82. http://dx.doi.org/10.1109/tcad.2008.917579.
Texto completoAbderehman, Mohammed, Rupak Gupta, Rakesh Reddy Theegala y Chandan Karfa. "BLAST: Belling the Black-Hat High-Level Synthesis Tool". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 41, n.º 11 (noviembre de 2022): 3661–72. http://dx.doi.org/10.1109/tcad.2022.3200513.
Texto completoKuznetsov, Maksim, Sergey Kalinin, Alexey Cherkaev y Dmitriy Ostertak. "Investigating physical model interface in the TCAD Sentaurus environment". Transaction of Scientific Papers of the Novosibirsk State Technical University, n.º 3 (18 de noviembre de 2020): 39–48. http://dx.doi.org/10.17212/2307-6879-2020-3-39-48.
Texto completoIbrahim, Walid, Valeriu Beiu y Azam Beg. "GREDA: A Fast and More Accurate Gate Reliability EDA Tool". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, n.º 4 (abril de 2012): 509–21. http://dx.doi.org/10.1109/tcad.2011.2176123.
Texto completoKagaris, Dimitri. "MOTO-X: A Multiple-Output Transistor-Level Synthesis CAD Tool". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, n.º 1 (enero de 2016): 114–27. http://dx.doi.org/10.1109/tcad.2015.2448675.
Texto completoPantho, Jubaer Hossain y Christophe Bobda. "MeXT-SE: A Design Tool to Transparently Generate Secure MPSoC". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, n.º 11 (noviembre de 2020): 3799–808. http://dx.doi.org/10.1109/tcad.2020.3012651.
Texto completoTao, Nick G. M., Bo-Rong Lin, Chien-Ping Lee, Tim Henderson y Barry J. F. Lin. "Study on mechanisms of InGaP/GaAs HBT safe operating area using TCAD simulation". International Journal of Microwave and Wireless Technologies 7, n.º 3-4 (10 de abril de 2015): 279–85. http://dx.doi.org/10.1017/s1759078715000495.
Texto completoShih, Hsiu-Chuan, Pei-Wen Luo, Jen-Chieh Yeh, Shu-Yen Lin, Ding-Ming Kwai, Shih-Lien Lu, Andre Schaefer y Cheng-Wen Wu. "DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, n.º 9 (septiembre de 2014): 1356–69. http://dx.doi.org/10.1109/tcad.2014.2323203.
Texto completoSZCZESNY, ROMUALD y MIECZYSLAW RONKOWSKI. "MODELING AND SIMULATION OF CONVERTER SYSTEMS PART II: SIMULATION PACKAGE TCAD". Journal of Circuits, Systems and Computers 05, n.º 04 (diciembre de 1995): 669–97. http://dx.doi.org/10.1142/s0218126695000400.
Texto completoLouris, E., D. Stefanakis, G. Priniotakis, L. Van Langenhove y D. Tassis. "Optimization of cylindrical textile organic field effect transistors using TCAD simulation tool". IOP Conference Series: Materials Science and Engineering 254 (octubre de 2017): 162006. http://dx.doi.org/10.1088/1757-899x/254/16/162006.
Texto completoMamidipaka, M., K. Khouri, N. Dutt y M. Abadir. "IDAP: A Tool for High-Level Power Estimation of Custom Array Structures". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, n.º 9 (septiembre de 2004): 1361–69. http://dx.doi.org/10.1109/tcad.2004.833609.
Texto completoTseng, Tsun-Ming, Mengchu Li, Daniel Nestor Freitas, Travis McAuley, Bing Li, Tsung-Yi Ho, Ismail Emre Araci y Ulf Schlichtmann. "Columba 2.0: A Co-Layout Synthesis Tool for Continuous-Flow Microfluidic Biochips". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, n.º 8 (agosto de 2018): 1588–601. http://dx.doi.org/10.1109/tcad.2017.2760628.
Texto completoMohanachandran Nair, Sarath, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Fazal Hameed y Mehdi B. Tahoori. "VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, n.º 7 (julio de 2018): 1396–407. http://dx.doi.org/10.1109/tcad.2017.2760861.
Texto completoRouying Zhan, Haigang Feng, Qiong Wu, Haolu Xie, Xiaokang Guan, Guang Chen y A. Z. H. Wang. "Esdextractor: a new technology-independent cad tool for arbitrary esd protection device extraction". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, n.º 10 (octubre de 2003): 1362–70. http://dx.doi.org/10.1109/tcad.2003.818140.
Texto completoMichez, A., S. Dhombres y J. Boch. "ECORCE: A TCAD Tool for Total Ionizing Dose and Single Event Effect Modeling". IEEE Transactions on Nuclear Science 62, n.º 4 (agosto de 2015): 1516–27. http://dx.doi.org/10.1109/tns.2015.2449281.
Texto completoBiagetti, G., S. Orcioni, C. Turchetti, P. Crippa y M. Alessandrini. "SiSMA—A Tool for Efficient Analysis of Analog CMOS Integrated Circuits Affected by Device Mismatch". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, n.º 2 (febrero de 2004): 192–207. http://dx.doi.org/10.1109/tcad.2003.822131.
Texto completoHazra, Aritra, Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Kevin M. Harer, Ansuman Banerjee y Subhankar Mukherjee. "POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, n.º 11 (noviembre de 2013): 1801–13. http://dx.doi.org/10.1109/tcad.2013.2267454.
Texto completoAkopyan, Filipp, Jun Sawada, Andrew Cassidy, Rodrigo Alvarez-Icaza, John Arthur, Paul Merolla, Nabil Imam et al. "TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, n.º 10 (octubre de 2015): 1537–57. http://dx.doi.org/10.1109/tcad.2015.2474396.
Texto completoViale, Benjamin y Bruno Allard. "Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits—Part II". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, n.º 10 (octubre de 2020): 3107–17. http://dx.doi.org/10.1109/tcad.2019.2962119.
Texto completoViale, Benjamin y Bruno Allard. "Scalable and Versatile Design Guidance Tool for the ESD Robustness of Integrated Circuits - Part I". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, n.º 10 (octubre de 2020): 3067–80. http://dx.doi.org/10.1109/tcad.2019.2962120.
Texto completoSeiculescu, Ciprian, Srinivasan Murali, Luca Benini y Giovanni De Micheli. "SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, n.º 12 (diciembre de 2010): 1987–2000. http://dx.doi.org/10.1109/tcad.2010.2061610.
Texto completoUsha, C. y Palanichamy Vimala. "Analytical Drain Current Model for Fully Depleted Surrounding Gate TFET". Journal of Nano Research 55 (noviembre de 2018): 75–81. http://dx.doi.org/10.4028/www.scientific.net/jnanor.55.75.
Texto completoZhan, R., H. Feng, Q. Wu, H. Xie, X. Guan, G. Chen y A. Z. H. Wang. "ESDInspector: A New Layout-Level ESD Protection Circuitry Design Verification Tool Using a Smart-Parametric Checking Mechanism". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, n.º 10 (octubre de 2004): 1421–28. http://dx.doi.org/10.1109/tcad.2004.833613.
Texto completoDuan, B. h., C. Xiong, L. Zhong, C. Zeng y J. h. Xiong. "Simulation of 14 MeV neutron-induced SEU in SRAM". Journal of Instrumentation 18, n.º 02 (1 de febrero de 2023): T02003. http://dx.doi.org/10.1088/1748-0221/18/02/t02003.
Texto completoLiu, Manwen, Wenzheng Cheng, Zheng Li, Zhenyang Zhao y Zhihua Li. "3D Simulation, Electrical Characteristics and Customized Manufacturing Method for a Hemispherical Electrode Detector". Sensors 22, n.º 18 (9 de septiembre de 2022): 6835. http://dx.doi.org/10.3390/s22186835.
Texto completoChen, Jing, Yufeng Guo, Jun Zhang, Jianhua Liu, Qing Yao, Jiafei Yao, Maolin Zhang y Man Li. "Off-State Performance Characterization of an AlGaN/GaN Device via Artificial Neural Networks". Micromachines 13, n.º 5 (5 de mayo de 2022): 737. http://dx.doi.org/10.3390/mi13050737.
Texto completoDargar, Shashi Kant, J. K. Srivastava, Santosh Bharti y Abha Nyati. "Performance Evaluation of GaN based Thin Film Transistor using TCAD Simulation". International Journal of Electrical and Computer Engineering (IJECE) 7, n.º 1 (1 de febrero de 2017): 144. http://dx.doi.org/10.11591/ijece.v7i1.pp144-151.
Texto completoSirakoulis, G. Ch, I. Karafyllidis y A. Thanailakis. "A TCAD tool for the simulation of the CVD process based on cellular automata". Le Journal de Physique IV 11, PR3 (agosto de 2001): Pr3–205—Pr3–212. http://dx.doi.org/10.1051/jp4:2001326.
Texto completoKUMARI, RITI, MANISH GOSWAMI y B. R. SINGH. "THE IMPACT OF CHANNEL ENGINEERING ON SHORT CHANNEL BEHAVIOR OF NANO FIN-FETs". International Journal of Nanoscience 11, n.º 02 (abril de 2012): 1250021. http://dx.doi.org/10.1142/s0219581x12500214.
Texto completoKim, Ki Yeong, Joo Seok Noh, Tae Young Yoon y Jang Hyun Kim. "Improvement in Turn-Off Loss of the Super Junction IGBT with Separated n-Buffer Layers". Micromachines 12, n.º 11 (19 de noviembre de 2021): 1422. http://dx.doi.org/10.3390/mi12111422.
Texto completoSharma, Sanjeev Kumar, Jeetendra Singh, Balwinder Raj y Mamta Khosla. "Analysis of Barrier Layer Thickness on Performance of In1–xGaxAs Based Gate Stack Cylindrical Gate Nanowire MOSFET". Journal of Nanoelectronics and Optoelectronics 13, n.º 10 (1 de octubre de 2018): 1473–77. http://dx.doi.org/10.1166/jno.2018.2374.
Texto completoJiang, Yi Fan, B. Jayant Baliga y Alex Q. Huang. "Influence of Lateral Straggling of Implated Aluminum Ions on High Voltage 4H-SiC Device Edge Termination Design". Materials Science Forum 924 (junio de 2018): 361–64. http://dx.doi.org/10.4028/www.scientific.net/msf.924.361.
Texto completoOthman, Nurul Aida Farhana, Sharidya Rahman, Sharifah Fatmadiana Wan Muhamad Hatta, Norhayati Soin, Brahim Benbakhti y Steven Duffy. "Design optimization of the graded AlGaN/GaN HEMT device performance based on material and physical dimensions". Microelectronics International 36, n.º 2 (1 de abril de 2019): 73–82. http://dx.doi.org/10.1108/mi-09-2018-0057.
Texto completoJayachandran, Remya, Dhanaraj Jagalchandran y Perinkolam Chidambaram Subramaniam. "Planar CMOS and multigate transistors based wide-band OTA buffer amplifiers for heavy resistance load". Facta universitatis - series: Electronics and Energetics 35, n.º 1 (2022): 13–28. http://dx.doi.org/10.2298/fuee2201013j.
Texto completoVimala, Palanichamy y N. R. Nithin Kumar. "Comparative Analysis of Various Parameters of Tri-Gate MOSFET with High-K Spacer". Journal of Nano Research 56 (febrero de 2019): 119–30. http://dx.doi.org/10.4028/www.scientific.net/jnanor.56.119.
Texto completoMasalsky, Nikolae V. "Simulation of the characteristics of low-voltage gates on combined cylindrical surrounding gate field-effect nanotransistors". Radioelectronics. Nanosystems. Information Technologies. 13, n.º 4 (29 de diciembre de 2021): 449–56. http://dx.doi.org/10.17725/rensit.2021.13.449.
Texto completoElpelt, Rudolf, Bernd Zippelius, Stefan Doering y Uwe Winkler. "Employing Scanning Spreading Resistance Microscopy (SSRM) for Improving TCAD Simulation Accuracy of Silicon Carbide". Materials Science Forum 897 (mayo de 2017): 295–98. http://dx.doi.org/10.4028/www.scientific.net/msf.897.295.
Texto completoMorozzi, A., M. Hoffmann, R. Mulargia, S. Slesazeck y E. Robutti. "Negative capacitance devices: sensitivity analyses of the developed TCAD ferroelectric model for HZO". Journal of Instrumentation 17, n.º 01 (1 de enero de 2022): C01048. http://dx.doi.org/10.1088/1748-0221/17/01/c01048.
Texto completoZhou, Kai, Songming Miao, Xuanze Zhou, Guangwei Xu, Lingfei Wang y Shibing Long. "A core drain current model for β-Ga2O3 power MOSFETs based on surface potential". AIP Advances 13, n.º 1 (1 de enero de 2023): 015202. http://dx.doi.org/10.1063/5.0134215.
Texto completoItalia, Markus, Ioannis Deretzis, Alfio Nastasi, Silvia Scalese, Antonino La Magna, Massimo Pirnaci, Daniele Pagano, Dario Tenaglia y Patrizia Vasquez. "Multiscale Simulations of Plasma Etching in Silicon Carbide Structures". Materials Science Forum 1062 (31 de mayo de 2022): 214–18. http://dx.doi.org/10.4028/p-n9v122.
Texto completoSubash, T. D., T. Gnanasekaran, J. Jagannathan y C. Divya. "Relative Analysis of GaAs, InSb, InP Using QWFET". Advanced Materials Research 984-985 (julio de 2014): 1080–84. http://dx.doi.org/10.4028/www.scientific.net/amr.984-985.1080.
Texto completoYang, Shao-Ming, Gene Sheu, Tzu Chieh Lee, Ting Yao Chien, Chieh Chih Wu y Yun Jung Lin. "Design of a Low on Resistance High Voltage (120V) Novel 3D NLDMOS with Side Isolation Based on 0.35um BCD Process Technology". MATEC Web of Conferences 201 (2018): 02004. http://dx.doi.org/10.1051/matecconf/201820102004.
Texto completoTang, Zhao Huan, Bin Wang, Jia Nan Wang y Kai Zhou Tan. "Use N+ Buried Layer to Design a Low On-Resistance VDMOS". Advanced Materials Research 756-759 (septiembre de 2013): 4267–70. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.4267.
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