Artículos de revistas sobre el tema "TCAD Design"
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Bellini, Marco y Lars Knoll. "Advanced TCAD Design Techniques for the Performance Improvement of SiC MOSFETs". Materials Science Forum 1004 (julio de 2020): 865–71. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.865.
Texto completoJohannesson, Daniel, Muhammad Nawaz y Hans Peter Nee. "TCAD Model Calibration of High Voltage 4H-SiC Bipolar Junction Transistors". Materials Science Forum 963 (julio de 2019): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.963.670.
Texto completoRehman, Atta Ur, Amna Siddiqui, Muhammad Nadeem y Muhammad Usman. "Improved PERC Solar Cell Design by TCAD Simulation". Proceedings of the Pakistan Academy of Sciences: A. Physical and Computational Sciences 58, n.º 4 (28 de marzo de 2022): 61–67. http://dx.doi.org/10.53560/ppasa(58-4)637.
Texto completoPan, Zijin, Cheng Li, Mengfu Di, Feilong Zhang y Albert Wang. "3D TCAD Analysis Enabling ESD Layout Design Optimization". IEEE Journal of the Electron Devices Society 8 (2020): 1289–96. http://dx.doi.org/10.1109/jeds.2020.3027034.
Texto completoWoo, Sola, Juhee Jeon y Sangsig Kim. "Prediction of Device Characteristics of Feedback Field-Effect Transistors Using TCAD-Augmented Machine Learning". Micromachines 14, n.º 3 (21 de febrero de 2023): 504. http://dx.doi.org/10.3390/mi14030504.
Texto completoSingh, Vivek. "Relevance of technology computer aided design (TCAD) to process-aware design". Journal of Micro/Nanolithography, MEMS, and MOEMS 1, n.º 3 (1 de octubre de 2002): 290. http://dx.doi.org/10.1117/1.1508411.
Texto completoChen, Yu-Guang, Hui Geng, Kuan-Yu Lai, Yiyu Shi y Shih-Chieh Chang. "Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 33, n.º 4 (abril de 2014): 507–18. http://dx.doi.org/10.1109/tcad.2013.2293881.
Texto completoWang, Ke, Haodong Jiang, Yiming Liao, Yue Xu, Feng Yan y Xiaoli Ji. "Degradation Prediction of GaN HEMTs under Hot-Electron Stress Based on ML-TCAD Approach". Electronics 11, n.º 21 (2 de noviembre de 2022): 3582. http://dx.doi.org/10.3390/electronics11213582.
Texto completoMa, Qiang y Evangeline F. Y. Young. "Multivoltage Floorplan Design". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, n.º 4 (abril de 2010): 607–17. http://dx.doi.org/10.1109/tcad.2010.2042895.
Texto completoNandi, Prajit, Hirak Talukdar, Dhiraj Kumar y Ashvin Kumar G. Katakwar. "A Novel Approach to Design SAR-ADC: Design Partitioning Method". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, n.º 3 (marzo de 2016): 346–56. http://dx.doi.org/10.1109/tcad.2015.2474379.
Texto completoPotbhare, Siddharth, Akin Akturk, Neil Goldsman, James M. McGarrity y Anant Agarwal. "Modeling and Design of High Temperature Silicon Carbide DMOSFET Based Medium Power DC-DC Converter". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (1 de enero de 2010): 000144–51. http://dx.doi.org/10.4071/hitec-spotbhare-tp22.
Texto completoKwon, Hyoungcheol, Hyunsuk Huh, Hwiwon Seo, Songhee Han, Imhee Won, Jiwoong Sue, Dongyean Oh et al. "TCAD augmented generative adversarial network for hot-spot detection and mask-layout optimization in a large area HARC etching process". Physics of Plasmas 29, n.º 7 (julio de 2022): 073504. http://dx.doi.org/10.1063/5.0093076.
Texto completoHu, Shiyan, Xiaobo Sharon Hu y Albert Y. Zomaya. "Guest Editorial Leveraging Design Automation Techniques for Cyber-Physical System Design". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35, n.º 5 (mayo de 2016): 697–98. http://dx.doi.org/10.1109/tcad.2016.2548179.
Texto completoVeneris, A. y M. S. Abadir. "Design rewiring using ATPG". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21, n.º 12 (diciembre de 2002): 1469–79. http://dx.doi.org/10.1109/tcad.2002.804388.
Texto completoKagalwalla, Abde Ali, Puneet Gupta, Christopher J. Progler y Steve McDonald. "Design-Aware Mask Inspection". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, n.º 5 (mayo de 2012): 690–702. http://dx.doi.org/10.1109/tcad.2011.2181909.
Texto completoKahng, A. B., Seokhyeong Kang, R. Kumar y J. Sartori. "Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31, n.º 3 (marzo de 2012): 404–17. http://dx.doi.org/10.1109/tcad.2011.2172610.
Texto completoLudwig, Tobias, Joakim Urdahl, Dominik Stoffel y Wolfgang Kunz. "Properties First—Correct-By-Construction RTL Design in System-Level Design Flows". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 39, n.º 10 (octubre de 2020): 3093–106. http://dx.doi.org/10.1109/tcad.2019.2921319.
Texto completoChen, H. M., I. M. Liu y M. D. F. Wong. "I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, n.º 11 (noviembre de 2006): 2552–56. http://dx.doi.org/10.1109/tcad.2006.873900.
Texto completoFanshu Jiao, Sergio Montano, Cristian Ferent, Alex Doboli y Simona Doboli. "Analog Circuit Design Knowledge Mining: Discovering Topological Similarities and Uncovering Design Reasoning Strategies". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, n.º 7 (julio de 2015): 1045–58. http://dx.doi.org/10.1109/tcad.2015.2418287.
Texto completoBrisk, Philip, Suman Chakraborty, Claudionor Coelho, Abdoulaye Gamatie, Swaroop Ghosh y Xun Jiao. "TCAD EIC Message: February 2019". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 38, n.º 2 (febrero de 2019): 197–98. http://dx.doi.org/10.1109/tcad.2018.2890315.
Texto completoRazdan, R. y A. Strojwas. "A Statistical Design Rule Developer". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, n.º 4 (octubre de 1986): 508–20. http://dx.doi.org/10.1109/tcad.1986.1270222.
Texto completoKane, R. y S. Sahni. "A Systolic Design-Rule Checker". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, n.º 1 (enero de 1987): 22–32. http://dx.doi.org/10.1109/tcad.1987.1270242.
Texto completoGnudi, A., P. Ciampolini, R. Guerrieri, M. Rudan y G. Baccarani. "Sensitivity Analysis for Device Design". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, n.º 5 (septiembre de 1987): 879–85. http://dx.doi.org/10.1109/tcad.1987.1270330.
Texto completoDe Smedt, B. y G. G. E. Gielen. "Watson: design space boundary exploration and model generation for analog and RF IC design". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, n.º 2 (febrero de 2003): 213–24. http://dx.doi.org/10.1109/tcad.2002.806598.
Texto completoDobre, Sorin Adrian, Andrew B. Kahng y Jiajia Li. "Design Implementation With Noninteger Multiple-Height Cells for Improved Design Quality in Advanced Nodes". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37, n.º 4 (abril de 2018): 855–68. http://dx.doi.org/10.1109/tcad.2017.2731679.
Texto completoTao, Nick G. M., Bo-Rong Lin, Chien-Ping Lee, Tim Henderson y Barry J. F. Lin. "Study on mechanisms of InGaP/GaAs HBT safe operating area using TCAD simulation". International Journal of Microwave and Wireless Technologies 7, n.º 3-4 (10 de abril de 2015): 279–85. http://dx.doi.org/10.1017/s1759078715000495.
Texto completoDash, T. P., S. Dey, S. Das, J. Jena, E. Mahapatra y C. K. Maiti. "Source/Drain Stressor Design for Advanced Devices at 7 nm Technology Node". Nanoscience & Nanotechnology-Asia 10, n.º 4 (26 de agosto de 2020): 447–56. http://dx.doi.org/10.2174/2210681209666190809101307.
Texto completoPangrle, B. M. y D. D. Gajski. "Design Tools for Intelligent Silicon Compilation". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, n.º 6 (noviembre de 1987): 1098–112. http://dx.doi.org/10.1109/tcad.1987.1270350.
Texto completoYongseok Cheon y M. D. F. Wong. "Design hierarchy-guided multilevel circuit partitioning". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, n.º 4 (abril de 2003): 420–27. http://dx.doi.org/10.1109/tcad.2003.809659.
Texto completoQiang Xu y N. Nicolici. "Multifrequency TAM design for hierarchical SOCs". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, n.º 1 (enero de 2006): 181–96. http://dx.doi.org/10.1109/tcad.2005.852440.
Texto completoCheng, Lei y Martin D. F. Wong. "Floorplan Design for Multimillion Gate FPGAs". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, n.º 12 (diciembre de 2006): 2795–805. http://dx.doi.org/10.1109/tcad.2006.882481.
Texto completoJaffari, J. y M. Anis. "Variability-Aware Bulk-MOS Device Design". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27, n.º 2 (febrero de 2008): 205–16. http://dx.doi.org/10.1109/tcad.2007.907234.
Texto completoChen, Yibin, Sean Safarpour, Joao Marques-Silva y Andreas Veneris. "Automated Design Debugging With Maximum Satisfiability". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 29, n.º 11 (noviembre de 2010): 1804–17. http://dx.doi.org/10.1109/tcad.2010.2061270.
Texto completoPan, David Z., Bei Yu y Jhih-Rong Gao. "Design for Manufacturing With Emerging Nanolithography". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 32, n.º 10 (octubre de 2013): 1453–72. http://dx.doi.org/10.1109/tcad.2013.2276751.
Texto completoSpoto, J. P., W. T. Coston y C. Paul Hernandez. "Statistical Integrated Circuit Design and Characterization". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, n.º 1 (enero de 1986): 90–103. http://dx.doi.org/10.1109/tcad.1986.1270180.
Texto completoKung-Chao Chu, J. P. Fishburn, P. Honeyman y Y. E. Lien. "A Database-Driven VLSI Design System". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, n.º 1 (enero de 1986): 180–87. http://dx.doi.org/10.1109/tcad.1986.1270185.
Texto completoChang, Wanli, Dip Goswami, Samarjit Chakraborty, Lei Ju, Chun Jason Xue y Sidharta Andalam. "Memory-Aware Embedded Control Systems Design". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 36, n.º 4 (abril de 2017): 586–99. http://dx.doi.org/10.1109/tcad.2016.2613933.
Texto completoPhung, L. V., D. Planson, P. Brosselard, D. Tournier y C. Brylinski. "3D TCAD Simulations for More Efficient SiC Power Devices Design". ECS Transactions 58, n.º 4 (31 de agosto de 2013): 331–39. http://dx.doi.org/10.1149/05804.0331ecst.
Texto completoKuruvilla, Nisha. "National Workshop on Advanced Nanoscale Device Design Using TCAD [Chapters]". IEEE Solid-State Circuits Magazine 8, n.º 4 (2016): 94–95. http://dx.doi.org/10.1109/mssc.2016.2601525.
Texto completoLim, Wee Han, Amy L. Ziebell, Iwan Cornelius, Mark I. Reinhard, Dale A. Prokopovich, Andrew S. Dzurak y Anatoly B. Rosenfeld. "Cylindrical Silicon-on-Insulator Microdosimeter: Design, Fabrication and TCAD Modeling". IEEE Transactions on Nuclear Science 56, n.º 2 (abril de 2009): 424–28. http://dx.doi.org/10.1109/tns.2009.2013467.
Texto completoBoufouss, E., J. Alvarado y D. Flandre. "Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM". Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, HITEC (1 de enero de 2010): 000077–82. http://dx.doi.org/10.4071/hitec-eboufouss-ta25.
Texto completoIshikawa, M., T. Matsuda, T. Yoshimura y S. Goto. "Compaction-Based Custom LSI Layout Design Method". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, n.º 3 (mayo de 1987): 374–82. http://dx.doi.org/10.1109/tcad.1987.1270282.
Texto completoModarres, H. y R. J. Lomax. "A Formal Approach to Design-Rule Checking". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 6, n.º 4 (julio de 1987): 561–73. http://dx.doi.org/10.1109/tcad.1987.1270303.
Texto completoWisniewski, M. Y. L., E. Yashchin, R. L. Franch, D. P. Conrady, D. N. Maynard, G. Fiorenza y I. C. Noyan. "The physical design of on-chip interconnections". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22, n.º 3 (marzo de 2003): 254–76. http://dx.doi.org/10.1109/tcad.2002.807881.
Texto completoCaldwell, A. E., H. J. Choi, A. B. Kahng, S. Mantik, M. Potkonjak, G. Qu y J. L. Wong. "Effective Iterative Techniques for Fingerprinting Design IP". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, n.º 2 (febrero de 2004): 208–15. http://dx.doi.org/10.1109/tcad.2003.822126.
Texto completoRyu, K. K. y V. J. MooneyIII. "Automated Bus Generation for Multiprocessor SoC Design". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23, n.º 11 (noviembre de 2004): 1531–49. http://dx.doi.org/10.1109/tcad.2004.835119.
Texto completoAuge, I., F. Petrot, F. Donnet y P. Gomez. "Platform-based design from parallel C specifications". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, n.º 12 (diciembre de 2005): 1811–26. http://dx.doi.org/10.1109/tcad.2005.852431.
Texto completoAgarwal, K., M. Agarwal, D. Sylvester y D. Blaauw. "Statistical interconnect metrics for physical-design optimization". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, n.º 7 (julio de 2006): 1273–88. http://dx.doi.org/10.1109/tcad.2005.855954.
Texto completoWang, G., S. Sivaswamy, C. Ababei, K. Bazargan, R. Kastner y E. Bozorgzadeh. "Statistical Analysis and Design of HARP FPGAs". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, n.º 10 (octubre de 2006): 2088–102. http://dx.doi.org/10.1109/tcad.2005.859485.
Texto completoDrinic, Milenko, Darko Kirovski, Seapahn Megerian y Miodrag Potkonjak. "Latency-Guided On-Chip Bus-Network Design". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25, n.º 12 (diciembre de 2006): 2663–73. http://dx.doi.org/10.1109/tcad.2006.882488.
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