Literatura académica sobre el tema "SUB MICRON TECHNOLOGIES"
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Artículos de revistas sobre el tema "SUB MICRON TECHNOLOGIES"
DESPOTULI, ALEXANDER y ALEXANDRA ANDREEVA. "A SHORT REVIEW ON DEEP-SUB-VOLTAGE NANOELECTRONICS AND RELATED TECHNOLOGIES". International Journal of Nanoscience 08, n.º 04n05 (agosto de 2009): 389–402. http://dx.doi.org/10.1142/s0219581x09006328.
Texto completoYamazaki, T., K. Imai, H. Yoshida, Y. Kinoshita y H. Suzuki. "Process integration technologies for sub-half micron BiCMOS LSls". Electrical Engineering 79, n.º 5 (octubre de 1996): 329–33. http://dx.doi.org/10.1007/bf01235873.
Texto completoBude, J. D. y M. Mastrapasqua. "Impact ionization and distribution functions in sub-micron nMOSFET technologies". IEEE Electron Device Letters 16, n.º 10 (octubre de 1995): 439–41. http://dx.doi.org/10.1109/55.464810.
Texto completoManolopoulos, Spyros, K. Mathieson y R. Turchetta. "Simulation of monolithic active pixels in deep sub-micron technologies". Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 487, n.º 1-2 (julio de 2002): 181–87. http://dx.doi.org/10.1016/s0168-9002(02)00963-4.
Texto completoBoyes, E. D. "LVEDS For Advanced Materials and Semiconductor Technologies". Microscopy and Microanalysis 5, S2 (agosto de 1999): 314–15. http://dx.doi.org/10.1017/s1431927600014896.
Texto completoDuruk, Alper, Ece Olcay Güneş y Hakan Kuntman. "A new low voltage CMOS differential OTRA for sub-micron technologies". AEU - International Journal of Electronics and Communications 61, n.º 5 (mayo de 2007): 291–99. http://dx.doi.org/10.1016/j.aeue.2006.05.009.
Texto completoKaloyeros, Alain E. y Michael A. Fury. "Chemical Vapor Deposition of Copper for Multilevel Metallization". MRS Bulletin 18, n.º 6 (junio de 1993): 22–29. http://dx.doi.org/10.1557/s0883769400047291.
Texto completoBude, Jeff D. "Monte Carlo Simulations of Impact Ionization Feedback in MOSFET Structures". VLSI Design 8, n.º 1-4 (1 de enero de 1998): 13–19. http://dx.doi.org/10.1155/1998/10649.
Texto completoVishnoi, U. y T. G. Noll. "Area- and energy-efficient CORDIC accelerators in deep sub-micron CMOS technologies". Advances in Radio Science 10 (18 de septiembre de 2012): 207–13. http://dx.doi.org/10.5194/ars-10-207-2012.
Texto completoGul, Waqas, Maitham Shams y Dhamin Al-Khalili. "SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview". Micromachines 13, n.º 8 (17 de agosto de 2022): 1332. http://dx.doi.org/10.3390/mi13081332.
Texto completoTesis sobre el tema "SUB MICRON TECHNOLOGIES"
Oey, James Boe-Kian 1980. "Cell-based array for deep sub-micron technologies". Thesis, Massachusetts Institute of Technology, 2003. http://hdl.handle.net/1721.1/18030.
Texto completoIncludes bibliographical references (p. 161).
In this thesis I explore transistor topologies for high density cell-based arrays that allows for dense computation blocks, small memory cells, and strong signal drivers. This involves simulating different circuit types with HSPICE to determine ideal transistor sizes. Using Magic and the results of the HSPICE simulations, I explore transistor topologies with different ratios of nFets to pFets. An analysis on the technology shows important characteristics for digital systems and how they relate to the explored transistor topologies.
by James Boe-Kian Oey.
M.Eng.
Sotiriadis, Paul Peter P. (Paul Peter Peter-Paul) 1973. "Interconnect modeling and optimization in deep sub-micron technologies". Thesis, Massachusetts Institute of Technology, 2002. http://hdl.handle.net/1721.1/29230.
Texto completoIncludes bibliographical references.
Interconnect will be a major bottleneck for deep sub-micron technologies in the years to come. This dissertation addresses the communication aspect from a power consumption and transmission speed perspective. A model for the energy consumption associated with data transmission through deep sub-micron technology buses is derived. The capacitive and inductive coupling between the bus lines as well as the distributed nature of the wires is taken into account. The model is used to estimate the power consumption of the bus as a function of the Transition Activity Matrix, a quantity generalizing the transition activity factors of the individual lines. An information theoretic framework has been developed to study the relation between speed (number of operations per time unit) and energy consumption per operation in the case of synchronous digital systems. The theory provides us with the fundamental minimum energy per input information bit that is required to process or communicate information at a certain rate. The minimum energy is a function of the information rate, and it is, in theory, asymptotically achievable using coding. This energy-information theory combined with the bus energy model result in the derivation of the fundamental performance limits of coding for low power in deep sub-micron buses. Although linear, block linear and differential coding schemes are favorable candidates for error correction, it is shown that they only increase power consumption in buses. Their resulting power consumption is related to structural properties of their generator matrices. In some cases the power is calculated exactly and in other cases bounds are derived.
(cont.) Both provide intuition about how to re-structure a given linear (block linear, etc.) code so that the energy is minimized within the set of all equivalent codes. A large class of nonlinear coding schemes is examined that leads to significant power reduction. This class contains all encoding schemes that have the form of connected Finite State Machines. The deep sub-micron bus energy model is used to evaluate their power reduction properties. Mathematical analysis of this class of coding schemes has led to the derivation of two coding optimization algorithms. Both algorithms derive efficient coding schemes taking into account statistical properties of the data and the particular structure of the bus. This coding design approach is generally applicable to any discrete channel with transition costs. For power reduction, a charge recycling technique appropriate for deep sub-micron buses is developed. A detailed mathematical analysis provides the theoretical limits of power reduction. It is shown that for large buses power can be reduced by a factor of two. An efficient modular circuit implementation is presented that demonstrates the practicality of the technique and its significant net power reduction. Coding for speed on the bus is introduced. This novel idea is based on the fact that coupling between the lines in a deep sub-micron bus implies that different transitions require different amounts of time to complete. By allowing only "fast" transitions to take place, we can increase the clock frequency of the bus. The combinatorial capacity of such a constrained bus ...
by Paul Peter P. Sotiriadis.
Ph.D.
Xu, Hao. "Runtime Leakage Control in Deep Sub-micron CMOS Technologies". University of Cincinnati / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1289235760.
Texto completoHenzler, Stephan. "Power management of digital circuits in deep sub-micron CMOS technologies /". [New York, NY] : Springer, 2007. http://www.gbv.de/dms/ilmenau/toc/511998031.PDF.
Texto completoSANT, LUCA. "Design of MEMS microphone front-ends in deep sub-micron CMOS technologies". Doctoral thesis, Università degli Studi di Milano-Bicocca, 2022. http://hdl.handle.net/10281/374735.
Texto completoMicrophone systems are extremely widespread in today's consumer electronics, the urge of a more natural interaction with our devices has heavily pushed voice recognition even in portable devices, forcing industry to create suitable products. This thesis describes the development of a new digital read-out ASIC that paired with Infineon Technologies latest sealed-dual membrane (SDM) MEMS transducer forms a prototype for a new high-end microphone product. State-of-the-art noise performance is achieved thanks to significant optimizations both on the MEMS as well as on the ASIC side. The ASIC features an unconventional read-out amplifier based on a power-scalable current-feedback architecture as well as a reconfigurable ΔΣ modulator allowing to trade-off signal-to-noise ratio (SNR) versus power consumption. The microphone system achieves an SNR of 72dB(A) supporting an acoustical overload point (AOP) of 130dB SPL. This represents a significant improvement to current state-of-the-art digital microphones.
Fuard, david. "Etude et caractérisation avancées des procédés plasma pour les technologies sub - 0.1 µm". Phd thesis, Université d'Orléans, 2003. http://tel.archives-ouvertes.fr/tel-00006610.
Texto completoGreenup, Phillip John. "Development of Novel Technologies for Improved Natural Illumination of High Rise Office Buildings". Thesis, Queensland University of Technology, 2004. https://eprints.qut.edu.au/15936/1/Philip_Greenup_Thesis.pdf.
Texto completoGreenup, Phillip John. "Development of Novel Technologies for Improved Natural Illumination of High Rise Office Buildings". Queensland University of Technology, 2004. http://eprints.qut.edu.au/15936/.
Texto completoIlle, Adrien. "Fiabilité des oxydes de grille ultra-minces sous décharges électrostatiques dans les technologies CMOS fortement sub-microniques". Phd thesis, Université de Provence - Aix-Marseille I, 2008. http://tel.archives-ouvertes.fr/tel-00407545.
Texto completoFleury, Dominique. "Contribution à l'étude expérimentale du transport dans les transistors de dimensions déca-nanométriques des technologies CMOS sub-45nm". Phd thesis, Grenoble INPG, 2009. http://tel.archives-ouvertes.fr/tel-00461948.
Texto completoLibros sobre el tema "SUB MICRON TECHNOLOGIES"
Power management of digital circuits in deep sub-micron CMOS technologies. [Dordrecht]: Springer, 2007.
Buscar texto completoCharles, Miller. Microcomputer and LAN security =: La sécurité des micro-ordinateurs et des réseaux locaux. Hull, Qué: Minister of Government Services Canada = Ministre des services gouvernementaux Canada, 1993.
Buscar texto completoHenzler, Stephan. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies. Henzler Stephan, 2010.
Buscar texto completoPower Management of Digital Circuits in Deep Sub-Micron CMOS Technologies. Springer Netherlands, 2006. http://dx.doi.org/10.1007/1-4020-5081-x.
Texto completoHenzler, Stephan. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies. Springer, 2006.
Buscar texto completoHenzler, Stephan. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies. Springer, 2007.
Buscar texto completoCapítulos de libros sobre el tema "SUB MICRON TECHNOLOGIES"
Packan, P. "Simulating Deep Sub-Micron Technologies: An Industrial Perspective". En Simulation of Semiconductor Devices and Processes, 34–41. Vienna: Springer Vienna, 1995. http://dx.doi.org/10.1007/978-3-7091-6619-2_8.
Texto completoYe, Yan y Lin Sen Chen. "Light Guide Plate Based on Sub-Micron Gratings". En Optics Design and Precision Manufacturing Technologies, 1061–65. Stafa: Trans Tech Publications Ltd., 2007. http://dx.doi.org/10.4028/0-87849-458-8.1061.
Texto completoJose, Philip C., S. Karthikeyan, K. Batri y S. Sivanantham. "An Efficient Algorithm for Tracing Minimum Leakage Current Vector in Deep-Sub Micron Circuits". En Advanced Computing and Communication Technologies, 59–69. Singapore: Springer Singapore, 2016. http://dx.doi.org/10.1007/978-981-10-1023-1_6.
Texto completoTing, Chia Jen, Hung Yin Tsai y Chang Pin Chou. "Fabrication of Large-Area Imprint Mold with High-Aspect-Ratio Nanotip Arrays of Sub-Micron Diameter". En Optics Design and Precision Manufacturing Technologies, 607–12. Stafa: Trans Tech Publications Ltd., 2007. http://dx.doi.org/10.4028/0-87849-458-8.607.
Texto completoJavaheri, Reza y Reza Sedaghat. "A Novel Delay Fault Testing Methodology for Resistive Faults in Deep Sub-micron Technologies". En Communications in Computer and Information Science, 653–60. Berlin, Heidelberg: Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-89985-3_80.
Texto completovan Gurp, J. F. C., Marcel Tichem y U. Staufer. "Design, Fabrication and Testing of Assembly Features for Enabling Sub-micron Accurate Passive Alignment of Photonic Chips on a Silicon Optical Bench". En Precision Assembly Technologies and Systems, 17–27. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-28163-1_3.
Texto completoHerkersdorf, Andreas, Michael Engel, Michael Glaß, Jörg Henkel, Veit B. Kleeberger, Johannes M. Kühn, Peter Marwedel et al. "RAP Model—Enabling Cross-Layer Analysis and Optimization for System-on-Chip Resilience". En Dependable Embedded Systems, 1–27. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-52017-5_1.
Texto completoReczek, W. y H. Terletzki. "Zuverlässigkeitsaspekte Dynamischer Speicher in Sub-Micron CMOS Technologie". En Mikroelektronik 89, 267–72. Vienna: Springer Vienna, 1989. http://dx.doi.org/10.1007/978-3-7091-9073-9_38.
Texto completoYang, Xiaoliang, Xuequan Wang, Zhe Pan, Jie Liu y Jiandong Luo. "Preliminary Application of CT Technology in Non-destructive Testing of Nuclear Fuel Elements". En Springer Proceedings in Physics, 98–106. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-1023-6_10.
Texto completoBehjati, Mohammadreza y John Cosmas. "Self-Organizing Network Solutions". En Advances in Wireless Technologies and Telecommunication, 241–53. IGI Global, 2017. http://dx.doi.org/10.4018/978-1-5225-2342-0.ch011.
Texto completoActas de conferencias sobre el tema "SUB MICRON TECHNOLOGIES"
Krishna, R. S. S. M. R. y Ashis Kumar Mal. "Performance analysis of parallel adders in sub-micron and deep sub-micron technologies". En 2016 International Conference on Microelectronics, Computing and Communications (MicroCom). IEEE, 2016. http://dx.doi.org/10.1109/microcom.2016.7522464.
Texto completoBooth, Heather. "Techniques and Applications of Laser Micro-Processing at the Micron and Sub-Micron Level". En Photonic Applications Systems Technologies Conference. Washington, D.C.: OSA, 2006. http://dx.doi.org/10.1364/phast.2006.pwb2.
Texto completoChueng, Kwang-Ting, Sujit Dey, Mike Rodgers y Kaushik Roy. "Test challenges for deep sub-micron technologies". En the 37th conference. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/337292.337353.
Texto completoLiou, Fu-Tai. "Manufacturing challenges for sub-half-micron technologies". En Microelectronic Manufacturing '95, editado por Anant G. Sabnis y Ivo J. Raaijmakers. SPIE, 1995. http://dx.doi.org/10.1117/12.221320.
Texto completoLiou, Fu-Tai. "Manufacturing challenges for sub-half-micron technologies". En Microelectronic Manufacturing '95. SPIE, 1995. http://dx.doi.org/10.1117/12.221435.
Texto completoLiou, Fu-Tai. "Manufacturing challenges for sub-half micron technologies". En Microelectronic Manufacturing '95, editado por Ih-Chin Chen, Girish A. Dixit, Trung T. Doan y Nobuo Sasaki. SPIE, 1995. http://dx.doi.org/10.1117/12.221147.
Texto completoLiou, Fu-Tai. "Manufacturing challenges for sub-half micron technologies". En Microelectronic Manufacturing '95, editado por John K. Lowell, Ray T. Chen y Jagdish P. Mathur. SPIE, 1995. http://dx.doi.org/10.1117/12.221210.
Texto completoKittl, Jorge A., Michael A. Gribelyuk, Donald Miles, Chih-Ping Chao, Mark Rodder, Qi-Zhong Hong, Hong Yang, Sunil Hattangady y Ning Yu. "Salicide Technologies for Deep-Sub-Micron-CMOS". En 1998 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1998. http://dx.doi.org/10.7567/ssdm.1998.a-7-1.
Texto completoBecht, J. G. M., B. A. Bauer, P. J. van der Put, J. Schoonman y B. Scarlett. "Laser Excited Synthesis Of Sub-Micron Powders". En Laser Technologies in Industry. SPIE, 1988. http://dx.doi.org/10.1117/12.968919.
Texto completoFino, Maria. "Modeling High Frequency VCOs for Sub-micron Technologies". En 2006 International Caribbean Conference on Devices, Circuits and Systems. IEEE, 2006. http://dx.doi.org/10.1109/iccdcs.2006.250879.
Texto completoInformes sobre el tema "SUB MICRON TECHNOLOGIES"
Coyner, Kelley y Jason Bittner. Automated Vehicles and Infrastructure Enablers: Electrification. 400 Commonwealth Drive, Warrendale, PA, United States: SAE International, diciembre de 2022. http://dx.doi.org/10.4271/epr2022029.
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