Artículos de revistas sobre el tema "Spacers gate"
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Weng, Chun Jen. "Etching Effects of Nanotechnology Fabrication on CMOS Transistor Gate Wafer Manufacturing Process Integration". Advanced Materials Research 154-155 (octubre de 2010): 938–41. http://dx.doi.org/10.4028/www.scientific.net/amr.154-155.938.
Texto completoWeng, Chun Jen. "Etching Process Effects of CMOS Transistor Gate Manufacturing Nanotechnology Fabrication Integration". Applied Mechanics and Materials 83 (julio de 2011): 91–96. http://dx.doi.org/10.4028/www.scientific.net/amm.83.91.
Texto completoWylie, Ian W. y N. Garry Tarr. "A new approach to gate/n− overlapped lightly doped drain structures: added gate after implantation of n− (AGAIN)". Canadian Journal of Physics 69, n.º 3-4 (1 de marzo de 1991): 174–76. http://dx.doi.org/10.1139/p91-027.
Texto completoKumar, Padakanti Kiran, Bukya Balaji y Karumuri Srinivasa Rao. "Design and analysis of asymmetrical low-k source side spacer halo doped nanowire metal oxide semiconductor field effect transistor". International Journal of Electrical and Computer Engineering (IJECE) 13, n.º 3 (1 de junio de 2023): 3519. http://dx.doi.org/10.11591/ijece.v13i3.pp3519-3529.
Texto completoWostyn, Kurt, Karine Kenis, Hans Mertens, Adrian Vaisman Chasin, Andriy Hikavyy, Frank Holsteyns y Naoto Horiguchi. "Low Temperature SiGe Steam Oxide - Aqueous Hf and NH3/NF3 Remote Plasma Etching and its Implementation as Si GAA Inner Spacer". Solid State Phenomena 282 (agosto de 2018): 126–31. http://dx.doi.org/10.4028/www.scientific.net/ssp.282.126.
Texto completoGuo, Mengxue, Weifeng Lü, Ziqiang Xie, Mengjie Zhao, Weijie Wei y Ying Han. "Effects of Symmetric and Asymmetric Double-Layer Spacers on a Negative-Capacitance Nanosheet Field-Effect Transistor". Journal of Nanoelectronics and Optoelectronics 17, n.º 6 (1 de junio de 2022): 873–82. http://dx.doi.org/10.1166/jno.2022.3266.
Texto completoDurfee, Curtis, Ivo Otto IV, Subhadeep Kal, Shanti Pancharatnam, Matthew Flaugh, Toshiki Kanaki, Matthew Rednor et al. "Epi Source-Drain Damage Mitigation During Channel Release of Stacked Nanosheet Gate-All-Around Transistors". ECS Transactions 112, n.º 1 (29 de septiembre de 2023): 45–52. http://dx.doi.org/10.1149/11201.0045ecst.
Texto completoConvertino, Clarissa, Cezar Zota, Heinz Schmid, Daniele Caimi, Marilyne Sousa, Kirsten Moselund y Lukas Czornomaz. "InGaAs FinFETs Directly Integrated on Silicon by Selective Growth in Oxide Cavities". Materials 12, n.º 1 (27 de diciembre de 2018): 87. http://dx.doi.org/10.3390/ma12010087.
Texto completoLi, Junjie, Yongliang Li, Na Zhou, Wenjuan Xiong, Guilei Wang, Qingzhu Zhang, Anyan Du et al. "Study of Silicon Nitride Inner Spacer Formation in Process of Gate-all-around Nano-Transistors". Nanomaterials 10, n.º 4 (20 de abril de 2020): 793. http://dx.doi.org/10.3390/nano10040793.
Texto completoBacquié, Valentin, Aurélien Tavernier, François Boulard, Olivier Pollet y Nicolas Possémé. "Gate spacers etching of Si3N4 using cyclic approach for 3D CMOS devices". Journal of Vacuum Science & Technology A 39, n.º 3 (mayo de 2021): 033005. http://dx.doi.org/10.1116/6.0000871.
Texto completoKalarickal, Nidhin Kurian, Ashok Dheenan, Joe F. McGlone, Sushovan Dhara, Mark Brenner, Steven A. Ringel y Siddharth Rajan. "Demonstration of self-aligned β-Ga2O3 δ-doped MOSFETs with current density >550 mA/mm". Applied Physics Letters 122, n.º 11 (13 de marzo de 2023): 113506. http://dx.doi.org/10.1063/5.0131996.
Texto completoNarula, Mandeep Singh y Archana Pandey. "Performance Evaluation of Stacked Gate Oxide/High K Spacers Based Gate All Around Device Architectures at 10 nm Technology Node". Silicon 14, n.º 5 (20 de enero de 2022): 2397–407. http://dx.doi.org/10.1007/s12633-022-01685-9.
Texto completoGu, Jie, Qingzhu Zhang, Zhenhua Wu, Jiaxin Yao, Zhaohao Zhang, Xiaohui Zhu, Guilei Wang et al. "Cryogenic Transport Characteristics of P-Type Gate-All-Around Silicon Nanowire MOSFETs". Nanomaterials 11, n.º 2 (26 de enero de 2021): 309. http://dx.doi.org/10.3390/nano11020309.
Texto completoMo, Fabrizio, Chiara Elfi Spano, Yuri Ardesi, Massimo Ruo Roch, Gianluca Piccinini y Marco Vacca. "NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance". Electronics 12, n.º 6 (21 de marzo de 2023): 1487. http://dx.doi.org/10.3390/electronics12061487.
Texto completoHsieh, C. S., P. C. Kao, C. S. Chiu, C. H. Hon, C. C. Fan, W. C. Kung, Z. W. Wang y E. S. Jeng. "NVM Characteristics of Single-MOSFET Cells Using Nitride Spacers With Gate-to-Drain NOI". IEEE Transactions on Electron Devices 51, n.º 11 (noviembre de 2004): 1811–17. http://dx.doi.org/10.1109/ted.2004.836796.
Texto completoLiu, Peng, Chuncheng Xie, Feng Zhang, Jianguo Chen y Dongmin Chen. "Elimination of Gate Leakage in GaN FETs by Placing Oxide Spacers on the Mesa Sidewalls". IEEE Electron Device Letters 34, n.º 10 (octubre de 2013): 1232–34. http://dx.doi.org/10.1109/led.2013.2278013.
Texto completovan Dam, D. B., M. P. J. Peeters, C. J. Curling, R. Schroeders y M. A. Verschuuren. "Application of Printable Electronics for LCD Manufacturing: Printing of TFT Gate Layers and Pillar Spacers". NIP & Digital Fabrication Conference 20, n.º 1 (1 de enero de 2004): 284–90. http://dx.doi.org/10.2352/issn.2169-4451.2004.20.1.art00065_1.
Texto completoBeghalem, Hamida, Khadidja Aliliche y Ahmed Landoulsi. "Phylogeny and Sequence Analysis of Sulla species Based on Intergenic Spacers trnL-trnF". South Asian Journal of Experimental Biology 11, n.º 3 (24 de mayo de 2021): 321–26. http://dx.doi.org/10.38150/sajeb.11(3).p321-326.
Texto completoChen, I. C., C. C. Wei y C. W. Teng. "Simple gate-to-drain overlapped MOSFETs using poly spacers for high immunity to channel hot-electron degradation". IEEE Electron Device Letters 11, n.º 2 (febrero de 1990): 78–81. http://dx.doi.org/10.1109/55.46934.
Texto completoJi Hun Choi, Tae Kyun Kim, Jung Min Moon, Young Gwang Yoon, Byeong Woon Hwang, Dong Hyun Kim y Seok-Hee Lee. "Origin of Device Performance Enhancement of Junctionless Accumulation-Mode (JAM) Bulk FinFETs With High-$\kappa $ Gate Spacers". IEEE Electron Device Letters 35, n.º 12 (diciembre de 2014): 1182–84. http://dx.doi.org/10.1109/led.2014.2364093.
Texto completoMiyashita, Toshihiko, Katsuaki Ookoshi, Akiyoshi Hatada, Keiji Ikeda, Young Suk Kim, Masatoshi Nishikawa y Hajime Kurata. "Design and Optimization of Gate Sidewall Spacers to Achieve 45 nm Ground Rule for High-Performance Applications". Japanese Journal of Applied Physics 48, n.º 4 (20 de abril de 2009): 04C053. http://dx.doi.org/10.1143/jjap.48.04c053.
Texto completoAbdula, Daner, YuJen Chiu, Brendan Marozas, Rami Khazaka, Caleb K. Miskin, Jung Soo Lee y Alexandros T. Demos. "Low-Temperature Selective Si:As Epitaxy". ECS Transactions 114, n.º 2 (27 de septiembre de 2024): 37–46. http://dx.doi.org/10.1149/11402.0037ecst.
Texto completoZhao, Jianli, Yilin Wang, Xiaowei Wang y Yisheng Zhang. "An Experimental Investigation of the Material Properties of the A356 Aluminum Alloy Power Fittings in the Vacuum Die-Casting Process". Materials 17, n.º 6 (8 de marzo de 2024): 1242. http://dx.doi.org/10.3390/ma17061242.
Texto completoBernard, E., T. Ernst, B. Guillaumot, N. Vulliet, Tao Chuan Lim, O. Rozeau, F. Danneville et al. "First Internal Spacers' Introduction in Record High $I_{\rm ON}/I_{\rm OFF}\ \hbox{TiN/HfO}_{2}$ Gate Multichannel MOSFET Satisfying Both High-Performance and Low Standby Power Requirements". IEEE Electron Device Letters 30, n.º 2 (febrero de 2009): 148–51. http://dx.doi.org/10.1109/led.2008.2009008.
Texto completoHeifetz, Aviad. "Non-well-founded-Type Spaces". Games and Economic Behavior 16, n.º 2 (octubre de 1996): 202–17. http://dx.doi.org/10.1006/game.1996.0083.
Texto completoHeifetz, Aviad y Philippe Mongin. "Probability Logic for Type Spaces". Games and Economic Behavior 35, n.º 1-2 (abril de 2001): 31–53. http://dx.doi.org/10.1006/game.1999.0788.
Texto completoRana, Ashwani K. "Impact of sidewall spacer on gate leakage behavior of nano-scale MOSFETs". Semiconductor Physics Quantum Electronics and Optoelectronics 14, n.º 2 (30 de junio de 2011): 203–8. http://dx.doi.org/10.15407/spqeo14.02.203.
Texto completoHeifetz, Aviad y Dov Samet. "Knowledge Spaces with Arbitrarily High Rank". Games and Economic Behavior 22, n.º 2 (febrero de 1998): 260–73. http://dx.doi.org/10.1006/game.1997.0591.
Texto completoRANA, ASHWANI K., NAROTTAM CHAND y VINOD KAPOOR. "MODELING GATE CURRENT FOR NANO SCALE MOSFET WITH DIFFERENT GATE SPACER". Journal of Circuits, Systems and Computers 20, n.º 08 (diciembre de 2011): 1659–75. http://dx.doi.org/10.1142/s0218126611008006.
Texto completoPark, Dong Gyu, Hyunwoo Kim y Jang Hyun Kim. "Improvement Breakdown Voltage by a Using Crown-Shaped Gate". Electronics 12, n.º 3 (17 de enero de 2023): 474. http://dx.doi.org/10.3390/electronics12030474.
Texto completoFitrianatsany, Fitrianatsany. "Harmonisasi Kehidupan Masyarakat Beragama pada Lingkungan Gated Community di Kelurahan Panggungharjo Yogyakarta". Aceh Anthropological Journal 8, n.º 1 (30 de abril de 2024): 97. http://dx.doi.org/10.29103/aaj.v8i1.15986.
Texto completoVimala, Palanichamy y N. R. Nithin Kumar. "Comparative Analysis of Various Parameters of Tri-Gate MOSFET with High-K Spacer". Journal of Nano Research 56 (febrero de 2019): 119–30. http://dx.doi.org/10.4028/www.scientific.net/jnanor.56.119.
Texto completoVeloso, Anabela, Geert Eneman, Eddy Simoen, Bogdan Cretu, An De Keersgieter, Anne Jourdain y Naoto Horiguchi. "(Invited, Digital Presentation) Innovations in Transistor Architecture and Device Connectivity Options for Advanced Logic Scaling". ECS Meeting Abstracts MA2022-01, n.º 19 (7 de julio de 2022): 1059. http://dx.doi.org/10.1149/ma2022-01191059mtgabs.
Texto completoKim, Hyun Woo y Daewoong Kwon. "Analysis on Tunnel Field-Effect Transistor with Asymmetric Spacer". Applied Sciences 10, n.º 9 (27 de abril de 2020): 3054. http://dx.doi.org/10.3390/app10093054.
Texto completoSil, Monali, Sk Masum Nawaz y Abhijit Mallik. "On the performance of hafnium-oxide-based negative capacitance FinFETs, with and without a spacer". Semiconductor Science and Technology 37, n.º 4 (23 de febrero de 2022): 045006. http://dx.doi.org/10.1088/1361-6641/ac52b7.
Texto completoSaxena, Raghvendra Sahai y M. Jagadesh Kumar. "Polysilicon Spacer Gate Technique to Reduce Gate Charge of a Trench Power MOSFET". IEEE Transactions on Electron Devices 59, n.º 3 (marzo de 2012): 738–44. http://dx.doi.org/10.1109/ted.2011.2176946.
Texto completoSpiteri, Jake C., Jonathan S. Schembri y David C. Magri. "A naphthalimide-based ‘Pourbaix sensor’: a redox and pH driven AND logic gate with photoinduced electron transfer and internal charge transfer mechanisms". New Journal of Chemistry 39, n.º 5 (2015): 3349–52. http://dx.doi.org/10.1039/c5nj00068h.
Texto completoMykhaylyuk, Volodymyr. "Namioka spaces, GO-spaces and an o-game". Topology and its Applications 235 (febrero de 2018): 1–13. http://dx.doi.org/10.1016/j.topol.2017.11.008.
Texto completoRomig, Kevin. "The Upper Sonoran Lifestyle: Gated Communities in Scottsdale, Arizona". City & Community 4, n.º 1 (marzo de 2005): 67–86. http://dx.doi.org/10.1111/j.1535-6841.2005.00103.x.
Texto completoAurichi, Leandro F. y Rodrigo R. Dias. "Topological Games and Alster Spaces". Canadian Mathematical Bulletin 57, n.º 4 (1 de diciembre de 2014): 683–96. http://dx.doi.org/10.4153/cmb-2013-048-5.
Texto completoVANNUCCI, STEFANO. "GAME FORMATS AS CHU SPACES". International Game Theory Review 09, n.º 01 (marzo de 2007): 119–38. http://dx.doi.org/10.1142/s021919890700131x.
Texto completoDress, Andreas W. M. y Rudolf Scharlau. "Gated sets in metric spaces". Aequationes Mathematicae 34, n.º 1 (febrero de 1987): 112–20. http://dx.doi.org/10.1007/bf01840131.
Texto completoVassilevski, Konstantin, Irina P. Nikitina, Alton B. Horsfall, Nicolas G. Wright, Andrew J. Smith y C. Mark Johnson. "Silicon Carbide Vertical JFET with Self-Aligned Nickel Silicide Contacts". Materials Science Forum 679-680 (marzo de 2011): 670–73. http://dx.doi.org/10.4028/www.scientific.net/msf.679-680.670.
Texto completoChattopadhyay, Ankush, Arpan Dasgupta, Rahul Das, Atanu Kundu y Chandan K. Sarkar. "Effect of spacer dielectric engineering on Asymmetric Source Underlapped Double Gate MOSFET using Gate Stack". Superlattices and Microstructures 101 (enero de 2017): 87–95. http://dx.doi.org/10.1016/j.spmi.2016.11.024.
Texto completoStone, Sally. "Gate 81:". idea journal 14, n.º 1 (3 de julio de 2018): 80–95. http://dx.doi.org/10.37113/ideaj.vi0.70.
Texto completoRao, Mukund Kadursrinivas, K. R. Sridhara Murthi y Baldev Raj. "Future Indian Space: Perspectives of Game Changers". New Space 6, n.º 2 (junio de 2018): 103–8. http://dx.doi.org/10.1089/space.2017.0013.
Texto completoWucherpfennig, Claudia y Anke Strüver. "„Es ist ja nur ein Spiel…“ – Zur Performativität geschlechtlich codierter Körper, Identitäten und Räume". Geographische Zeitschrift 102, n.º 3 (2014): 175–89. http://dx.doi.org/10.25162/gz-2014-0018.
Texto completoKuang, Fengyu, Cong Li, Haokun Li, Hailong You y M. Jamal Deen. "Effect of Non-Ideal Cross-Sectional Shape on the Performance of Nanosheet-Based FETs". Electronics 12, n.º 16 (11 de agosto de 2023): 3419. http://dx.doi.org/10.3390/electronics12163419.
Texto completoLi, Yu Kui y Yun Peng Liu. "Characteristics of a Triode Field Emission Display Panel with the Suspension Gate Structure". Materials Science Forum 663-665 (noviembre de 2010): 203–6. http://dx.doi.org/10.4028/www.scientific.net/msf.663-665.203.
Texto completoN, Anitha y Dr Srividya P. "Parameter Analysis of CNTFET". International Journal of Recent Technology and Engineering (IJRTE) 8, n.º 2 (30 de julio de 2019): 5355–59. http://dx.doi.org/10.35940/ijrte.b2609078219.
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