Bibliografías temáticas / Software acceleration / Tesis
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Tesis sobre el tema "Software acceleration"

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Publicado: 25 de mayo de 2024
Última modificación: 31 de julio de 2025

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1

Borgström, Fredrik. "Acceleration of FreeRTOS withSierra RTOS accelerator : Implementation of a FreeRTOS software layer onSierra RTOS accelerator." Thesis, KTH, Data- och elektroteknik, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-188518.

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Today, the effect of the most common ways to improve the performance of embedded systems and real-time operating systems is stagnating. Therefore it is interesting to examine new ways to push the performance boundaries of embedded systems and real-time operating systems even further. It has previously been demonstrated that the hardware-based real-time operating system, Sierra, has better performance than the software-based real-time operating system, FreeRTOS. These real-time operating systems have also been shown to be similar in many aspects, which mean that it is possible for Sierra to acc
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2

Kulkarni, Pallavi Anil. "Hardware acceleration of software library string functions." Ann Arbor, Mich. : ProQuest, 2007. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:1447245.

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Thesis (M.S. in Computer Engineering)--S.M.U., 2007.<br>Title from PDF title page (viewed Nov. 19, 2009). Source: Masters Abstracts International, Volume: 46-03, page: 1577. Adviser: Mitch Thornton. Includes bibliographical references.
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3

Blumer, Aric David. "Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration." Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/29380.

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The run-time reconfiguration of Field Programmable Gate Arrays (FPGAs) opens new avenues to hardware reuse. Through the use of process migration between hardware and software, an FPGA provides a parallel execution cache. Busy processes can be migrated into hardware-based, parallel processors, and idle processes can be migrated out increasing the utilization of the hardware. The application of hardware/software process migration to the acceleration of Register Transfer Level (RTL) circuit simulation is developed and analyzed. RTL code can exhibit a form of locality of reference such that execut
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4

Samothrakis, Stavros Nikolaou. "Acceleration techniques in ray tracing for dynamic scenes." Thesis, University of Sussex, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.241671.

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5

Singh, Ajeet. "GePSeA: A General-Purpose Software Acceleration Framework for Lightweight Task Offloading." Thesis, Virginia Tech, 2009. http://hdl.handle.net/10919/34264.

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Hardware-acceleration techniques continue to be used to boost the performance of scientific codes. To do so, software developers identify portions of these codes that are amenable for offloading and map them to hardware accelerators. However, offloading such tasks to specialized hardware accelerators is non-trivial. Furthermore, these accelerators can add significant cost to a computing system. <p> Consequently, this thesis proposes a framework called GePSeA (General Purpose Software Acceleration Framework), which uses a small fraction of the computational power on multi-core architectures
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6

Zhu, Huanzhou. "Developing graph-based co-scheduling algorithms with GPU acceleration." Thesis, University of Warwick, 2016. http://wrap.warwick.ac.uk/92000/.

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On-chip cache is often shared between processes that run concurrently on different cores of the same processor. Resource contention of this type causes the performance degradation to the co-running processes. Contention-aware co-scheduling refers to the class of scheduling techniques to reduce the performance degradation. Most existing contention-aware co-schedulers only consider serial jobs. However, there often exist both parallel and serial jobs in computing systems. This thesis aims to tackle these issues. We start with modelling the problem of co-scheduling the mix of serial and parallel
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7

Yalim, Hacer. "Acceleration Of Direct Volume Rendering With Texture Slabs On Programmable Graphics Hardware." Master's thesis, METU, 2005. http://etd.lib.metu.edu.tr/upload/12606195/index.pdf.

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This thesis proposes an efficient method to accelerate ray based volume rendering with texture slabs using programmable graphics hardware. In this method, empty space skipping and early ray termination are utilized without performing any preprocessing on CPU side. The acceleration structure is created on the fly by making use of depth buffer efficiently on Graphics Processing Unit (GPU) side. In the proposed method, texture slices are grouped together to form a texture slab. Rendering all the slabs from front to back viewing order in multiple rendering passes generates the resulting volume ima
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8

Sherban, V. Yu. "Software components of the system for the kinematic and dynamic analysis of machines for sewing, textile and shoe industries." Thesis, Київський національний університет технологій та дизайну, 2017. https://er.knutd.edu.ua/handle/123456789/6655.

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9

Wang, Tsu-Han. "Real-time Software Architectures and Performance Evaluation Methods for 5G Radio Systems." Electronic Thesis or Diss., Sorbonne université, 2022. https://accesdistant.sorbonne-universite.fr/login?url=https://theses-intra.sorbonne-universite.fr/2022SORUS362.pdf.

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La thèse porte sur les architectures temps réel pour la radio-logicielle 5G. Afin de répondre aux exigences de performances de la 5G, une accélération des procédés critiques combinée à des méthodes d’ordonnancement de processus temps réels sont nécessaires. Dans les systèmes embarqués 5G, l'accélération équivaut à une combinaison judicieuse d'unités matérielles supplémentaires pour les fonctions les plus coûteuses en termes de calcul avec des composants logiciels pour des procédures de contrôle complexe ainsi que l’arithmétique simples. Des solutions entièrement logicielles apparaissent égalem
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10

Tell, Eric. "Design of Programmable Baseband Processors." Doctoral thesis, Linköping : Univ, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-4377.

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11

Axillus, Viktor. "Comparing Julia and Python : An investigation of the performance on image processing with deep neural networks and classification." Thesis, Blekinge Tekniska Högskola, Institutionen för programvaruteknik, 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-19160.

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Python is the most popular language when it comes to prototyping and developing machine learning algorithms. Python is an interpreted language that causes it to have a significant performance loss compared to compiled languages. Julia is a newly developed language that tries to bridge the gap between high performance but cumbersome languages such as C++ and highly abstracted but typically slow languages such as Python. However, over the years, the Python community have developed a lot of tools that addresses its performance problems. This raises the question if choosing one language over the o
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12

Závodník, Tomáš. "Architektura pro rekonstrukci knihy objednávek s nízkou latencí." Master's thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2016. http://www.nusl.cz/ntk/nusl-255477.

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Information technology forms an important part of the world and algorithmic trading has already become a common concept among traders. The High Frequency Trading (HFT) requires use of special hardware accelerators which are able to provide input response with sufficiently low latency. This master's thesis is focused on design and implementation of an architecture for order book building, which represents an essential part of HFT solutions targeted on financial exchanges. The goal is to use the FPGA technology to process information about an exchange's state with latency so low that the resulti
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13

Kekely, Lukáš. "Softwarově řízené monitorování síťového provozu." Doctoral thesis, Vysoké učení technické v Brně. Fakulta informačních technologií, 2017. http://www.nusl.cz/ntk/nusl-412592.

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Tato disertační práce se zabývá návrhem nového způsobu softwarově řízené (definované) hardwarové akcelerace pro moderní vysokorychlostní počítačové sítě. Hlavním cílem práce je formulace obecného, flexibilního a jednoduše použitelného konceptu akcelerace použitelného pro různé bezpečnostní a monitorovací aplikace, který by umožnil jejich reálné nasazení ve 100 Gb/s a rychlejších sítích. Disertační práce začíná rozborem aktuálního stavu poznání v oborech síťového monitorování, bezpečnosti a způsobů akcelerace zpracování vysokorychlostních síťových dat. Na základě tohoto rozboru je formulován a
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14

David, Radu Alin. "Improving Channel Estimation and Tracking Performance in Distributed MIMO Communication Systems." Digital WPI, 2015. https://digitalcommons.wpi.edu/etd-dissertations/229.

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This dissertation develops and analyzes several techniques for improving channel estimation and tracking performance in distributed multi-input multi-output (D-MIMO) wireless communication systems. D-MIMO communication systems have been studied for the last decade and are known to offer the benefits of antenna arrays, e.g., improved range and data rates, to systems of single-antenna devices. D-MIMO communication systems are considered a promising technology for future wireless standards including advanced cellular communication systems. This dissertation considers problems related to channel e
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15

Lee, Joo Hong. "Hybrid Parallel Computing Strategies for Scientific Computing Applications." Diss., Virginia Tech, 2012. http://hdl.handle.net/10919/28882.

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Multi-core, multi-processor, and Graphics Processing Unit (GPU) computer architectures pose significant challenges with respect to the efficient exploitation of parallelism for large-scale, scientific computing simulations. For example, a simulation of the human tonsil at the cellular level involves the computation of the motion and interaction of millions of cells over extended periods of time. Also, the simulation of Radiative Heat Transfer (RHT) effects by the Photon Monte Carlo (PMC) method is an extremely computationally demanding problem. The PMC method is example of the Monte Carlo simu
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16

Agha, Shahrukh. "Software and hardware techniques for accelerating MPEG2 motion estimation." Thesis, Loughborough University, 2006. https://dspace.lboro.ac.uk/2134/33935.

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The aim of this thesis is to accelerate the process of motion estimation (ME) for the implementation of real time, portable video encoding. To this end a number of different techniques have been considered and these have been investigated in detail. Data Level Parallelism (DLP) is exploited first, through the use of vector instruction extensions using configurable/re-configurable processors to form a fast System-On-Chip (SoC) video encoder capable of embedding both full search and fast ME methods. Further parallelism is then exploited in the form of Thread Level Parallelism (TLP), introduced i
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17

Linford, John Christian. "Accelerating Atmospheric Modeling Through Emerging Multi-core Technologies." Diss., Virginia Tech, 2010. http://hdl.handle.net/10919/27599.

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The new generations of multi-core chipset architectures achieve unprecedented levels of computational power while respecting physical and economical constraints. The cost of this power is bewildering program complexity. Atmospheric modeling is a grand-challenge problem that could make good use of these architectures if they were more accessible to the average programmer. To that end, software tools and programming methodologies that greatly simplify the acceleration of atmospheric modeling and simulation with emerging multi-core technologies are developed. A general model is developed to s
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18

Yu, Jason Kwok Kwun. "Vector processing as a soft-core processor accelerator." Thesis, University of British Columbia, 2008. http://hdl.handle.net/2429/2394.

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Soft processors simplify hardware design by being able to implement complex control strategies using software. However, they are not fast enough for many intensive data-processing tasks, such as highly data-parallel embedded applications. This thesis suggests adding a vector processing core to the soft processor as a general-purpose accelerator for these types of applications. The approach has the benefits of a purely software-oriented development model, a fixed ISA allowing parallel software and hardware development, a single accelerator that can accelerate multiple functions in an applicatio
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19

Bashford-Rogers, Thomas. "Accelerating global illumination for physically-based rendering." Thesis, University of Warwick, 2011. http://wrap.warwick.ac.uk/36762/.

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Lighting is essential to generate realistic images using computer graphics. The computation of lighting takes into account the multitude of ways which light propagates around a virtual scene. This is termed global illumination, and is a vital part of physically-based rendering. Although providing compelling and accurate images, this is a computationally expensive process. This thesis presents several methods to improve the speed of global illumination computation, and therefore enables faster image synthesis. Global illumination can be calculated in an offline process, typically taking many mi
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20

Kancharla, Akshitha, and Akhil Pannala. "Factors for Accelerating the Development Speed in Systems of Artificial Intelligence." Thesis, Blekinge Tekniska Högskola, Institutionen för programvaruteknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-18420.

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Background: With the increase in the application of Artificial Intelligence, there is an urge to find ways to increase the development speed of these systems (time-to-market). Because time is one of the most expensive and valuable resources in software development. Faster development speed is essential for companies to survive. There are articles in the literature that states the factors/antecedents for improving the development speed in Traditional Software Engineering. However, we cannot draw direct conclusions from these factors because development in Traditional Software Engineering and Ar
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21

Woods, Andrew. "Accelerating software radio astronomy FX correlation with GPU and FPGA co-processors." Master's thesis, University of Cape Town, 2010. http://hdl.handle.net/11427/12212.

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Includes abstract.<br>Includes bibliographical references (leaves [117]-121).<br>This thesis attempts to accelerate compute intensive sections of a frequency domain radio astronomy correlator using dedicated co-processors. Two co-processor implementations were made independently with one using reconfigurable hardware (Xilinx Virtex 4LXlOO) and the other uses a graphics processor (Nvidia 9800GT). The objective of a radio astronomy correlator is to compute the complex valued correlation products for each baseline which can be used to reconstruct the sky's radio brightness distribution. Radio ast
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22

Enes, Petter. "Build and Release Management : Supporting development of accelerator control software at CERN." Thesis, Norwegian University of Science and Technology, Department of Computer and Information Science, 2007. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-8708.

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<p>Software configuration management deals with control of the evolution of complex computer systems. The ability to handle changes, corrections and extensions is decisive for the outcome of a software project. Automated processes for handling these elements are therefore a crucial part of software development. This thesis focuses on build and release management, in the context of developing a control system for the world’s biggest particle accelerator. Build and release cover topics such as build support, versioning, dependency management and release management. The main part of the work has
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23

Motyka, Mikael. "Impact of Usability for Particle Accelerator Software Tools Analyzing Availability and Reliability." Thesis, Blekinge Tekniska Högskola, Institutionen för programvaruteknik, 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-14394.

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The importance of considering usability when developing software is widely recognized in literature. This non-functional system aspect focuses on the ease, effectiveness and efficiency of handling a system. However, usability cannot be defined as a specific system aspect since it depends on the field of application. In this work, the impact of usability for accelerator tools targeting availability and reliability analysis is investigated by further developing the already existing software tool Availsim. The tool, although proven to be unique by accounting for special accelerator complexities n
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24

Khasymski, Aleksandr Sergeev. "Accelerated Storage Systems." Diss., Virginia Tech, 2015. http://hdl.handle.net/10919/51612.

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Today's large-scale, high-performance, data-intensive applications put a tremendous stress on data centers to store, index, and retrieve large amounts of data. Exemplified by technologies such as social media, photo and video sharing, and e-commerce, the rise of the real-time web demands data stores support minimal latencies, always-on availability and ever-growing capacity. These requirements have fostered the development of a large number of high-performance storage systems, arguably the most important of which are Key-Value (KV) stores. An emerging trend for achieving low latency and high t
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25

Alhamwi, Ali. "Co-design hardware/software of real time vision system on FPGA for obstacle detection." Thesis, Toulouse 3, 2016. http://www.theses.fr/2016TOU30342/document.

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La détection, localisation d'obstacles et la reconstruction de carte d'occupation 2D sont des fonctions de base pour un robot navigant dans un environnement intérieure lorsque l'intervention avec les objets se fait dans un environnement encombré. Les solutions fondées sur la vision artificielle et couramment utilisées comme SLAM (simultaneous localization and mapping) ou le flux optique ont tendance a être des calculs intensifs. Ces solutions nécessitent des ressources de calcul puissantes pour répondre à faible vitesse en temps réel aux contraintes. Nous présentons une architecture matérielle
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26

Magnuson, Martin. "Process Control Methods for Operation of Superconducting Cavities at the LEP Accelerator at CERN." Thesis, Linköpings universitet, Institutionen för fysik, kemi och biologi, 1992. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-56503.

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The aim of this thesis is to analyse the cryogenic process for cooling superconducting radio frequency accelerator test cavities in the LEP accelerator at CERN. A liquefaction cryoplant is analysed, including the production of liquid helium at 4.5 K, the systems for distribution and regulation of liquid helium, and the radio frequency field used for accelerating particles. After discussing regulation problems and modifications planned for a new cavity installation in 1992, different techniques for specifying the control programs for the new installation are evaluated. Various diagramming techn
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27

Ouedraogo, Ganda Stéphane. "Automatic synthesis of hardware accelerator from high-level specifications of physical layers for flexible radio." Thesis, Rennes 1, 2014. http://www.theses.fr/2014REN1S183/document.

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L'internet des objets vise à connecter des milliards d'objets physiques ainsi qu'à les rendre accessibles depuis le monde numérique que représente l'internet d'aujourd'hui. Pour ce faire, l'accès à ces objets sera majoritairement réalisé sans fil et sans utiliser d'infrastructures prédéfinies ou de normes spécifiques. Une telle technologie nécessite de définir et d'implémenter des nœuds radio intelligents capables de s'adapter à différents protocoles physiques de communication. Nos travaux de recherches ont consisté à définir un flot de conception pour ces nœuds intelligents partant de leur mo
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28

Silva, João Paulo Sá da. "Data processing in Zynq APSoC." Master's thesis, Universidade de Aveiro, 2014. http://hdl.handle.net/10773/14703.

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Mestrado em Engenharia de Computadores e Telemática<br>Field-Programmable Gate Arrays (FPGAs) were invented by Xilinx in 1985, i.e. less than 30 years ago. The influence of FPGAs on many directions in engineering is growing continuously and rapidly. There are many reasons for such progress and the most important are the inherent reconfigurability of FPGAs and relatively cheap development cost. Recent field-configurable micro-chips combine the capabilities of software and hardware by incorporating multi-core processors and reconfigurable logic enabling the development of highly optimized compu
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29

Jönsson, Oscar. "An explorative study of the technology transfer coach as a preliminary for the design of a computer aid." Thesis, Linköpings universitet, Interaktiva och kognitiva system, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-108308.

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The university technology transfer coach has an important role in supporting the commercialization of research results. This thesis has studied the technology transfer coach and their needs in the coaching process. The goal has been to investigate information needs of the technology transfer coach as a preliminary for the design of computer aids.Using a grounded theory approach, we interviewed 17 coaches working in the Swedish technology transfer environment. Extracted quotes from interviews were openly coded and categorized. The analysis show three main problem areas related to the informatio
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30

Yang, Fu-Kai, and 楊復凱. "Acceleration and Improvement of MPEG View Synthesis Reference Software on NVIDIA CUDA." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/62819489159539479165.

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碩士<br>國立交通大學<br>電子研究所<br>100<br>With the prosperity of 3D technology, Free Viewpoint Television (FTV) becomes a popular research topic. “View Synthesis” is a key step in FTV. There are some important and to-be-solved issues such as real-time operation and complexity reduction. NVIDIA Compute Unified Device Architecture (CUDA) is an effective platform in handling data-intensive applications. To implement the MPEG view synthesis reference software (VSRS) on CUDA, we parallelize the VSRS structure. In the meanwhile, our proposed parallel scheme improves the picture quality. We first propose an in
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31

Wu, Jyun-Cheng, and 吳峻丞. "Design of a Real-time Software-Based GPS Baseband Receiver Using GPU Acceleration." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/21287776369433988238.

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碩士<br>國立臺灣大學<br>電子工程學研究所<br>99<br>Nowaday, the personal navigation devices are more and more popular. The demand of GPS receiver in any form is also increasing. Developing the GPS receiver in software is feasible with the increasing of processor computation power. Compared to the traditional hardware receiver, the software-based receiver has many advantages. In system integration, upgrade, new algorism adopting and the platform changing, the software-based receiver has much more flexibility than traditional hardware receiver. In this thesis, I will improve the GPS software baseband receiver b
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32

Zhou, Boyou. "A multi-layer approach to designing secure systems: from circuit to software." Thesis, 2019. https://hdl.handle.net/2144/36149.

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In the last few years, security has become one of the key challenges in computing systems. Failures in the secure operations of these systems have led to massive information leaks and cyber-attacks. Case in point, the identity leaks from Equifax in 2016, Spectre and Meltdown attacks to Intel and AMD processors in 2017, Cyber-attacks on Facebook in 2018. These recent attacks have shown that the intruders attack different layers of the systems, from low-level hardware to software as a service(SaaS). To protect the systems, the defense mechanisms should confront the attacks in the different layer
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33

Nüssle, Mondrian [Verfasser]. "Acceleration of the hardware software interface of a communication device for parallel systems / vorgelegt von Mondrian Benediktus Nüßle." 2009. http://d-nb.info/993238440/34.

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34

TADDEI, RUGGERO. "Numerical Techniques for Antenna Arrays: Multi-Objective Optimization and Method of Moments Acceleration." Doctoral thesis, 2015. http://hdl.handle.net/2158/976428.

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The approximate solution of Maxwell's equations exploiting Numerical Techniques is known as Computational ElectroMagnetics (CEM). CEM techniques have been available for close on four decades now, and they currently form an invaluable part of current RF, antenna and microwave engineering practice. The present work is focused on two different applications of numerical techniques for Computational Electromagnetics: numerical optimization and full-wave techniques.
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35

Abell, Stephen W. "Parallel acceleration of deadlock detection and avoidance algorithms on GPUs." Thesis, 2013. http://hdl.handle.net/1805/3653.

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Indiana University-Purdue University Indianapolis (IUPUI)<br>Current mainstream computing systems have become increasingly complex. Most of which have Central Processing Units (CPUs) that invoke multiple threads for their computing tasks. The growing issue with these systems is resource contention and with resource contention comes the risk of encountering a deadlock status in the system. Various software and hardware approaches exist that implement deadlock detection/avoidance techniques; however, they lack either the speed or problem size capability needed for real-time systems. The researc
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36

Lin, Jing-bin, and 林景彬. "Software Accelerator Discussion for H.264/AVC." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/29527963119602892761.

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碩士<br>南台科技大學<br>電子工程系<br>96<br>With the flourishing development in multimedia technology and Internet, the application of multimedia is very popular. Due to the demand of transmitting and storing large image data, high-performance video compression techniques play important and inevitable roles in image processing. A new video compression standard, H.264, was proposed after the reveals of MPEG-1, MPEG-2 and MPEG-4 standards. It has the property of high compressing rate than MPEG-4, and has recently become a major role in multimedia field. The complexity of H.264 decoder is very huge. If the im
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37

Yuan, Yi. "A microprocessor performance and reliability simulation framework using the speculative functional-first methodology." Thesis, 2011. http://hdl.handle.net/2152/ETD-UT-2011-12-4848.

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With the high complexity of modern day microprocessors and the slow speed of cycle-accurate simulations, architects are often unable to adequately evaluate their designs during the architectural exploration phases of chip design. This thesis presents the design and implementation of the timing partition of the cycle-accurate, microarchitecture-level SFFSim-Bear simulator. SFFSim-Bear is an implementation of the speculative functional-first (SFF) methodology, and utilizes a hybrid software-FPGA platform to accelerate simulation throughput. The timing partition, implemented in FPGA, features thr
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38

Lin, Zi-Gang, and 林子剛. "Design of Stack Memory Device and System Software for Java Accelerator IP." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/61631031609034851274.

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39

Neto, Nuno Miguel Ladeira. "A Container-based architecture for accelerating software tests via setup state caching and parallelization." Master's thesis, 2019. https://hdl.handle.net/10216/122203.

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40

Chang, Keng-Chia, and 張耿嘉. "Adaboost-based Hardware Accelerator DIP Design and Hardware/Software Co-simulation for Face Detection." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/96k2r2.

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碩士<br>國立中興大學<br>電機工程學系所<br>106<br>In recent years, many car accidents caused by the fatigue driving have occurred frequently. Thus, many scholars and experts all over the world have paid great efforts in this issue, and they are developing the suitable detection technologies to reduce car accidents caused by driver''s drowsiness. For the fatigue detection issue, the driver’s spirit status can be evaluated through the eye blinking condition. Therefore, the proposed design implements the hardware accelerator to process the large amount of high repetitiveness data on a hardware/software co-desig
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(9529172), Ejebagom J. Ojogbo. "ZipThru: A software architecture that exploits Zipfian skew in datasets for accelerating Big Data analysis." Thesis, 2020.

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<div>In the past decade, Big Data analysis has become a central part of many industries including entertainment, social networking, and online commerce. MapReduce, pioneered by Google, is a popular programming model for Big Data analysis, famous for its easy programmability due to automatic data partitioning, fault tolerance, and high performance. Majority of MapReduce workloads are summarizations, where the final output is a per-key ``reduced" version of the input, highlighting a shared property of each key in the input dataset.</div><div><br></div><div>While MapReduce was originally proposed
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"Efficient and Secure Deep Learning Inference System: A Software and Hardware Co-design Perspective." Doctoral diss., 2020. http://hdl.handle.net/2286/R.I.62825.

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abstract: The advances of Deep Learning (DL) achieved recently have successfully demonstrated its great potential of surpassing or close to human-level performance across multiple domains. Consequently, there exists a rising demand to deploy state-of-the-art DL algorithms, e.g., Deep Neural Networks (DNN), in real-world applications to release labors from repetitive work. On the one hand, the impressive performance achieved by the DNN normally accompanies with the drawbacks of intensive memory and power usage due to enormous model size and high computation workload, which significantly hampers
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Ramesh, Chinthala. "Hardware-Software Co-Design Accelerators for Sparse BLAS." Thesis, 2017. http://etd.iisc.ac.in/handle/2005/4276.

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Sparse Basic Linear Algebra Subroutines (Sparse BLAS) is an important library. Sparse BLAS includes three levels of subroutines. Level 1, Level2 and Level 3 Sparse BLAS routines. Level 1 Sparse BLAS routines do computations over sparse vector and spare/dense vector. Level 2 deals with sparse matrix and vector operations. Level 3 deals with sparse matrix and dense matrix operations. The computations of these Sparse BLAS routines on General Purpose Processors (GPPs) not only suffer from less utilization of hardware resources but also takes more compute time than the workload due to poor data loc
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