Bibliografías temáticas / SOC.045.040.001

Literatura académica sobre el tema "SOC.045.040.001"

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Publicado: 26 de julio de 2024
Última modificación: 27 de julio de 2024

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Artículos de revistas sobre el tema "SOC.045.040.001"

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中川, 友紀子. "SoC". Journal of Japan Society for Fuzzy Theory and Intelligent Informatics 33, n.º 1 (15 de febrero de 2021): 30. http://dx.doi.org/10.3156/jsoft.33.1_30_2.

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Ehrlich, Cyril y Dave Russell. "Soc. Pop." Musical Times 129, n.º 1742 (abril de 1988): 192. http://dx.doi.org/10.2307/965320.

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Moch, S., M. Bereković, H. J. Stolberg, L. Friebe, M. B. Kulaczewski, A. Dehnhardt y P. Pirsch. "HIBRID-SOC". ACM SIGARCH Computer Architecture News 32, n.º 3 (junio de 2004): 55–61. http://dx.doi.org/10.1145/1024295.1024303.

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Buchanan, Mark. "SOC revisited". Nature Physics 11, n.º 6 (junio de 2015): 442. http://dx.doi.org/10.1038/nphys3354.

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Smith, Matthew. "The SOC is Dead, Long Live the SOC!" ITNOW 62, n.º 1 (17 de febrero de 2020): 34–35. http://dx.doi.org/10.1093/itnow/bwaa015.

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Abstract The traditional tiered security operation centre approach is flawed, writes Matthew Smith, Global Head of Cyber Security, St. James's Palace - simply because we are human. We must leverage the benefits of machine learning, user behaviour analytics and security automation to deliver effective detection and response in 2020 and beyond.
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Chen, Jein-Shan, Xin Chen, Shaohua Pan y Jiawei Zhang. "Some characterizations for SOC-monotone and SOC-convex functions". Journal of Global Optimization 45, n.º 2 (7 de noviembre de 2008): 259–79. http://dx.doi.org/10.1007/s10898-008-9373-z.

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Lee, Hyoung-Ro, Won-Jong Kim, Han-Jin Cho y Chi-Ho Lin. "Development and Verification of SoC Architecture using SoC Virtual Platform". Journal of the Institute of Electronics and Information Engineers 54, n.º 11 (30 de noviembre de 2017): 86–92. http://dx.doi.org/10.5573/ieie.2017.54.11.86.

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KOBLANOV, Nurbek y Rasim SULIEV. "SOC Building Basics". Trudy Universiteta, n.º 2 (2021): 168–71. http://dx.doi.org/10.52209/1609-1825_2021_2_168.

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KOBLANOV, Nurbek y Rasim SULIEV. "SOC Building Basics". Trudy Universiteta, n.º 2 (2021): 179–82. http://dx.doi.org/10.52209/1609-1825_2021_2_179.

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Eshraghian, K. "SoC Emerging Technologies". Proceedings of the IEEE 94, n.º 6 (junio de 2006): 1197–213. http://dx.doi.org/10.1109/jproc.2006.873615.

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Tesis sobre el tema "SOC.045.040.001"

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Pratomo, Istas. "Adaptive NoC for reconfigurable SoC". Phd thesis, Université Rennes 1, 2013. http://tel.archives-ouvertes.fr/tel-00980066.

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Chips will be designed with billions of transistors and heterogeneous components integrated to provide full functionality of a current application for embedded system. These applications also require highly parallel and flexible communicating architecture through a regular interconnection network. The emerging solution that can fulfill this requirement is Network-on-Chips (NoCs). Designing an ideal NoC with high throughput, low latency, minimum using resources, minimum power consumption and small area size are very time consuming. Each application required different levels of QoS such as minimum level throughput delay and jitter. In this thesis, firstly, we proposed an evaluation of the impact of design parameters on performance of NoC. We evaluate the impact of NoC design parameters on the performances of an adaptive NoCs. The objective is to evaluate how big the impact of upgrading the value on performances. The result shows the accuracy of choosing and adjusting the network parameters can avoid performance degradation. It can be considered as the control mechanism in an adaptive NoC to avoid the degradation of QoS NoC. The use of deep sub-micron technology in embedded system and its variability process cause Single Event Upsets (SEU) and ''aging'' the circuit. SEU and aging of circuit is the major problem that cause the failure on transmitting the packet in a NoC. Implementing fault-tolerant routing techniques in NoC switching instead of adding virtual channel is the best solution to avoid the fault in NoC. Communication performance of a NoC is depends heavily on the routing algorithm. An adaptive routing algorithm such as fault-tolerant has been proposed for deadlock avoidance and load balancing. This thesis proposed a novel adaptive fault-tolerant routing algorithm for 2D mesh called Gradient and for 3D mesh called Diagonal. Both algorithms consider sequences of alternative paths for packets when the main path fails. The proposed algorithm tolerates faults in worst condition traffic in NoCs. The number of hops, the number of alternative paths, latency and throughput in faulty network are determined and compared with other 2D mesh routing algorithms. Finally, we implemented Gradient routing algorithm into FPGA. All these work were validated and characterized through simulation and implemented into FPGA. The results provide the comparison performance between proposed method with existing related method using some scenarios.
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Yap, S. Y. "SoC architectures for video compression". Thesis, Queen's University Belfast, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.411805.

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Procháska, František. "Implementace protokolu EtherCAT pro SoC". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2019. http://www.nusl.cz/ntk/nusl-400616.

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Nemoto, Rie. "Soil organic carbon (SOC) now and in the future. Effect of soil characteristics and agricultural management on SOC and model initialisation methods using recent SOC data". Phd thesis, Université Blaise Pascal - Clermont-Ferrand II, 2013. http://tel.archives-ouvertes.fr/tel-00973853.

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Soil organic carbon (SOC) concentrations and greenhouse gas (GHG) emissions are not uniform across the landscape, but assemble in "hotspots" in specific areas. These differences are mainly driven by human-induced activities such as agricultural management. 40-50% of the Earth's land surface is under agricultural land-use, for instance cropland, managed grassland and permanent crops including agro-forestry and bio-energy crops. Furthermore, 62% of the global soil C stock is SOC and the soil stores more than 3 times more C than the atmosphere. Thus, C sequestration in agricultural soil has a potentially important role in increasing SOC storage and GHG mitigation, and there is considerable interest in understanding the effects of agricultural management on SOC and GHG fluxes in both grasslands and croplands, in order to better assess the uncertainty and vulnerability of terrestrial SOC reservoirs. For the sake of discovering the agricultural management practices relating to the effective and sustainable C sequestration in agricultural lands in Europe, simulating future terrestrial C stocks and GHG budgets under varied agricultural management systems in major European ecosystems is essential. Using models is a useful method with the purpose of this and abundant studies have carried out. However, many model results have not been validated with reliable observed long-term data, while other studies have reported a strong impact of model initialisation on model result. Nevertheless, predictions of annual to decadal variability in the European terrestrial C and GHG ressources largely rely on model results. Consequently, finding the most appropriate and comprehensive model initialisation method for obtaining reliable model simulations became important, especially for process-based ecosystem models. In recent years, Zimmermann et al. (2007) have succeed in initialising the Rothamsted Carbon model (RothC) using a physical and chemical soil fractionation method. For that reason, we hypothesised that measured detailed SOC data would be useful to initialise ecosystem models, and this hypothesis should be tested for different process-based models and agricultural land-use and management. (...)
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Ding, Hao. "Key concepts for implementing SoC-Holter". Thesis, Clermont-Ferrand 2, 2011. http://www.theses.fr/2011CLF22166/document.

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En dépit du développement rapide de la médecine, les maladies cardiovasculaires restent la première cause de mortalité dans le monde. En France, chaque année, plus de 50 000 personnes meurent subitement en raison d'arythmies cardiaques. L'identification des patients à risque élevé de décès soudain est toujours un défi. Pour détecter les arythmies cardiaques, actuellement Holter est généralement utilisé pour enregistrer les signaux électrocardiogramme (ECG) à 1~3 dérivations pendant 24h à 72h. Cependant l'utilisation de Holter est limitée parmi la population en raison de son encombrement (pas convivial) et de son coût. Un Holter mono puce portable nommé SoC-Holter qui permet d'enregistrer 1 à 4 dérivations est introduit. Le déploiement d'un réseau de capteurs sans fil exige que chaque SoC-Holter soit peu encombrant et peu cher, et consomme peu d’énergie. Afin de minimiser la consommation d'énergie et le coût du système, la technologie Complementary Metal Oxide Semiconductor (CMOS) (0.35μm) est utilisée pour la première implémentation de SoC-Holter. Puis une nouvelle méthode de détection basée sur Acquisition Comprimée (CS) est introduite pour résoudre les problèmes de consommation d'énergie et de capacité de stockage de SoC-Holter. Le principe premier de cette plate-forme est d'échantillonner les signaux ECG sous la fréquence de Nyquist ‘sub-Nyquist’ et par la suite de classer directement les mesures compressées en états normal et anormal. Minimiser le nombre de fils qui relient les électrodes à la plate-forme peut rendre l’utilisateur de SoC-Holter plus confortable, car deux électrodes sont très proches sur la surface du corps. La différence ECG enregistrée est analysée à l'aide de Vectocardiogramme (VCG). Les résultats expérimentaux montrent qu'une approche intégrée, à faible coût et de faible encombrement (SoC-Holter) est faisable. Le SoC-Holter consomme moins de 10mW en fonctionnement. L'estimation des paramètres du signal acquis est effectuée directement à partir de mesures compressées, éliminant ainsi l'étape de la reconstruction et réduisant la complexité et le volume des calculs. En outre, le système fournit les signaux ECG compressés sans perte d'information, de ce fait il réduit significativement la consommation d'énergie pour l'envoi de message et l’espace de stockage mémoire. L'effet de placement des électrodes est évalué sur la QRS complexe lorsqu'il a enregistré avec deux électrodes adjacentes. La méthode est basée sur l'algorithme de ‘QRS-VCG loop alignment’. La méthode moindre carré est utilisée pour estimer la corrélation entre une boucle VCG observée et une boucle de référence en respectant les transformations de rotation et la synchronisation du temps. Les emplacements d'électrodes les moins sensibles aux interférences sont étudiés
According to the figures released by World Health Organization (WHO), cardiovascular disease is the number one cause of death in the world. In France every year more than 50,000 people die suddenly due cardiac arrhythmias. Identification of high risk sudden death patients is still a challenge. To detect cardiac arrhythmias, currently Holter is generally used to record 1~4 leads electrocardiogram (ECG) signals during 24h to 72h. However the use of Holter is limited among the population due to its form factor (not user-friendly) and cost. An integrated single chip wearable Holter named SoC-Holter that enables to record 1 to 4 leads ECG is introduced. Deployment of wireless sensor network requires each SoC-Holter with less power consumption, low-cost charging system and less die area.To minimize energy consumption and system cost, Complementary Metal Oxide Semiconductor (CMOS) technology (0.35μm) is used to prototype the first implementation of SoC-Holter. Then a novel method based on Compressed Sensing (CS) technique is introduced for solving the problems of power consumption and storage capacity of SoC-Holter. The main principle underlying this framework is to sample analog signals at sub-Nyquist rate and to classify directly compressed measurement into normal and abnormal state. Minimizing the wire connected electrodes to the platform can make the carrier more comfortable because two electrodes are attached closely on the surface of the body. Recording difference ECG is analyzed using Vectorcardiogram (VCG) theory. Experimental results show that an integrated, low cost, and user-friendly SoC-Holter is feasible. SoC-Holter consumes less than 10mW while the device is operating. It takes advantage of estimating parameters directly from compressed measurements, thereby eliminating the reconstruction stage and reducing the computational complexity on the platform. In addition, the framework provides compressed ECG signals without loss of information, reducing significantly the power consumption for message sending and memory storage space. The effect of electrode placement is evaluated by estimating QRS complex in recorded ECG signals by two adjacent electrodes. The method is based on the QRS-VCG loop alignment algorithm that estimates Least Square (LS) between an observed VCG loop and a reference loop with respect to the transformations of rotation and time synchronization. The electrode location with less sensitive to interference is investigated
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Ding, Jian. "Electro-thermal models for highly integrated SoC". Thesis, Queen's University Belfast, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.486133.

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In this thesis, electronic packaging technology was introduced and discussed from the device level to system level, followed by a review of crosstalk suppression, thermal management and electro-thermal modelling of electronic packages. The first dynamic electro-thermal UCSD HBT model for the OMMICTM DH15IB InP process was developed in an electro-thermal simulator fREEDATM. Simulations were performed for the devices and a demonstrator amplifier in fREEDATM and Agilent™ ADS. The results showed how the thermal effects influenced the electrical behaviour. Static DC IV measurements and S parameter measurements were applied to verify the simulation results. At package level, a transmitter System-in-Package (SiP) demonstrator was developed. It was modelled and analyzed with a multi-physics simulator COMSOL Multiphysics™. A Low Temperature Co-fired Ceramic (LTCC) antenna array at 65GHz was designed for this SiP package demonstrator. Thermal vias were demonstrated to have positive effects on the package thermal management by simulation. An embedded chip package based on a new die attachment method was also electrothermally modelled and simulated with COMSOL Multiphysics™. The results have a good agreement with the measurement results based on a Temperature Co-efficient of Resistance (TCR) technique. Hypodermic thermocouples were also used for direct temperature measurement. Impact of different numbers of contact windows and different sizes of outer guard rings in the Ground Plane Silicon-on-Insulator (GPSOI) crosstalk suppression test structures were studied for the first 'time. Measurements, modelling and simulations were performed for a series of test structures in this work. An equivalent lumped circuit model for the test structure was developed for further investigation of crosstalk isolation. Conclusions were drawn that more contact windows on the GSG ground rails can generate better crosstalk reduction and that guard rings should have appropriate sizes and not be positioned far away from the devices in order to be effective on the crosstalk isolation.
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Lü, Liang. "Reconfigurable SoC architectures for video motion compensation". Thesis, Queen's University Belfast, 2008. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.491876.

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Research has been undertaken into domain-specific reconfigurable architectures for future System-on-Chip applications. In particular the focus has been on video compression systems with the objective o£developing systems suitable for most of the common video compression standards. An important aspect of the research presented is a new domain-specific architecture for real-time integer motion estimation (ME). This has been derived from a detailed investigation of the properties of custom ME architectures, with sharable and non-sharable sub-functions multiplexed onto a reconfigurable data-path which is programmable via data configuration lines. Design studies demonstrate that this architecture requires only slightly more power and silicon area to achieve a high degree of flexibility when compared with equivalent dedicated circuits. It also saves at least an order of magnitude of power consumption compared with an equivalent FPGA implementation. The architecture also provides higher throughput rates and smaller silicon area compared with the best dedicated designs to date for H.264 and AVS. This thesis also describes a new domain-specific reconfigurable sub-pixel interpolation architecture for multi-standard video coding systems. Flexibility has been achieved by using a: multiplexed reconfigurable data-path that allows the choice of different filter coefficients corresponding to different video standards. A detailed design study shows that this requires only a 6.6% overhead to cater for the most complex scenario - MPEG-4. Finally, a new real-time architecture for rate-distortion optimisation for detennining the best matching motion vector is proposed. In traditional methods, this is derived from a pre-defined look-up table whose size is inflexible once fabricated. The proposed real-time architecture calculates the value of this cost function. The design studies show that this approach saves approximately 26% of the silicon area when compared with the smallest look-up table implementations reported to date. Moreover, it is easily extended to larger motion search range with little increase in silicon area.
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Buitenga, John. "An embedded microcontroller core for SOC applications". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0032/MQ65868.pdf.

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Flynn, David Walter. "Energy-efficient SOC design technology and methodology". Thesis, Loughborough University, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.479318.

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Becker, Carlos André. "Detecção distribuída de falhas em SoC multiprocessado". Pontifícia Universidade Católica do Rio Grande do Sul, 2008. http://hdl.handle.net/10923/3207.

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Made available in DSpace on 2013-08-07T18:53:33Z (GMT). No. of bitstreams: 1 000404328-Texto+Completo-0.pdf: 3041840 bytes, checksum: 71eb19106ae512b0259919d42c2e2389 (MD5) Previous issue date: 2008
Increasing evolution in the microelectronic field within the last decades has resulted in an expansive growth of integration capacity of systems on a single chip, that has brought about the need for new technologies for analyzing the correct functioning of systems. Recently, new processor architectures have been observed moving from a single CPU (Central Processing Unit) to multiple cores (typically 2, 4 and 8 processors on a single chip). It is a scenario which evolves from mono electronic systems to multiprocessors that this paper lies, aiming at proposing an expansion of CFCSS (Control Flow Checking by Software Signatures) technique, which was developed by Edward J. McCluskey for monoprocessed systems, in a version applicable to systems with multiple processors in a single SoC (Systemon- Chip). This work is made of two parts. The first part presents taxonomy and basic concepts of fault-tolerating systems, followed by a bibliographical review of main techniques for detecting fault in software in monoprocessed systems, besides approaching reprogrammable technology evolution. The second part describes the development methodology for hardware and software platforms, as well the stages carried out and the difficulties found. In addition, it presents the CFCSS technique adapted to several processors, the communication protocol developed to carry out tests and the results obtained. This paper presents an innovative profile and is justified by the tendency of embedded systems to have, in the near future, multiple processors and applications being executed simultaneously.
A crescente evolução da área da microeletrônica nas últimas décadas acarretou um aumento expressivo da capacidade de integração de sistemas em um único chip, o que levou à necessidade de novas tecnologias para a análise do correto funcionamento dos sistemas. Observam-se, recentemente, novas arquiteturas de processadores, migrando de uma única CPU (Unidade Central de Processamento) para múltiplos núcleos (tipicamente, 2, 4 e 8 processadores em uma única pastilha). É neste cenário, que evolui de sistemas eletrônicos mono para multiprocessados, que este trabalho se insere, visando propor uma expansão da técnica CFCSS (Control Flow Checking by Software Signatures), desenvolvida por Edward J. McCluskey para sistemas monoprocessados, a uma versão aplicável a sistemas com vários processadores em um SoC (System-on-Chip). Quanto à sua estrutura, este trabalho constitui-se de duas partes. A primeira apresenta a taxonomia e os conceitos básicos de sistemas tolerantes a falhas e uma revisão bibliográfica das principais técnicas de detecção de falhas em software em sistemas monoprocessados, além de abordar a evolução da tecnologia reprogramável. A segunda parte descreve a metodologia de desenvolvimento das plataformas de hardware e de software, bem como as etapas realizadas e as dificuldades encontradas. Além disso, apresenta a técnica CFCSS adaptada a vários processadores, o protocolo de comunicação desenvolvido para a realização dos testes e os resultados obtidos. Assim, este trabalho demonstra caráter inovador e se justifica pela tendência de os sistemas embarcados possuírem, vários processadores e aplicações sendo executadas simultaneamente.
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Libros sobre el tema "SOC.045.040.001"

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Nāṣir, Naṣīr Aḥmad. Soc. Lāhaur: Fīrozsanz, 1989.

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Brym, Robert J. SOC+. Toronto: Nelson Education, 2012.

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Witt, Jon. SOC. 2a ed. New York: McGraw-Hill, 2012.

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Rāhī, Sājid. Soc samundar. Raḥīmyār K̲h̲ān: Sanjok Sirāʼīkī Adabī Sangat, 1994.

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ʻAyān̲, Rashīdah. Soc samandar. Karācī: al- Ḥasanāt Buk, 2006.

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Hazārah, Adabiyāt-i., ed. Soc mināre. Aibaṭābād: Adabiyāt-i Hazārah, 2009.

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Friedrich Wilhelm Joseph von Schelling. Soc inenija: [...]. Moskva: Izdat. Mysl £, 1989.

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Walter, Podilchak y University of Toronto. Dept. of Sociology., eds. SOC 202Y. [Toronto]: Custom Publishing Service, University of Toronto, 2002.

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ʻAlī, Nūrulʻain. Soc lījīʼe. Pūnah: Salīqah Kitāb Ghar, 1989.

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Jon, Witt, ed. Soc updated. 2a ed. New York: McGraw-Hill, 2010.

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Capítulos de libros sobre el tema "SOC.045.040.001"

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Chen, Jein-Shan. "SOC-Convexity and SOC-Monotonity". En Springer Optimization and Its Applications, 39–99. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-4077-2_2.

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Chen, Jein-Shan. "SOC Means and SOC Inequalities". En Springer Optimization and Its Applications, 159–88. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-4077-2_4.

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Chen, Jein-Shan. "SOC Functions". En Springer Optimization and Its Applications, 1–37. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-4077-2_1.

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Chakravarthi, Veena S. "SOC Packaging". En A Practical Approach to VLSI System on Chip (SoC) Design, 215–24. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-23049-4_11.

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Chakravarthi, Veena S. "SOC Constituents". En A Practical Approach to VLSI System on Chip (SoC) Design, 41–61. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-23049-4_3.

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Chakravarthi, Veena S. "SOC Synthesis". En A Practical Approach to VLSI System on Chip (SoC) Design, 81–97. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-23049-4_5.

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Taraate, Vaibbhav. "SOC Prototyping". En Advanced HDL Synthesis and SOC Prototyping, 197–210. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8776-9_11.

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Taraate, Vaibbhav. "SOC Design". En Advanced HDL Synthesis and SOC Prototyping, 17–24. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-8776-9_2.

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Chakravarthi, Veena S. "SoC Packaging". En A Practical Approach to VLSI System on Chip (SoC) Design, 215–28. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-18363-8_10.

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Chakravarthi, Veena S. "SoC Constituents". En A Practical Approach to VLSI System on Chip (SoC) Design, 37–57. Cham: Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-18363-8_3.

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Actas de conferencias sobre el tema "SOC.045.040.001"

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Leuschel, Michael, Marisa Llorens, Javier Oliver, Josep Silva y Salvador Tamarit. "SOC". En the 2009 ACM SIGPLAN workshop. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1480945.1480969.

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Ferri, Cesare, Andrea Marongiu, Benjamin Lipton, R. Iris Bahar, Tali Moreshet, Luca Benini y Maurice Herlihy. "SoC-TM". En the seventh IEEE/ACM/IFIP international conference. New York, New York, USA: ACM Press, 2011. http://dx.doi.org/10.1145/2039370.2039380.

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Reid, Alastair D., Krisztian Flautner, Edmund Grimley-Evans y Yuan Lin. "SoC-C". En the 2008 international conference. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1450095.1450112.

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Marangozova-Martin, Vania y Generoso Pagano. "SoC-TRACE". En the Posters and Demo Track. New York, New York, USA: ACM Press, 2012. http://dx.doi.org/10.1145/2405153.2405163.

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Nguyen, Tan, Swathi Gurumani, Kyle Rupnow y Deming Chen. "FCUDA-SoC". En FPGA'16: The 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. New York, NY, USA: ACM, 2016. http://dx.doi.org/10.1145/2847263.2847344.

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Nieuwoudt, Arthur, Tamer Ragheb y Yehia Massoud. "SOC-NLNA". En the 43rd annual conference. New York, New York, USA: ACM Press, 2006. http://dx.doi.org/10.1145/1146909.1147133.

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Moch, S., M. Bereković, H. J. Stolberg, L. Friebe, M. B. Kulaczewski, A. Dehnhardt y P. Pirsch. "HIBRID-SOC". En the 2003 workshop. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/1152923.1024303.

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Cho, Hsun-Wei y Kang G. Shin. "Unify: Turning BLE/FSK SoC into WiFi SoC". En ACM MobiCom '23: 29th Annual International Conference on Mobile Computing and Networking. New York, NY, USA: ACM, 2023. http://dx.doi.org/10.1145/3570361.3592512.

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Marshall, Andrew. "Advanced SoC components". En 2016 29th IEEE International System-on-Chip Conference (SOCC). IEEE, 2016. http://dx.doi.org/10.1109/socc.2016.7905479.

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Vladimir, Hahanov, Litvinova Eugenia y Pobezhenko Irina. "SOC verification infrastructure". En 2010 IEEE Region 8 International Conference on "Computational Technologies in Electrical and Electronics Engineering" (SIBIRCON 2010). IEEE, 2010. http://dx.doi.org/10.1109/sibircon.2010.5555318.

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Informes sobre el tema "SOC.045.040.001"

1

Van Dyke, Anthony E. MEU(SOC) and CINC's. Fort Belvoir, VA: Defense Technical Information Center, febrero de 1993. http://dx.doi.org/10.21236/ada264141.

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Hicks, Jacqueline. The Role of Gender in Serious and Organised/Transnational Crime. Institute of Development Studies, marzo de 2021. http://dx.doi.org/10.19088/k4d.2021.059.

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Resumen
This rapid review synthesises evidence on the role of gender in serious and organised/transnational crime (SOC) with regard to gender norms, participation and prevention. It looks at the literature on the roles women play in organised crime groups and their pathways to participation, the impact of cultural gender norms in different forms of participation for men and women in SOC, and the role of gender dynamics within families or communities in preventing SOC. Key Overall Findings linking gender norms, female participation and prevention of SOC: 1). Gender norms and women’s participation in SOC are varied and highly contextual, highlighting the importance of gender analysis to programming; 2). Gendered perceptions of men as perpetrators and women as victims in SOC undermine effective responses; and 3). Some types of masculine identity have been linked to involvement in violent crime and societal tolerance of organised crime groups. In Italy, some feminists characterise opposition to SOC as an anti-patriarchal struggle.
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Cooperider, Stephen B. Expanding the MEU(SOC) Joint Task Force Enabler Concept. Fort Belvoir, VA: Defense Technical Information Center, mayo de 1998. http://dx.doi.org/10.21236/ada529533.

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4

NATURESERVE ARLINGTON VA. Species of Concern (SOC) on Department of Defense Installations. Fort Belvoir, VA: Defense Technical Information Center, julio de 2002. http://dx.doi.org/10.21236/ada541486.

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5

Herndon, Timothy A. Training the MEU(SOC) ACE Commander: Making a MAGTF Officer. Fort Belvoir, VA: Defense Technical Information Center, enero de 1997. http://dx.doi.org/10.21236/ada529536.

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Kalkhoff, Bryan. Emulating Control-Flow and Memory Bus Attacks on an FPGA SoC. Ames (Iowa): Iowa State University, diciembre de 2021. http://dx.doi.org/10.31274/cc-20240624-617.

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Laguna Sánchez, Gerardo Abel y Jacobo Sandoval Gutiérrez. Reporte de investigación: Empleo del trans-receptor AD936x y una plataforma SoC, como banco de pruebas, para el desarrollo de aplicaciones Software Defined Radio. División de Ciencias Básicas e Ingeniería, noviembre de 2020. http://dx.doi.org/10.24275/uaml.ri.0001.

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Gu, Zu Han y Alexei A. Maradudin. A Proposal for the Purchase of SOC-500 Laser Interferometric Monostatic Reflectometer. Fort Belvoir, VA: Defense Technical Information Center, mayo de 2001. http://dx.doi.org/10.21236/ada394044.

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9

Rankin, John J. MEU(SOC)s in the 21st Century: Will They Be Capable of Conducting Humanitarian Operations. Fort Belvoir, VA: Defense Technical Information Center, mayo de 1997. http://dx.doi.org/10.21236/ada328107.

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10

Bando, Atsushi. Rapid Analysis Technology of SOC (Substance of Concern) Corresponding to the ELV Directive in Europe. Warrendale, PA: SAE International, mayo de 2005. http://dx.doi.org/10.4271/2005-08-0185.

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