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Artículos de revistas sobre el tema "Sigma-delta continuous-time bandpass modulator"

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Publicado: 25 de mayo de 2024

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1

Lima, Evelyn Cristina de Oliveira, Antonio Wallace Antunes Soares y Diomadson Rodrigues Belfort. "4th Order LC-Based Sigma Delta Modulators". Sensors 22, n.º 22 (18 de noviembre de 2022): 8915. http://dx.doi.org/10.3390/s22228915.

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Due to the characteristic of narrow band conversion around a central radio frequency, the Sigma Delta Modulator (ΣΔM) based on LC resonators is a suitable option for use in Software-Defined Radio (SDR). However, some aspects of the topologies described in the state-of-the-art, such as noise and nonlinear sources, affect the performance of ΣΔM. This paper presents the design methodology of three high-order LC-Based single-block Sigma Delta Modulators. The method is based on the equivalence between continuous time and discrete time loop gain using a Finite Impulse Response Digital-to-Analog Converter (FIRDAC) through a numerical approach to defining the coefficients. The continuous bandpass LC ΣΔM simulations are performed at a center frequency of 432 MHz and a sampling frequency of 1.72 GHz. To the proposed modulators a maximum Signal-to-Noise Ratio (SNR) of 51.39 dB, 48.48 dB, and 46.50 dB in a 4 MHz bandwidth was achieved to respectively 4th Order Gm-LC ΣΔM, 4th Order Magnetically Coupled ΣΔM and 4th Order Capacitively Coupled ΣΔM.
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2

Pulincherry, A., M. Hufford, E. Naviasky y Un-Ku Moon. "A time-delay jitter-insensitive continuous-time bandpass /spl Delta//spl Sigma/ modulator architecture". IEEE Transactions on Circuits and Systems II: Express Briefs 52, n.º 10 (octubre de 2005): 680–84. http://dx.doi.org/10.1109/tcsii.2005.850746.

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3

Matsuura, Koji y Takao Waho. "Design of a continuous-timeGm-C bandpass Delta-Sigma modulator". Electronics and Communications in Japan (Part II: Electronics) 87, n.º 3 (2004): 39–44. http://dx.doi.org/10.1002/ecjb.10168.

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4

Van Engelen, J. A. E. P., R. J. Van De Plassche, E. Stikvoort y A. G. Venes. "A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF". IEEE Journal of Solid-State Circuits 34, n.º 12 (1999): 1753–64. http://dx.doi.org/10.1109/4.808900.

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5

Javidan, Mohammad, Jerome Juillard y Philippe Benabes. "High‐loop‐delay sixth‐order bandpass continuous‐time sigma–delta modulators". IET Circuits, Devices & Systems 7, n.º 6 (noviembre de 2013): 305–12. http://dx.doi.org/10.1049/iet-cds.2011.0313.

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6

Ju, Chunge, Xiang Li, Junjun Zou, Qi Wei, Bin Zhou y Rong Zhang. "An Auto-Tuning Continuous-Time Bandpass Sigma-Delta Modulator with Signal Observation for MEMS Gyroscope Readout Systems". Sensors 20, n.º 7 (1 de abril de 2020): 1973. http://dx.doi.org/10.3390/s20071973.

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This paper presents the design and implementation of an auto-tuning continuous-time bandpass sigma-delta (ΣΔ) modulator for micro-electromechchanical systems (MEMS) gyroscope readout systems. Its notch frequency can well match the input signal frequency by adding a signal observation to the traditional ΣΔ modulator. The filter of the observation adopts the same architecture as that of the traditional ΣΔ modulator, allowing the two filters to have the same response to input signal change, which is converted into a control voltage on metal-oxide semiconductor (MOS) resistance in the filters. The automatic tuning not only works to solve the mismatch problem caused by process error and temperature variation, but can also be applied to the interface circuit of gyroscopes with different resonant frequencies. The circuit is implemented in a 0.18-μm complementary metal-oxide semiconductor (CMOS) process with a core area of 2.4 mm2. The improved modulator achieves a dynamic range of 106 dB, a noise floor below 120 dB and a maximum signal-to-noise and distortion ratio (SNDR) of 86.4 dB. The tuning capability of the chip is relatively stable under input signals from 6 to 15 kHz at temperatures ranging from −45 to 60 °C.
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7

Song-Bok Kim, M. Robens, S. Joeres, R. Wunderlich y S. Heinen. "A Polyphase Filter Design for Continuous-Time Quadrature Bandpass Sigma–Delta Modulators". IEEE Transactions on Circuits and Systems I: Regular Papers 55, n.º 11 (diciembre de 2008): 3457–68. http://dx.doi.org/10.1109/tcsi.2008.925352.

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8

Sobot, R., S. Stapleton y M. Syrzycki. "Tunable continuous-time bandpass /spl Sigma//spl Delta/ modulators with fractional delays". IEEE Transactions on Circuits and Systems I: Regular Papers 53, n.º 2 (febrero de 2006): 264–73. http://dx.doi.org/10.1109/tcsi.2005.857085.

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9

Molina-Salgado, Gerardo, Alonso Morgado, Gordana Jovanovic Dolecek y Jose M. de la Rosa. "LC-Based Bandpass Continuous-Time Sigma-Delta Modulators With Widely Tunable Notch Frequency". IEEE Transactions on Circuits and Systems I: Regular Papers 61, n.º 5 (mayo de 2014): 1442–55. http://dx.doi.org/10.1109/tcsi.2013.2289412.

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10

Jiang, Dongyang, Sai‐Weng Sin, Seng‐Pan U, Rui Paulo Martins y Franco Maloberti. "Reconfigurable mismatch‐free time‐interleaved bandpass sigma–delta modulator for wireless communications". Electronics Letters 53, n.º 7 (marzo de 2017): 506–8. http://dx.doi.org/10.1049/el.2016.4623.

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11

Raghavan, G., J. F. Jensen, J. Laskowski, M. Kardos, M. G. Case, M. Sokolich y S. Thomas. "Architecture, design, and test of continuous-time tunable intermediate-frequency bandpass delta-sigma modulators". IEEE Journal of Solid-State Circuits 36, n.º 1 (2001): 5–13. http://dx.doi.org/10.1109/4.896223.

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12

Bernardinis, G., F. Borghetti, V. Ferragina, A. Fornasari, U. Gatti, P. Malcovati y F. Maloberti. "A wide-band 280-MHz four-path time-interleaved bandpass sigma-delta modulator". IEEE Transactions on Circuits and Systems I: Regular Papers 53, n.º 7 (julio de 2006): 1423–32. http://dx.doi.org/10.1109/tcsi.2006.875191.

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13

Henkel, F., U. Langmann, A. Hanke, S. Heinen y E. Wagner. "A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers". IEEE Journal of Solid-State Circuits 37, n.º 12 (diciembre de 2002): 1628–35. http://dx.doi.org/10.1109/jssc.2002.804332.

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14

Ho, Chen-Yen, Wei-Shan Chan, Yung-Yu Lin y Tsung-Hsien Lin. "A Quadrature Bandpass Continuous-Time Delta-Sigma Modulator for a Tri-Mode GSM-EDGE/UMTS/DVB-T Receiver". IEEE Journal of Solid-State Circuits 46, n.º 11 (noviembre de 2011): 2571–82. http://dx.doi.org/10.1109/jssc.2011.2164026.

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15

Naderi, A., M. Sawan y Y. Savaria. "On the Design of Undersampling Continuous-Time Bandpass Delta–Sigma Modulators for Gigahertz Frequency A/D Conversion". IEEE Transactions on Circuits and Systems I: Regular Papers 55, n.º 11 (diciembre de 2008): 3488–99. http://dx.doi.org/10.1109/tcsi.2008.925364.

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16

Afifi, M., Y. Manoli y M. Keller. "A study of excess loop delay in tunable continuous-time bandpass delta–sigma modulators using RC-resonators". Analog Integrated Circuits and Signal Processing 79, n.º 3 (10 de abril de 2014): 555–68. http://dx.doi.org/10.1007/s10470-014-0294-0.

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17

Chanyong Jeong, Yonghwan Kim y Soowon Kim. "Efficient Discrete-Time Bandpass Sigma-Delta Modulator and Digital I/Q Demodulator for Multistandard Wireless Applications". IEEE Transactions on Consumer Electronics 54, n.º 1 (febrero de 2008): 25–32. http://dx.doi.org/10.1109/tce.2008.4470019.

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18

Kwon, Minho y Gunhee Han. "An I/Q-Channel Time-Interleaved Bandpass Sigma–Delta Modulator for a Low-IF Receiver". IEEE Transactions on Circuits and Systems II: Express Briefs 54, n.º 3 (marzo de 2007): 252–56. http://dx.doi.org/10.1109/tcsii.2006.888726.

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19

Zhang, Junfeng, Yang Xu, Zehong Zhang, Yichuang Sun, Zhihua Wang y Baoyong Chi. "A 10-b Fourth-Order Quadrature Bandpass Continuous-Time $\Sigma \Delta $ Modulator With 33-MHz Bandwidth for a Dual-Channel GNSS Receiver". IEEE Transactions on Microwave Theory and Techniques 65, n.º 4 (abril de 2017): 1303–14. http://dx.doi.org/10.1109/tmtt.2017.2662378.

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20

Kim, Song-Bok, Stefan Joeres, Ralf Wunderlich y Stefan Heinen. "A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 $\mu$m CMOS". IEEE Journal of Solid-State Circuits 44, n.º 3 (marzo de 2009): 891–900. http://dx.doi.org/10.1109/jssc.2008.2012367.

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21

VERNIK, IGOR V. "ULTRASENSITIVE WIDEBAND INTEGRATED SPECTROMETER FOR CHEMICAL AND BIOLOGICAL AGENT DETECTION". International Journal of High Speed Electronics and Systems 18, n.º 01 (marzo de 2008): 87–98. http://dx.doi.org/10.1142/s0129156408005163.

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A novel concept of a compact mm/submm integrated spectrometers for environmental monitoring for hazardous materials of chemical and biological origin as well as for remote monitoring of the Earth atmosphere is discussed. The agents will be exactly identified by their unique spectral signatures. The assembled on a multi-chip module, cryocooler-mounted Superconducting Integrated SPectromer (SISP) exploits the superior performance of superconducting Josephson junction technology and unique on-chip integration of analog components, analog-to-digital converter, and digital components. Analog components include a superconductor-insulator-superconductor (SIS) mixer with integrated quasioptical antenna, mm-wave local oscillator, and SQUID amplifier for the down-converted (IF) signals. Upon amplification, the IF signal is digitized using a bandpass delta-sigma modulator, followed by real time processing with rapid single flux quantum (RSFQ) circuitry. Experimental results showing both operation of spectrometer components and the way to their successful integration are presented.
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22

Kim, Song-Bok. "Correction to “A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 $\mu$m CMOS” [Mar 09 891-900]". IEEE Journal of Solid-State Circuits 44, n.º 6 (junio de 2009): 1853. http://dx.doi.org/10.1109/jssc.2009.2021901.

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23

Le Guillou, Y. y H. Fakhoury. "Elliptic filtering in continuous-time sigma-delta modulator". Electronics Letters 41, n.º 4 (2005): 167. http://dx.doi.org/10.1049/el:20057874.

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24

Fakhoury, Hussein, Chadi Jabbour y Van-Tam Nguyen. "A 40 MHz 11-Bit ENOB Delta Sigma ADC for Communication and Acquisition Systems". Sensors 23, n.º 1 (20 de diciembre de 2022): 36. http://dx.doi.org/10.3390/s23010036.

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This paper describes a Delta Sigma ADC IC that embeds a 5th-order Continuous-Time Delta Sigma modulator with 40 MHz signal bandwidth, a low ripple 20 to 80 MS/s variable-rate digital decimation filter, a bandgap voltage reference, and high-speed CML buffers on a single die. The ADC also integrates on-chip calibrations for RC time-constant variation and quantizer offset. The chip was fabricated in a 1P7M 65 nm CMOS process. Clocked at 640 MHz, the Continuous-Time Delta Sigma modulator achieves 11-bit ENOB and 76.5 dBc THD up to 40 MHz of signal bandwidth while consuming 82.3 mW.
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25

Tamaddon, Mohsen y Mohammad Yavari. "An NTF-enhanced time-based continuous-time sigma-delta modulator". Analog Integrated Circuits and Signal Processing 85, n.º 2 (24 de mayo de 2015): 283–97. http://dx.doi.org/10.1007/s10470-015-0562-7.

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26

Xiong, Jiu, Jin Liu y Hoi Lee. "A Continuous-Time Sigma-Delta Modulator With Continuous-Time Delay-Based Integrator". IEEE Transactions on Circuits and Systems II: Express Briefs 69, n.º 3 (marzo de 2022): 914–18. http://dx.doi.org/10.1109/tcsii.2021.3127024.

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27

Zorn, C., T. Brückner, M. Ortmanns y W. Mathis. "State scaling of continuous-time sigma-delta modulators". Advances in Radio Science 11 (4 de julio de 2013): 119–23. http://dx.doi.org/10.5194/ars-11-119-2013.

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Abstract. In this paper, the common method of scaling the feedback coefficients of continuous time sigma delta modulators in order to stabilize the system is enhanced. The presented approach scales the different states of the system instead of the coefficients. The new corresponding coefficients are then calculated from the solution of the state space description. Therewith, it is possible to tune the maximum out-of-band gain directly in continuous time. In addition, the input amplitude distribution between each quantization level of multi bit sigma-delta modulator can be adapted.
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28

Lee, Kwangchun, Bonghyuk Park, Seunghyun Jang, Jaeho Jung y Kyoungrok Cho. "Tunable continuous-time ^|^Delta;^|^Sigma; modulator for switching power amplifier". IEICE Electronics Express 9, n.º 22 (2012): 1714–19. http://dx.doi.org/10.1587/elex.9.1714.

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29

Colodro, F., A. Torralba y M. Laguna. "Continuous-Time Sigma–Delta Modulator With an Embedded Pulsewidth Modulation". IEEE Transactions on Circuits and Systems I: Regular Papers 55, n.º 3 (abril de 2008): 775–85. http://dx.doi.org/10.1109/tcsi.2008.919764.

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30

Ucar, Alper, Ediz Cetin y Izzet Kale. "A Continuous-Time Delta-Sigma Modulator for RF Subsampling Receivers". IEEE Transactions on Circuits and Systems II: Express Briefs 59, n.º 5 (mayo de 2012): 272–76. http://dx.doi.org/10.1109/tcsii.2012.2190860.

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31

Chavoshisani, Reza y Omid Hashemipour. "Low Power Current Conveyor Based Continuous Time Sigma Delta Modulator". Journal of Low Power Electronics 13, n.º 2 (1 de junio de 2017): 249–54. http://dx.doi.org/10.1166/jolpe.2017.1481.

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32

Zhao, Feng, Hong Gao, Lin Xing, Yasunori Kobori, Shu Wu, Haruo Kobayashi, Shyunsuke Miwa, Atsushi Motozawa, Zachary Nosker y Nobukazu Takai. "Continuous-Time Delta-Sigma Controller for DC-DC Converter". Key Engineering Materials 643 (mayo de 2015): 53–59. http://dx.doi.org/10.4028/www.scientific.net/kem.643.53.

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This paper describes applications of a Delta-Sigma (ΔΣ) modulator to control a DC-DC converter. We propose to use a continuous-time (CT) feed-forward (FF) ΔΣ controller in a DC-DC converter and show that its transient response is faster than discrete-time (DT) and/or feedback-type (FB) ΔΣ controllers. We have also performed experiments of a DC-DC converter with a first-order continuous-time feedback ΔΣ controller and show its results.
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33

Keller, M., A. Buhmann, M. Kuderer y Y. Manoli. "On the synthesis and optimization of cascaded continuous-time Sigma-Delta modulators". Advances in Radio Science 4 (6 de septiembre de 2006): 293–97. http://dx.doi.org/10.5194/ars-4-293-2006.

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Abstract. Up to now, there exist two completely different approaches for the synthesis of cascaded CT Sigma-Delta modulators. While the first method is based on a DT prototype and thus on the application of a DT-to-CT transformation, the second one is entirely performed in the CT domain. In this contribution, the method of lifting will be applied to overcome the disadvantages afflicted with the first method (e.g. less ideal anti-aliasing filter performance, increased circuit complexity) and to establish a time efficient DT simulation model for the second method. Thereby, optimal modulator coefficients as well as optimal digital cancellation filters for an arbitrary cascaded CT modulator can be simulated in an efficient and rapid manner. For illustrative purposes, the complete synthesis procedure is demonstrated by the example of a 2-1-1 cascaded CT modulator.
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34

Gupta, Anshu, Lalita Gupta y R. K. Baghel. "Low Power Continuous-Time Delta-Sigma Modulators Using the Three Stage OTA and Dynamic Comparator". International Journal of Engineering & Technology 7, n.º 2.16 (12 de abril de 2018): 38. http://dx.doi.org/10.14419/ijet.v7i2.16.11413.

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A second-order sigma delta modulator that uses an operational transconductance amplifier as integrator and latch comparator as quantizer. The proposed technique where a low power high gain OTA is used as integrator and another circuit called dynamic latch comparator with two tail transistors and two controlling switches are used to achieve high speed, low power and high resolution in second order delta sigma modulator. It enhances the power efficiency and compactness of the modulator by implementing these blocks as sub modules. A second order modulator has been designed to justify the effectiveness of the proposed design. Technology 180nm CMOS process is used to implement complete second order continuous time sigma delta modulator. We introduce the sub threshold three stage OTA, which is a way of achieving low distortion operation with input referred noise at 1 KHz is equal to the 2.2647pV/ and with low power consumption of 296.72nW. A high-speed, low-voltage and a low-power Double-Tail dynamic comparator is also proposed. The proposed structure is contrasted with past dynamic comparators. In this paper, the comparator’s delay will be investigated and systematic analysis are inferred. a novel comparator using two tail transistor is proposed, here circuitry of a customized comparator having two tail is changed for low power dissipation and also it operates fast at little supply voltages. By maintaining the outline and by including couple of transistors, during the regeneration strengthening of positive feedback can be maintained, this results in amazingly diminished delay parameter. It is investigated that in proposed design structure of comparator using two tail transistors, power consumption is reduced and delay time is also diminished to a great extent. The proposed comparator is having maximum clock frequency that is possibly expanded up to 1GHz at voltages of 1 V whereas it is dissipating 10.99 µW of power, individually. By using sub threshold three stage OTA and dynamic standard two tail latch comparator, designed second order sigma delta ADC will consume 29.95µW of power.
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35

Pavan, Shanthi. "Continuous-Time Delta-Sigma Modulator Design Using the Method of Moments". IEEE Transactions on Circuits and Systems I: Regular Papers 61, n.º 6 (junio de 2014): 1629–37. http://dx.doi.org/10.1109/tcsi.2013.2290846.

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36

Taylor, Gerry y Ian Galton. "A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC". IEEE Journal of Solid-State Circuits 45, n.º 12 (diciembre de 2010): 2634–46. http://dx.doi.org/10.1109/jssc.2010.2073193.

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37

Cai, H., H. Petit y J. F. Naviner. "Reliability aware design of low power continuous-time sigma–delta modulator". Microelectronics Reliability 51, n.º 9-11 (septiembre de 2011): 1449–53. http://dx.doi.org/10.1016/j.microrel.2011.06.054.

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38

Hernández, L., E. Pun, E. Prefasi y S. Paton. "Continuous time sigma-delta modulator based on binary weighted charge balance". Electronics Letters 45, n.º 9 (2009): 458. http://dx.doi.org/10.1049/el.2009.0323.

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39

Matsukawa, Kazuo, Yosuke Mitani, Masao Takayama, Koji Obata, Shiro Dosho y Akira Matsuzawa. "A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator". IEEE Journal of Solid-State Circuits 45, n.º 4 (abril de 2010): 697–706. http://dx.doi.org/10.1109/jssc.2010.2042244.

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40

Yoon, Do-Yeon, Stacy Ho y Hae-Seung Lee. "A Continuous-Time Sturdy-MASH $\Delta\Sigma$ Modulator in 28 nm CMOS". IEEE Journal of Solid-State Circuits 50, n.º 12 (diciembre de 2015): 2880–90. http://dx.doi.org/10.1109/jssc.2015.2466459.

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41

Anand, Awinash, Nischal Koirala, Ramesh K. Pokharel, Haruichi Kanaya y Keiji Yoshida. "Systematic Design Methodology of a Wideband Multibit Continuous-Time Delta-Sigma Modulator". International Journal of Microwave Science and Technology 2013 (7 de marzo de 2013): 1–5. http://dx.doi.org/10.1155/2013/275289.

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Systematic design of a low power, wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented. The design methodology is illustrated with a 640 MS/s, 20 MHz signal bandwidth 4th order 2-bit CTDMS implemented in 0.18 µm CMOS technology. The implemented design achieves a peak SNDR of 65.7 dB and a high dynamic range of 70 dB while consuming only 19.7 mW from 1.8 V supply. The design achieves a FoM of 0.31 pJ/conv. Direct path compensation is employed for one clock excess loop delay compensation. In the feedforward topology, capacitive summation using the last opamp eliminates extra summation opamp.
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42

Cai, Hao, You Wang, Kaikai Liu, Lirida Alves de Barros Naviner, Hervé Petit y Jean-François Naviner. "Cross-layer investigation of continuous-time sigma–delta modulator under aging effects". Microelectronics Reliability 55, n.º 3-4 (febrero de 2015): 645–53. http://dx.doi.org/10.1016/j.microrel.2014.11.015.

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43

Jeong, Donghyeok y Changsik Yoo. "Voltage-controlled-oscillator based Continuous-time Sigma-delta Modulator Analog-to-digital Converter". Journal of the Institute of Electronics and Information Engineers 58, n.º 4 (30 de abril de 2021): 32–39. http://dx.doi.org/10.5573/ieie.2021.58.4.32.

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44

Pakniat, Hossein. "Five‐level class‐D amplifier employing fourth‐order continuous‐time sigma‐delta modulator". Electronics Letters 57, n.º 4 (20 de enero de 2021): 175–78. http://dx.doi.org/10.1049/ell2.12004.

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45

Gonzalez-Diaz, Victor R. y Fabio Pareschi. "A 65nm Continuous-Time Sigma-Delta Modulator With Limited OTA DC Gain Compensation". IEEE Access 8 (2020): 36464–75. http://dx.doi.org/10.1109/access.2020.2975601.

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46

Ding, HaiTao, ZhenChuan Yang, ZhanFei Wang, Michael Kraft y GuiZhen Yan. "MEMS gyroscope control system using a band-pass continuous-time sigma-delta modulator". Science China Information Sciences 56, n.º 10 (28 de septiembre de 2012): 1–10. http://dx.doi.org/10.1007/s11432-012-4670-z.

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47

Mariano, A., D. Dallet, Y. Deval y J. B. Bégueret. "Top-down design methodology of a multi-bit continuous-time delta–sigma modulator". Analog Integrated Circuits and Signal Processing 60, n.º 1-2 (25 de julio de 2008): 145–53. http://dx.doi.org/10.1007/s10470-008-9206-5.

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48

He, Xiao-yong, Kong-pang Pun, Siu-kei Tang, Chiu-sing Choy y Peter Kinget. "A 0.5 V 65.7 dB 1 MHz continuous-time complex delta sigma modulator". Analog Integrated Circuits and Signal Processing 66, n.º 2 (28 de agosto de 2010): 255–67. http://dx.doi.org/10.1007/s10470-010-9530-4.

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49

Yan, Haiyue, Lin He, Yan Ye y Fujiang Lin. "A second-order continuous-time delta-sigma modulator with double self noise coupling". Analog Integrated Circuits and Signal Processing 99, n.º 2 (20 de febrero de 2019): 251–59. http://dx.doi.org/10.1007/s10470-019-01425-x.

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Silva-Rivas, F., C. Y. Lu, P. Kode, B. K. Thandri y J. Silva-Martinez. "Digital based calibration technique for continuous-time bandpass sigma-delta analog-to-digital converters". Analog Integrated Circuits and Signal Processing 59, n.º 1 (27 de noviembre de 2008): 91–95. http://dx.doi.org/10.1007/s10470-008-9240-3.

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