Bibliografías temáticas / Sigma-delta continuous-time bandpass modulator

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Literatura académica sobre el tema "Sigma-delta continuous-time bandpass modulator"

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Publicado: 25 de mayo de 2024

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Artículos de revistas sobre el tema "Sigma-delta continuous-time bandpass modulator"

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Lima, Evelyn Cristina de Oliveira, Antonio Wallace Antunes Soares y Diomadson Rodrigues Belfort. "4th Order LC-Based Sigma Delta Modulators". Sensors 22, n.º 22 (18 de noviembre de 2022): 8915. http://dx.doi.org/10.3390/s22228915.

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Due to the characteristic of narrow band conversion around a central radio frequency, the Sigma Delta Modulator (ΣΔM) based on LC resonators is a suitable option for use in Software-Defined Radio (SDR). However, some aspects of the topologies described in the state-of-the-art, such as noise and nonlinear sources, affect the performance of ΣΔM. This paper presents the design methodology of three high-order LC-Based single-block Sigma Delta Modulators. The method is based on the equivalence between continuous time and discrete time loop gain using a Finite Impulse Response Digital-to-Analog Converter (FIRDAC) through a numerical approach to defining the coefficients. The continuous bandpass LC ΣΔM simulations are performed at a center frequency of 432 MHz and a sampling frequency of 1.72 GHz. To the proposed modulators a maximum Signal-to-Noise Ratio (SNR) of 51.39 dB, 48.48 dB, and 46.50 dB in a 4 MHz bandwidth was achieved to respectively 4th Order Gm-LC ΣΔM, 4th Order Magnetically Coupled ΣΔM and 4th Order Capacitively Coupled ΣΔM.
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Pulincherry, A., M. Hufford, E. Naviasky y Un-Ku Moon. "A time-delay jitter-insensitive continuous-time bandpass /spl Delta//spl Sigma/ modulator architecture". IEEE Transactions on Circuits and Systems II: Express Briefs 52, n.º 10 (octubre de 2005): 680–84. http://dx.doi.org/10.1109/tcsii.2005.850746.

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Matsuura, Koji y Takao Waho. "Design of a continuous-timeGm-C bandpass Delta-Sigma modulator". Electronics and Communications in Japan (Part II: Electronics) 87, n.º 3 (2004): 39–44. http://dx.doi.org/10.1002/ecjb.10168.

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Van Engelen, J. A. E. P., R. J. Van De Plassche, E. Stikvoort y A. G. Venes. "A sixth-order continuous-time bandpass sigma-delta modulator for digital radio IF". IEEE Journal of Solid-State Circuits 34, n.º 12 (1999): 1753–64. http://dx.doi.org/10.1109/4.808900.

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Javidan, Mohammad, Jerome Juillard y Philippe Benabes. "High‐loop‐delay sixth‐order bandpass continuous‐time sigma–delta modulators". IET Circuits, Devices & Systems 7, n.º 6 (noviembre de 2013): 305–12. http://dx.doi.org/10.1049/iet-cds.2011.0313.

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Ju, Chunge, Xiang Li, Junjun Zou, Qi Wei, Bin Zhou y Rong Zhang. "An Auto-Tuning Continuous-Time Bandpass Sigma-Delta Modulator with Signal Observation for MEMS Gyroscope Readout Systems". Sensors 20, n.º 7 (1 de abril de 2020): 1973. http://dx.doi.org/10.3390/s20071973.

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This paper presents the design and implementation of an auto-tuning continuous-time bandpass sigma-delta (ΣΔ) modulator for micro-electromechchanical systems (MEMS) gyroscope readout systems. Its notch frequency can well match the input signal frequency by adding a signal observation to the traditional ΣΔ modulator. The filter of the observation adopts the same architecture as that of the traditional ΣΔ modulator, allowing the two filters to have the same response to input signal change, which is converted into a control voltage on metal-oxide semiconductor (MOS) resistance in the filters. The automatic tuning not only works to solve the mismatch problem caused by process error and temperature variation, but can also be applied to the interface circuit of gyroscopes with different resonant frequencies. The circuit is implemented in a 0.18-μm complementary metal-oxide semiconductor (CMOS) process with a core area of 2.4 mm2. The improved modulator achieves a dynamic range of 106 dB, a noise floor below 120 dB and a maximum signal-to-noise and distortion ratio (SNDR) of 86.4 dB. The tuning capability of the chip is relatively stable under input signals from 6 to 15 kHz at temperatures ranging from −45 to 60 °C.
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Song-Bok Kim, M. Robens, S. Joeres, R. Wunderlich y S. Heinen. "A Polyphase Filter Design for Continuous-Time Quadrature Bandpass Sigma–Delta Modulators". IEEE Transactions on Circuits and Systems I: Regular Papers 55, n.º 11 (diciembre de 2008): 3457–68. http://dx.doi.org/10.1109/tcsi.2008.925352.

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Sobot, R., S. Stapleton y M. Syrzycki. "Tunable continuous-time bandpass /spl Sigma//spl Delta/ modulators with fractional delays". IEEE Transactions on Circuits and Systems I: Regular Papers 53, n.º 2 (febrero de 2006): 264–73. http://dx.doi.org/10.1109/tcsi.2005.857085.

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Molina-Salgado, Gerardo, Alonso Morgado, Gordana Jovanovic Dolecek y Jose M. de la Rosa. "LC-Based Bandpass Continuous-Time Sigma-Delta Modulators With Widely Tunable Notch Frequency". IEEE Transactions on Circuits and Systems I: Regular Papers 61, n.º 5 (mayo de 2014): 1442–55. http://dx.doi.org/10.1109/tcsi.2013.2289412.

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Jiang, Dongyang, Sai‐Weng Sin, Seng‐Pan U, Rui Paulo Martins y Franco Maloberti. "Reconfigurable mismatch‐free time‐interleaved bandpass sigma–delta modulator for wireless communications". Electronics Letters 53, n.º 7 (marzo de 2017): 506–8. http://dx.doi.org/10.1049/el.2016.4623.

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Tesis sobre el tema "Sigma-delta continuous-time bandpass modulator"

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Yang, Xi S. M. Massachusetts Institute of Technology. "Design of a continuous-time bandpass delta-sigma modulator". Thesis, Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/87939.

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Thesis: S.M., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2014.
Cataloged from PDF version of thesis.
Includes bibliographical references (pages 103-105).
An 8th-order continuous-time (CT) bandpass delta-sigma modulator has been designed and simulated in a 65 nm CMOS process. This modulator achieves in simulation 25 MHz signal bandwidth at 250 MHz center frequency with a signal-to- noise ratio (SNR) of 75.5 dB. The modulator samples at 1 GS/s while consuming 319 mW. On the system level, the feedback topology secures stability for the 8th-order system, achieving a maximum stable input range of -1.9 dBFS. A 2.5-V/1.2-V dual-supply loop filter with a feed-forward coupling path has been proposed to suppress noise and distortion. On the transistor level, a 5th -order dual-supply feed-forward operational amplifier (op amp) and a 4th-order single-supply feed-forward op amp have been designed to enable high modulator linearity and coefficient accuracy.
by Xi Yang.
S.M.
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2

Liu, Xuemei. "Design of a 125 mhz tunable continuous-time bandpass modulator for wireless IF applications". Texas A&M University, 2004. http://hdl.handle.net/1969.1/3257.

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Bandpass sigma-delta modulators combine oversampling and noise shaping to get very high resolution in a limited bandwidth. They are widely used in applications that require narrowband high-resolution conversion at high frequencies. In recent years interests have been seen in wireless system and software radio using sigma-delta modulators to digitize signals near the front end of radio receivers. Such applications necessitate clocking the modulators at a high frequency (MHz or above). Therefore a loop filter is required in continuous-time circuits (e.g., using transconductors and integrators) rather than discretetime circuits (e.g., using switched capacitors) where the maximum clocking rate is limited by the bandwidth of Opamp, switch’s speed and settling-time of the circuitry. In this work, the design of a CMOS fourth-order bandpass sigma-delta modulator clocking at 500 MHz for direct conversion of narrowband signals at 125 MHz is presented. A new calibration scheme is proposed for the best signal-to-noise-distortion-ratio (SNDR) of the modulator. The continuous-time loop filter is based on Gm-C resonators. A novel transconductance amplifier has been developed with high linearity at high frequency. Qfactor of filter is enhanced by tunable negative impedance which cancels the finite output impendence of OTA. The fourth-order modulator is implemented using 0.35 mm triplemetal standard analog CMOS technology. Postlayout simulation in CADENCE demonstrates that the modulator achieves a SNDR of 50 dB (~8 bit) performance over a 1 MHz bandwidth. The modulator’s power consumption is 302 mW from supply power of ± 1.65V.
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3

Mariano, André Augusto. "Mixed Simulations and Design of a Wideband Continuous-Time Bandpass Delta-Sigma Converter Dedicated to Software Dfined Radio Applications". Thesis, Bordeaux 1, 2008. http://www.theses.fr/2008BOR13644/document.

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La chaîne de réception des téléphones mobiles de dernière génération utilisent au moins deux étages de transposition en fréquence avant d'effectuer la démodulation en quadrature. La transposition en fréquence augmente la complexité du système et engendre de nombreux problèmes tels que la limitation de l'échelle dynamique et l'introduction de bruit issu de l'oscillateur local. Il est alors nécessaire d'envisager une numérisation du signal le plus près possible de l'antenne. Cette dernière permet la conversion directe d'un signal analogique en un signal numérique à des fréquences intermédiaires. Elle simplifie ainsi la conception globale du système et limite les problèmes liés aux mélangeurs. Pour cela, des architectures moins conventionnelles doivent être développées, comme la conversion analogique-numérique utilisant la modulation Sigma-Delta à temps continu. La modélisation comportementale de ce convertisseur analogique-numérique, ainsi que la conception des principaux blocs ont donc été l'objet de cette thèse. L'application d'une méthodologie de conception avancée, permettant la simulation mixte des blocs fonctionnels à différents niveaux d'abstraction, a permis de valider aussi bien la conception des circuits que le système global de conversion. En utilisant une architecture à multiples boucles de retour avec un quantificateur multi-bit, le convertisseur Sigma-Delta passe bande à temps continu atteint un rapport signal sur bruit (SNR) d'environ 76 dB dans une large bande de 20MHz
Wireless front-end receivers of last generation mobile devices operate at least two frequency translations before I/Q demodulation. Frequency translation increases the system complexity, introducing several problems associated with the mixers (dynamic range limitation, noise injection from the local oscillator, etc.). Herein, the position of the analog-to-digital interface in the receiver chain can play an important role. Moving the analog-to-digital converter (ADC) as near as possible to the antenna, permits to simplify the overall system design and to alleviate requirements associated with analog functions (filters, mixers). These currently requirements have led to a great effort in designing improved architectures as Continuous-Time Delta-Sigma ADCs. The behavioural modeling this converter, although the circuit design of the main blocks has been the subject of this thesis. The use of an advanced design methodology, allowing the mixed simulation at different levels of abstraction, allows to validate both the circuit design and the overall system conversion. Using a multi-feedback architecture associated with a multi-bit quantizer, the continuous-time Bandpass Delta-Sigma converter achieves a SNR of about 76 dB in a wide band of 20MHz
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Mahmoud, Doaa. "Convertisseur analogique-numérique de type Sigma-Delta Passe-Bande avec résonateurs à un et deux amplificateurs". Electronic Thesis or Diss., Sorbonne université, 2021. http://www.theses.fr/2021SORUS288.

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Le récepteur radio logicielle (SDR) est une technique prometteuse pour les futurs récepteurs adaptés à une variété de protocoles. Il numérise le signal RF directement en basse fréquence. Nous proposons un récepteur SDR basé sur un modulateur sigma-delta à temps continu passe-bande (CT BP ). Nous nous concentrons sur les résonateurs RC actifs pour diminuer la surface du circuit. Nous ciblons les applications au voisinage de 400 MHz, à savoir Advanced Research and Global Observation Satellite (ARGOS), Medical Implant Communication Service (MICS), Automobile Keyless system et Industrial, Scientific and Medical (ISM). Nous présentons une nouvelle comparaison détaillée entre le modulateur CT BP à résonateur à deux amplificateurs et le modulateur CT BP à résonateur à un amplificateur. Les deux modulateurs sont conçus à l'aide de transistors MOS en technologie FDSOI-28nm, où nous utilisons la polarisation du caisson pour compenser les variations de processus, de tension et de température
Software defined radio receiver is a promising technique for future receivers which provides a variety of protocols. It digitizes the RF signal directly to low-frequency. We propose an SDR receiver based on a bandpass sigma delta modulator. The most essential element is the loop filter, there are two main configurations, an LC tank resonator and an active RC resonator. We focus on the active RC resonators for a low chip area. We target applications in the vicinity of 400 MHz, namely Advanced Research and Global Observation Satellite, Medical Implant Communication Service. We introduce a new comparison between the two-op-amp resonator CT BP sigma delta modulator and the one-op-amp resonator CT BP sigma delta modulator. We study the sensitivity of the quality factor and the signal to noise ratio to the DC-gain op-amps in two-op-amp resonator sigma delta modulator. It also shows how, in one-op-amp resonator sigma delta modulator, the quality factor and the signal to noise ratio, are very sensitive to any variations in the capacitors values for limited DC-gain op-amps. We establish a mathematical model of the thermal-noise behaviour for two-op-amp resonator CT BP sigma delta modulator. This model matches the circuit simulator results with a good accuracy. Furthermore, we demonstrate that a high quality factor (>100) of the two-op-amp resonators can be achieved by selecting the proper value of the integrator gain at a moderate DC-gain op-amp (35dB). Both sigma delta modulators are designed using flipped-well devices on fully depleted silicon on insulator technology, where we use body biasing to compensate the process, voltage and temperature variations
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5

Ding, Chongjun [Verfasser] y Yiannos [Akademischer Betreuer] Manoli. "Design study of high-speed continuous-time delta-sigma modulator". Freiburg : Universität, 2016. http://d-nb.info/1122647026/34.

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Juang, Philip Weimin 1978. "A continuous time sigma-delta modulator for digitizing carrier band measurements". Thesis, Massachusetts Institute of Technology, 2001. http://hdl.handle.net/1721.1/86681.

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Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2001.
Includes bibliographical references (p. 135-136).
by Philip Weimin Juang.
M.Eng.
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7

Chi, Jiazuo. "Micro-Power Inverter-Based Continuous-Time Sigma-Delta Modulator for Biosensor Applications". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-177367.

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Biosensor applications have made promising progress during the last decade, presenting potentials and challenges at the same time. Meanwhile, digital signal processing (DSP) has become even more powerful than before, due to Moore's Law. Bridging the biosensor applications and the digital circuits, analog-to-digital converters (ADCs) are a critical block that inuences the performance of the entire system, in terms of speed, accuracy and power. Particularly, incremental ΣΔ (IΣΔ) ADCs have recently received increasing research interest because of their high-resolution feature and the ability to time-multiplex different channels of input signals, making them especially suitable for neuro-science studies and brain-computer-interface (BCI). However, IΣΔ ADCs are less power-ecient than traditional ΣΔ ADCs. To improve the power eciency and reduce the chip size, an inverter-based continuous-time (CT) Sigma-Delta (ΣΔ) modulator is proposed, to be integrated in a two-step I(ΣΔ) ADC previously designed. Inverter-based operational transconductance amplifers (OTA) have recently demonstrated their high power efficiency in multiple ΣΔ modulators, most of which are discrete-time (DT) implementation. CT implementation is investigated in this thesis for the possibility to further reduce power consumption, due to its more relaxed requirements on bandwidth and settling compared to the DT counterpart. In the circuit implementation of the modulator, fully-differential topology is used in inverter-based CT ΣΔ ADCs for the rst time. Compared to pseudo-differential topology, fully-differential topology has more precise control on the operating point and the quiescent power. The post-layout simulation result shows that the modulator achieves a peak SNDR of 58.1 dB, and a dynamic range of 65.9 dB. The entire modulator consumes 1.28 μW from a 1.2 V supply voltage, on a chip area of only 0.07 mm2. This corresponds to a FoM of 243 fJ/(conv. step).
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Chu, Chao [Verfasser]. "A high speed/high linearity continuous-time delta-sigma modulator / Chao Chu". Ulm : Universität Ulm, 2017. http://d-nb.info/1147848033/34.

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McGinnis, Ryan Edward. "Flexible Sigma Delta Time-Interleaved Bandpass Analog-to-Digital Converter". Wright State University / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=wright1152542196.

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Yoon, Do Yeon. "A continuous-time multi-stage noise-shaping delta-sigma modulator with analog delay". Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/75689.

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Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.
Cataloged from PDF version of thesis.
Includes bibliographical references (p. 73-75).
A new continuous-time multi-stage noise-shaping delta-sigma modulator has been designed. This modulator provides high resolution and robust stability characteristics which are the primary advantages of the conventional multi-stage noise-shaping architecture. At the same time, previous critical challenges that degraded the overall performance of multi-stage noise-shaping delta-sigma modulators are eliminated through several unique techniques. Additionally, these techniques relax the requirements of each component of the proposed delta-sigma modulator. As a result, this new delta-sigma modulator architecture can provide several advantages that are not obtainable in other modulator architectures.
by Do Yeon Yoon.
S.M.
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Capítulos de libros sobre el tema "Sigma-delta continuous-time bandpass modulator"

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van Engelen, Jurgen y Rudy van de Plassche. "Design of Continuous Time Bandpass SDMS". En Bandpass Sigma Delta Modulators, 107–19. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-4586-3_6.

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Bolatkale, Muhammed, Lucien J. Breems y Kofi A. A. Makinwa. "Continuous-Time Delta-Sigma Modulator". En Analog Circuits and Signal Processing, 9–35. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-05840-5_2.

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Huang, Jhin-Fang, Jiun-Yu Wen y Wei-Chih Chen. "Chip Design of a Continuous-Time 5-MHz Low-Pass Sigma-Delta Modulator". En Proceedings of the 4th International Conference on Computer Engineering and Networks, 925–33. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-11104-9_106.

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Kunamalla, Sarangam y Bheema Rao Nistala. "A Low-Power Third-Order Passive Continuous-Time Sigma-Delta Modulator Using FinFET". En Lecture Notes in Electrical Engineering, 395–405. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-7031-5_38.

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Firouzkouhi, Hossein, José De la Rosa y Paolo Crovetti. "Design of a 1st-Order Continuous-Time $$\Sigma \Delta$$ Modulator with a Digital-Based Floating-Inverter Integrator". En Lecture Notes in Electrical Engineering, 54–59. Cham: Springer Nature Switzerland, 2023. http://dx.doi.org/10.1007/978-3-031-48711-8_7.

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Pereira, Nuno, João L. A. de Melo y Nuno Paulino. "Design of a 3rd Order 1.5-Bit Continuous-Time Fully Differential Sigma-Delta (ΣΔ) Modulator Optimized for a Class D Audio Amplifier Using Differential Pairs". En IFIP Advances in Information and Communication Technology, 639–46. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-37291-9_69.

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Actas de conferencias sobre el tema "Sigma-delta continuous-time bandpass modulator"

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Lieu, Don T. y Thomas P. Weldon. "A 10MHz continuous time bandpass delta sigma modulator". En SOUTHEASTCON 2012. IEEE, 2012. http://dx.doi.org/10.1109/secon.2012.6196890.

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Mariano, A., D. Dallet, Y. Deval y J.-B. Begueret. "High-speed multi-bit continuous-time bandpass delta-sigma modulator". En 2007 Ph.D Research in Microelectronics and Electronics Conference. IEEE, 2007. http://dx.doi.org/10.1109/rme.2007.4401814.

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Honarparvar, Mohammad, Rene Landry, Frederic Nabki y Mohamad Sawan. "Advanced modeling technique for bandpass continuous-time delta-sigma modulators". En 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS). IEEE, 2014. http://dx.doi.org/10.1109/newcas.2014.6934052.

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Sakr, Khaled, Mohamed Dessouky y Abd-El Halim Zekry. "Design of tunable continuous-time quadrature bandpass delta-sigma modulators". En 2011 IEEE 6th International Design and Test Workshop (IDT). IEEE, 2011. http://dx.doi.org/10.1109/idt.2011.6123110.

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Flynn, Michael P., Jaehun Jeong, Sunmin Jang, Hyungil Chae, Daniel Weyer, Rundao Lu y John Bell. "Continuous-Time Bandpass Delta-Sigma Modulators and Bitstream Processing: (Invited)". En 2020 IEEE Custom Integrated Circuits Conference (CICC). IEEE, 2020. http://dx.doi.org/10.1109/cicc48029.2020.9075928.

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Schmidt, Martin, Stefan Heck, Ingo Dettmann, Markus Grozing, Manfred Berroth, Dirk Wiegner y Wolfgang Templ. "Continuous-Time Bandpass Delta-Sigma Modulator for a Signal Frequency of 2.2 GHz". En 2009 German Microwave Conference (GeMIC 2009). IEEE, 2009. http://dx.doi.org/10.1109/gemic.2009.4815872.

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Kim, Song-Bok, Stefan Joeres, Niklas Zimmermann, Markus Robens, Ralf Wunderlich y Stefan Heinen. "Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GPS/Galileo Low-If Receiver". En 2007 IEEE International Workshop on Radio-Frequency Integration Technology. IEEE, 2007. http://dx.doi.org/10.1109/rfit.2007.4443935.

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Yuan, Xiaolong, Xiaobo Wu y Svante Signell. "Continuous-Time Quadrature Bandpass Sigma Delta Modulators with Different Feedback DAC". En 2008 4th IEEE International Conference on Circuits and Systems for Communications (ICCSC 2008). IEEE, 2008. http://dx.doi.org/10.1109/iccsc.2008.129.

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Saalfeld, Tobias, Markus Scholl, Christoph Beyerstedt, Ralf Wunderlich y Stefan Heinen. "A Tracking Quantizer for Continuous Time Quadrature Bandpass Sigma-Delta Modulators". En 2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, 2018. http://dx.doi.org/10.1109/icecs.2018.8618055.

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Hussein, A. I., N. M. Ibrahim y W. B. Kuhn. "Undersampled continuous-time bandpass MASH /spl Sigma//spl Delta/ modulator for wireless communication applications". En Proceedings of the Twentieth National Radio Science Conference (NRSC'2003). IEEE, 2003. http://dx.doi.org/10.1109/nrsc.2003.157342.

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