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Artículos de revistas sobre el tema "SERIAL ASYNCHRONOUS"

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Autor: Grafiati
Publicado: 26 de octubre de 2023

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1

Dobkin, Rostislav, Michael Moyal, Avinoam Kolodny y Ran Ginosar. "Asynchronous Current Mode Serial Communication". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18, n.º 7 (julio de 2010): 1107–17. http://dx.doi.org/10.1109/tvlsi.2009.2020859.

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2

P, Srikanth y Latha Kodam. "Design of Serial-Serial Multiplier based on the Asynchronous Counter Accumulation". International Journal of Computer Applications Technology and Research 3, n.º 4 (1 de abril de 2014): 263–66. http://dx.doi.org/10.7753/ijcatr0304.1013.

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3

Tošić, M. B., M. K. Stojčev, D. M. Maksimović y G. Lj Djordjević. "The asynchronous counterflow pipeline bit-serial multiplier". Journal of Systems Architecture 44, n.º 12 (septiembre de 1998): 985–1004. http://dx.doi.org/10.1016/s1383-7621(97)00046-5.

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4

Hariyanto, D., A. C. Nugraha, A. Asmara y H. Liu. "An Asynchronous Serial Communication Learning Media: Usability Evaluation". Journal of Physics: Conference Series 1413 (noviembre de 2019): 012018. http://dx.doi.org/10.1088/1742-6596/1413/1/012018.

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5

Pambudi, Bimo Langgeng Rilo y Wahyu Sapto Aji. "Serial Communication Module with Visual Basic and Arduino for Practical Use". Buletin Ilmiah Sarjana Teknik Elektro 3, n.º 2 (30 de septiembre de 2021): 130–36. http://dx.doi.org/10.12928/biste.v3i2.1494.

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Interface techniques on computers and instruments cannot be separated from the software contained in computers to communicate. Communication that is commonly used is serial and parallel data. The method used in this development uses the Asynchronous serial data communication method which occurs if the clock on each communication device is not synchronized in reading data and displaying data. serial communication using Visual Basic Software as a medium to read and display serial data from Arduino. The level of accuracy when reading data and displaying data error rate/error 0% with 8 times of testing Data reading and displaying data. Teknik interface pada komputer dan instrumen tidak dapat dipisahkan dari perangkat lunak yang terdapat pada komputer untuk berkomunikasi. Komunikasi yang umum digunakan adalah data serial dan paralel. Metode yang digunakan pada pengembangan ini menggunakan metode Komunikasi data serial Asynchronous yang terjadi jika clock yang terdapat pada masing-masing perangkat komunikasi tidak tersinkronisasi pada pembacaan data dan menampilkan data. komunikasi serial menggunakan Software Visual Basic sebagai media untuk membaca dan menampilkan data serial dari Arduino. Tingkat akurasi pada saat Pembacaan data dan menampilkan data tingkat kesalahan/error 0% dengan 8 kali pengujian Pembacaan data dan menampilkan data.
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6

Zeki, Semir. "A massively asynchronous, parallel brain". Philosophical Transactions of the Royal Society B: Biological Sciences 370, n.º 1668 (19 de mayo de 2015): 20140174. http://dx.doi.org/10.1098/rstb.2014.0174.

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Whether the visual brain uses a parallel or a serial, hierarchical, strategy to process visual signals, the end result appears to be that different attributes of the visual scene are perceived asynchronously—with colour leading form (orientation) by 40 ms and direction of motion by about 80 ms. Whatever the neural root of this asynchrony, it creates a problem that has not been properly addressed, namely how visual attributes that are perceived asynchronously over brief time windows after stimulus onset are bound together in the longer term to give us a unified experience of the visual world, in which all attributes are apparently seen in perfect registration. In this review, I suggest that there is no central neural clock in the (visual) brain that synchronizes the activity of different processing systems. More likely, activity in each of the parallel processing-perceptual systems of the visual brain is reset independently, making of the brain a massively asynchronous organ, just like the new generation of more efficient computers promise to be. Given the asynchronous operations of the brain, it is likely that the results of activities in the different processing-perceptual systems are not bound by physiological interactions between cells in the specialized visual areas, but post-perceptually, outside the visual brain.
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7

Zhan, Hua Lin y Xiao Chun Lai. "Multiple Serial Communication Design Based on ADSP-BF561". Advanced Materials Research 846-847 (noviembre de 2013): 667–70. http://dx.doi.org/10.4028/www.scientific.net/amr.846-847.667.

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This paper introduces asynchronous serial design and communication implementation by TI Co.,Ltd TL16C554 based on dual core processorADSP-BF561 and uClinux. This paper has accomplished multiple serial accessing using share interrupt scheme which has already been used in a wireless sense network.
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8

Kim, Hyoung Won, Hyo Dal Park y Taek Lyul Song. "Multisensor Bias Estimation with Serial Fusion for Asynchronous Sensors". Journal of the Korea Institute of Military Science and Technology 15, n.º 5 (5 de octubre de 2012): 676–86. http://dx.doi.org/10.9766/kimst.2012.15.5.676.

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9

KumarMeena, Manoj y Neelam Rup Prakash. "ARM7TDMI based Low Cost Portable Serial Asynchronous Protocol Analyzer". International Journal of Computer Applications 40, n.º 7 (29 de febrero de 2012): 27–32. http://dx.doi.org/10.5120/4977-7234.

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10

Gopal, P. Bala y K. Hari Kishore. "An FPGA Implementation of On Chip UART Testing with BIST Techniques". International Journal of Reconfigurable and Embedded Systems (IJRES) 5, n.º 3 (1 de noviembre de 2016): 176. http://dx.doi.org/10.11591/ijres.v5.i3.pp176-182.

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A Universal Asynchronous Receiver Transmitter (UART) is usually implemented for asynchronous serial communication, mostly used for short distance communications. It allows full duplex serial communication link and is used in data communication and control system. Nowadays there is a requirement for on chip testing to overcome the product failures. This paper targets the introduction of Built-in self test (BIST) for UART to overcome the above two constraints of testability and data integrity. The 8-bit UART with BIST module is coded in Verilog HDL and synthesized and simulated using Xilinx XST and implemented on SPARTAN 3E FPGA. Results indicate that this model eliminates the need for expensive testers and thereby it can reduce the development time and cost.
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11

Pan, Deng, Yu Hua y Yu Xiang. "Research of Transport Stream and PCR Timestamp in the Satellite Digital TV Time Service System". Applied Mechanics and Materials 411-414 (septiembre de 2013): 799–802. http://dx.doi.org/10.4028/www.scientific.net/amm.411-414.799.

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The Satellite Digital TV Time Service is based on the DVB-S Satellite Digital TV system, using Program Clock Reference (PCR) in the MPEG-2 frame to capture timestamp and measure delay time. This paper, considering the PCR as the Time Synchronization Flag after researching Transport Stream (TS) frame and Asynchronous Serial Interface (ASI) in Satellite Digital TV system, recovers the asynchronous serial data from TS in Satellite Digital TV by oversampling technology. After that, PCR will be found from the recovered data, and the timestamp will be captured when PCR is detected. Finally, this method is tested by using E5710 Encoder and FPGA Cyclone II chip. The experimental results are satisfactory, and the precision of detecting bit synchronization excels 3.7ns.
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12

Meher, Manas Ranjan, Ching Chuen Jong y Chip-Hong Chang. "A High Bit Rate Serial-Serial Multiplier With On-the-Fly Accumulation by Asynchronous Counters". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19, n.º 10 (octubre de 2011): 1733–45. http://dx.doi.org/10.1109/tvlsi.2010.2060374.

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13

Feng, Xiao Hui y Chang Li Wang. "Research on Serial Communication in the Permanent Magnet Linear Synchronous Motor Vertical Transportation System". Advanced Materials Research 905 (abril de 2014): 476–80. http://dx.doi.org/10.4028/www.scientific.net/amr.905.476.

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The serial communication design based on DSP in the permanent magnet linear synchronous motor vertical transportation system is presented in this paper. The control system structure and fundamental are introduced briefly at first. Then, the realization of serial communication between the TMS320VC5402 and PC by asynchronous serial communications chip TL16C550C is introduced in detail. Finally, the design of system hardware interface circuit and software programs are presented. The features of this system include simple programming , good reliability and real-time capability.
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14

Zhao, Xue Mei. "Realization of Serial Port Expansion Circuit". Applied Mechanics and Materials 271-272 (diciembre de 2012): 1597–601. http://dx.doi.org/10.4028/www.scientific.net/amm.271-272.1597.

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This article describes the design of a interface chip with serial port expansion circuit of computer in industrial applications. It is used to connect with 422 and RS232 interfaces. Circuits involved several major chip such as the interface of 422 and RS232 and UART(Universal Asynchronous Receiver Transmitter)16C550 Inside the computer. Paper describes the composition of the hardware circuit, theory and implementation and initialization programming of URAT interface chip. We use interface chip with the FIFO to the circuit, It improves the efficiency of the application software, And it solves the problem of insufficient of computer serial port.
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15

Tong, Xiao Rong y Zhong Biao Sheng. "Design of UART with CRC Check Based on FPGA". Advanced Materials Research 490-495 (marzo de 2012): 1241–45. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.1241.

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In order to realize the accurate serial communication, a simple and practical scheme for URAT design and implementation was put forward based on the analysis of CRC generation algorithm. The reliability of serial communication can be improved by adding CRC into the asynchronous serial communication. The CRC checksum module is achieved with Verilog language on the basis of FPGA and obtained consistence between the results of simulation and theoretical analysis. Therefore, the expected design target was met, and the communication speed and efficiency was improved.
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16

Yintang, Yang, Guan Xuguang, Zhou Duan y Zhu Zhangming. "A full asynchronous serial transmission converter for network-on-chips". Journal of Semiconductors 31, n.º 4 (abril de 2010): 045007. http://dx.doi.org/10.1088/1674-4926/31/4/045007.

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17

Jones, Dylan M. "Disruption of Memory for Lip-Read Lists by Irrelevant Speech: Further Support for the Changing State Hypothesis". Quarterly Journal of Experimental Psychology Section A 47, n.º 1 (febrero de 1994): 143–60. http://dx.doi.org/10.1080/14640749408401147.

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Two experiments critically re-examine the finding of Campbell and Dodd (1984, Experiment 2), which suggests that irrelevant speech disrupts the encoding of visual material for serial recall. Support is sought for the competing view that the effect of irrelevant speech is on storage by comparing the effect of a range of acoustic conditions on memory for graphic and lip-read lists. Initially, serial short-term recall of visually presented lists was examined with irrelevant speech that was both asynchronous with the visually presented items and of varied speech content (Experiment 1a). In this experiment substantial impairments in recall of both graphic and lip-read lists were found. However, with unvarying asynchronous speech (Experiment 1b) the effect of speech was small and non-significant. Experiment 2 examined the effect of changing state and of synchrony of speech with lip movements. When conditions of synchronous and asynchronous unvarying speech were contrasted, no significant effect of synchrony or irrelevant speech was found (Experiment 2a and 2c). In contrast, when the speech was varying in content, a strong effect of irrelevant speech was found; moreover, the effect was roughly the same for synchronous and asynchronous materials (Experiment 2b). The contrast in outcome with varying and unvarying speech provides strong support for the “changing state” model of the irrelevant speech effect. Coupled with the absence of an effect of synchrony in Experiment 2, these experiments reinforce the view that disruption by irrelevant speech occurs in memory, not at encoding.
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18

Park, Geun-Duk, Sam-Kweon Oh y Byoung-Kuk Kim. "An Interrupt Coalescence Method for Improving Performance of Asynchronous Serial Communication". Journal of the Korea Academia-Industrial cooperation Society 12, n.º 3 (31 de marzo de 2011): 1380–86. http://dx.doi.org/10.5762/kais.2011.12.3.1380.

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19

Kidiyarova-Shevchenko, A. Yu, K. Yu Platov, E. M. Tolkacheva y I. A. Kataeva. "RSQO asynchronous serial multiplier and spreading codes generator for multiuser detector". IEEE Transactions on Appiled Superconductivity 13, n.º 2 (junio de 2003): 429–32. http://dx.doi.org/10.1109/tasc.2003.813889.

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20

Kim, Chang Ouk, Ick-Hyun Kwon y Jun-Geol Baek. "Asynchronous action-reward learning for nonstationary serial supply chain inventory control". Applied Intelligence 28, n.º 1 (17 de febrero de 2007): 1–16. http://dx.doi.org/10.1007/s10489-007-0038-2.

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21

Kim, Chang Ouk, Ick-Hyun Kwon y Jun-Geol Baek. "Asynchronous action-reward learning for nonstationary serial supply chain inventory control". Applied Intelligence 30, n.º 2 (29 de julio de 2007): 187. http://dx.doi.org/10.1007/s10489-007-0087-6.

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22

Zhang, Hang. "A Systematic Analysis of The UART Transceiver Theory and Application". Highlights in Science, Engineering and Technology 61 (30 de julio de 2023): 172–79. http://dx.doi.org/10.54097/hset.v61i.10290.

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This article introduces the theoretical foundation and application of Universal Asynchronous Receiver/Transmitter (UART) in four chapters, including the history and structure of UART transceivers, and so on. UART is a kind of communication hardware using serial Asynchronous communication, which has the advantages of simple structure and good stability. It can convert serial data and parallel data to each other and transmit data between devices. It is widely used on various devices. In the 50 years since its invention, it has undergone many improvements and improvements. In the end, UART transceivers became one of the extremely important hardware in modern electronic technology. At present, UART transceivers are applied in many fields, including healthcare, the Internet of Things, and avionics. Its application in the fields of healthcare and the Internet of Things is of great significance, providing more possibilities for a more convenient life for humanity. Meanwhile, researchers are also attempting to continue improving the transmission speed of UART transceivers and reducing their power consumption.
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23

Zhang, Jie Fei, Peng Fei Zhan y Gang Zhang. "Ethernet Controller and Serial Interface Conversion Technology Based on FPGA". Applied Mechanics and Materials 423-426 (septiembre de 2013): 2671–74. http://dx.doi.org/10.4028/www.scientific.net/amm.423-426.2671.

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The FPGA-based 10/100M Ethernet MAC controller and universal asynchronous serial communication controller are designed and connected on chip in this paper. Such functions as writing data transmitted by the serial interface to the Ethernet controller and sending them to the network, and serially outputting network data received by the Ethernet controller are implemented and interconnection communications between Ethernet and the serial are achieved, possessing great practical values in system test. Modularization design is performed on the whole system with VHDL in this study, whose hardware application is verified on Xilinx Virtex2P XC2VP30 development board. The simulation results prove that the design has reliability, stability and good applications in the data transmission test.
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24

de Vreede, Gert-Jan, Robert O. Briggs y Roni Reiter-Palmon. "Exploring Asynchronous Brainstorming in Large Groups: A Field Comparison of Serial and Parallel Subgroups". Human Factors: The Journal of the Human Factors and Ergonomics Society 52, n.º 2 (abril de 2010): 189–202. http://dx.doi.org/10.1177/0018720809354748.

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Objective: The aim of this study was to compare the results of two different modes of using multiple groups (instead of one large group) to identify problems and develop solutions. Background: Many of the complex problems facing organizations today require the use of very large groups or collaborations of groups from multiple organizations. There are many logistical problems associated with the use of such large groups, including the ability to bring everyone together at the same time and location. Methods: A field study involved two different organizations and compared productivity and satisfaction of group. The approaches included (a) multiple small groups, each completing the entire process from start to end and combining the results at the end (parallel mode); and (b) multiple subgroups, each building on the work provided by previous subgroups (serial mode). Results: Groups using the serial mode produced more elaborations compared with parallel groups, whereas parallel groups produced more unique ideas compared with serial groups. No significant differences were found related to satisfaction with process and outcomes between the two modes. Conclusion: Preferred mode depends on the type of task facing the group. Parallel groups are more suited for tasks for which a variety of new ideas are needed, whereas serial groups are best suited when elaboration and in-depth thinking on the solution are required. Application: Results of this research can guide the development of facilitated sessions of large groups or “teams of teams.”
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25

Chen, Zai Ping y Zhi Tong Chen. "Absolute Value Encoder Communication Interface Design Based on SSI Protocol". Applied Mechanics and Materials 441 (diciembre de 2013): 932–35. http://dx.doi.org/10.4028/www.scientific.net/amm.441.932.

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In terms of absolute value encoder applications, SSI communication protocol, as an earlier implementation of communication protocol, has been widely used recently. Many companies, including both domestic and overseas, have introduced encoder communication interfaces with the SSI absolute value. In this paper, based on the features of SSI protocol communication, we propose a low cost of SSI protocol communication interface design scheme for the absolute value encoder whose output is asynchronous or parallel. The experiment shows that this kind of communication interface is stable, reliable and makes the absolute value encoder with asynchronous serial or parallel output interface meet the SSI protocol specification of communication function.
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26

Chen, Wenchong, Hongwei Liu y Ershi Qi. "Buffer allocation in asynchronous serial production systems with Bernoulli machines during transients". International Journal of Industrial and Systems Engineering 39, n.º 2 (2021): 176. http://dx.doi.org/10.1504/ijise.2021.118263.

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27

Calabretta, Nicola, Marco Presi, Giampiero Contestabile y Ernesto Ciaramella. "All-Optical Asynchronous Serial-to-Parallel Converter Circuit for DPSK Optical Packets". IEEE Photonics Technology Letters 19, n.º 10 (mayo de 2007): 783–85. http://dx.doi.org/10.1109/lpt.2007.895895.

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28

Mourão, Flávio Afonso Gonçalves, André Luiz Vieira Lockmann, Gabriel Perfeito Castro, Daniel de Castro Medeiros, Marina Pádua Reis, Grace Schenatto Pereira, André Ricardo Massensini y Marcio Flávio Dutra Moraes. "Triggering Different Brain States Using Asynchronous Serial Communication to the Rat Amygdala". Cerebral Cortex 26, n.º 5 (21 de enero de 2015): 1866–77. http://dx.doi.org/10.1093/cercor/bhu313.

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29

Liu, Hongwei, Wenchong Chen y Ershi Qi. "Buffer allocation in asynchronous serial production systems with Bernoulli machines during transients". International Journal of Industrial and Systems Engineering 1, n.º 1 (2020): 1. http://dx.doi.org/10.1504/ijise.2020.10030579.

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30

En, De, Huang He Wei, Na Na Wei, Xiao Long Shi y Chang Sheng Zhou. "Design of Collecting and Processing System of GPS Information Based on ARM and Linux". Applied Mechanics and Materials 273 (enero de 2013): 714–17. http://dx.doi.org/10.4028/www.scientific.net/amm.273.714.

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GPS information collecting and processing is an important part of the navigation and positioning system. Through the establishment of cross-compiler environment, using the ARM processor S3C2440A and Linux operating systems as the hardware and software platform and the GS87 is used as GPS receiver module, the NMEA-0183 communications protocol and serial asynchronous communication between the ARM platform and GS87 module are analyzed. Through the serial port programming, GPS information collecting and processing system is realized. By querying the GPRMC statement and the corresponding conversion, the useful information is separated. The final practice has proved that the system data is of high precision, real-time property and good practical value.
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31

Legalov, Alexander I., Ivan V. Matkovskii, Mariya S. Ushakova y Darya S. Romanova. "Dynamically Changing Parallelism with the Asynchronous Sequential Data Flows". Modeling and Analysis of Information Systems 27, n.º 2 (24 de junio de 2020): 164–79. http://dx.doi.org/10.18255/1818-1015-2020-2-164-179.

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A statically typed version of the data driven functional parallel computing model is proposed. It enables a representation of dynamically changing parallelism by means of asynchronous serial data flows. We consider the features of the syntax and semantics of the statically typed data driven functional parallel programming language Smile that supports asynchronous sequential flows. Our main idea is to apply the Hoar concept of communicating sequential processes to the computation control on the data readiness. It is assumed that on the data readiness a control signal is emitted to inform the processes about the occurrence of certain events. The special feature of our approach is that the model is extended with the special asynchronous containers that can generate events on their partial filling. These containers are a stream and a swarm, each of which has its own specifics. A stream is used to process data which have identical type. The data comes sequentially and asynchronously at arbitrary time moments. The number of the incoming data elements is initially unknown, so the processing completes on the signal of the end of the stream. A swarm is used to contain independent data of the same type and may be used for the massive parallel operations performing. Unlike a stream, the swarm’s size is fixed and known in advance. General principles of the operations with the asynchronous sequential flows with an arbitrary order of data arrival are described. The use of the streams and the swarms in various situations is considered. We propose the language constructions which allow us to operate the swarms and streams and describe the specifics of their application. We provide the sample functions to illustrate the use of the different approaches to description of the parallelism: recursive processing of the asynchronous flows, processing of the flows in an arbitrary or predefined order of operations, direct access and access by the reference to the elements of the streams and swarms, pipelining of calculations. We give a preliminary parallelism assessment which depends on the ratio of the rates of data arrival and their processing. The proposed methods can be used in the development of the future languages and tool-kits of architecture-independent parallel programming.
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32

Zhang, Zhonghua, Song Chen, Shuyun Wang, Junwu Kan, Jianming Wen y Can Yang. "Performance evaluation and comparison of a serial–parallel hybrid multichamber piezoelectric pump". Journal of Intelligent Material Systems and Structures 29, n.º 9 (4 de marzo de 2018): 1995–2007. http://dx.doi.org/10.1177/1045389x18758181.

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To improve the output capability of piezoelectric pumps, researchers have made an attempt to combine multiple single-chamber pumps either in series or in parallel. In this article, a serial–parallel hybrid multichamber piezoelectric pump is presented. The novel serial–parallel hybrid multichamber piezoelectric pump structure is characterized by the simultaneous occurrence of serial/parallel forms through a combination of synchronous and asynchronous modes of piezoelectric actuators. Moreover, the pump can be operated in multiple working modes to obtain the desired chamber volume and number through different serial–parallel configurations. The performance characteristics of the pump with various serial–parallel hybrid combinations were experimentally investigated and evaluated using a quintuple-chamber pump at 90 V with a frequency range of 60–400 Hz. Experimental results showed that the characteristics in terms of flow rate and backpressure changed significantly with different serial–parallel modes. Nevertheless, the backpressure presented very similar characteristics for the serial–parallel hybrid multichamber piezoelectric pump with the same number of in-phase parallel actuators. Meanwhile, the frequency-dependent flow rate characteristics were approximately similar for those pumps with symmetric serial–parallel combinations. It was found that the flow rate and backpressure mainly depended on the actuation frequency and serial–parallel modes, respectively. Compared with the quintuple-chamber pump with full out-of-phase actuators, the maximum powers of the serial–parallel hybrid multichamber piezoelectric pump with two, three, four, and five in-phase actuators were decreased by 21.1%, 51.4%, 77.7%, and 94.4%, respectively.
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33

Yang, Hong Cai y Ming Qing Wu. "NC Processing Network Platform RS-232-C Interface Circuit Design". Advanced Materials Research 529 (junio de 2012): 29–32. http://dx.doi.org/10.4028/www.scientific.net/amr.529.29.

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RS-232-C and a modem together, the interface can connect all kinds of different types of micro computer, so that they can direct communication. Nowadays more popular FANUC series CNC system, and the machine is equipped with a 25 injection of RS-232-C asynchronous serial communication interface standards, connect the computer and programmer and peripherals. With MAX232 chip design of interface circuit DB9.
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34

Chen, Ding. "Design and Innovation of Asynchronous Serial Communication Interface Conversion System of Field Bus". Journal of Physics: Conference Series 1792, n.º 1 (1 de febrero de 2021): 012069. http://dx.doi.org/10.1088/1742-6596/1792/1/012069.

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35

ONIZAWA, Naoya, Takahiro HANYU y Vincent C. GAUDET. "High-Throughput Bit-Serial LDPC Decoder LSI Based on Multiple-Valued Asynchronous Interleaving". IEICE Transactions on Electronics E92-C, n.º 6 (2009): 867–74. http://dx.doi.org/10.1587/transele.e92.c.867.

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36

Ito, M., K. Kawasaki, N. Yoshikawa, A. Fujimaki, H. Terai y S. Yorozu. "20 GHz Operation of Bit-Serial Handshaking Systems Using Asynchronous SFQ Logic Circuits". IEEE Transactions on Appiled Superconductivity 15, n.º 2 (junio de 2005): 255–58. http://dx.doi.org/10.1109/tasc.2005.849773.

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37

Mizuno, Masaaki y Mikhail Nesterenko. "A transformation of self-stabilizing serial model programs for asynchronous parallel computing environments". Information Processing Letters 66, n.º 6 (junio de 1998): 285–90. http://dx.doi.org/10.1016/s0020-0190(98)00069-6.

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38

HARIYAMA, M., S. ISHIHARA y M. KAMEYAMA. "Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture". IEICE Transactions on Electronics E91-C, n.º 9 (1 de septiembre de 2008): 1419–26. http://dx.doi.org/10.1093/ietele/e91-c.9.1419.

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39

Ridley, Dennis y Pierre Ngnepieba. "Antithetic Power Transformation in Monte Carlo Simulation: Correcting Hidden Errors in the Response Variable". Mathematics 11, n.º 9 (28 de abril de 2023): 2097. http://dx.doi.org/10.3390/math11092097.

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Monte Carlo simulation is performed with uniformly distributed U(0,1) pseudo-random numbers. Because the numbers are generated from a mathematical formula, they will contain some serial correlation, even if very small. This serial correlation becomes embedded in the correlation structure of the response variable. The response variable becomes an asynchronous time series. This leads to hidden errors in the response variable. The purpose of this paper is to illustrate how this happens and how it can be corrected. The method is demonstrated for the case of a simple queue for which the time in the system is known exactly from theory. The paper derives the correlation between an exponential random variable and its antithetic counterpart obtained by power transform with an infinitesimal negative exponent.
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40

ARENDT, DUSTIN y YANG CAO. "EFFECTIVE GPU ACCELERATION OF LARGE SCALE, ASYNCHRONOUS SIMULATIONS ON GRAPHS". Advances in Complex Systems 15, n.º 08 (8 de noviembre de 2012): 1250035. http://dx.doi.org/10.1142/s021952591250035x.

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The recent emergence of GPGPU programming has resulted in a number of very efficient, but ultimately ad-hoc implementations of GPU accelerated simulations of complex systems. Because developing applications for the GPU is still a difficult and time consuming task, efficient GPU parallelizations of general purpose modeling frameworks are very useful. The dimer automaton is a stochastic modeling and simulation framework with a good balance of robustness, generality, and simplicity with capacity to model a wide range of phenomena. A major advantage of dimer automata is the ease in which they can be applied to any space that can be represented as a graph. Therefore, we have developed an efficient GPU implementation of dimer automata that runs up to 80 times faster than the serial implementation.
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41

Huang, Jian, Wu Wang, Yuzhu Wang, Jinrong Jiang, Chen Yan, Lian Zhao y Yidi Bai. "Performance Evaluation and Optimization of the Weather Research and Forecasting (WRF) Model Based on Kunpeng 920". Applied Sciences 13, n.º 17 (30 de agosto de 2023): 9800. http://dx.doi.org/10.3390/app13179800.

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The Weather Research and Forecasting (WRF) model is a mesoscale numerical weather prediction system, which is widely used in major high-performance server platforms. This study focuses on the performance evaluation and optimization of WRF on Huawei’s self-developed kunpeng 920 processor platform, aiming to improve the operational efficiency of WRF. The results of the study show that the scalability of WRF on kunpeng 920 processor is well performed; the performance of WRF on kunpeng 920 processor is improved by 32.6% after invoking the Fast Math Library and Domain Decomposition Core Tile Division optimization. In terms of IO, the main optimizations are parallel IO and asynchronous IO. Eventually, the single output time of WRF is reduced from 37.28 s in serial IO mode to 0.14 s in asynchronous IO mode, and the overall running time is reduced from 1078.80 s to 807.94 s.
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42

Guyeux, Christophe. "Convergence versus Divergence Behaviors of Asynchronous Iterations, and Their Applications in Concrete Situations". Mathematical and Computational Applications 25, n.º 4 (16 de octubre de 2020): 69. http://dx.doi.org/10.3390/mca25040069.

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Asynchronous iterations have long been used in distributed computing algorithms to produce calculation methods that are potentially faster than a serial or parallel approach, but whose convergence is more difficult to demonstrate. Conversely, over the past decade, the study of the complex dynamics of asynchronous iterations has been initiated and deepened, as well as their use in computer security and bioinformatics. The first work of these studies focused on chaotic discrete dynamical systems, and links were established between these dynamics on the one hand, and between random or complex behaviours in the sense of the theory of the same name. Computer security applications have focused on pseudo-random number generation, hash functions, hidden information, and various security aspects of wireless sensor networks. At the bioinformatics level, this study of complex systems has allowed an original approach to understanding the evolution of genomes and protein folding. These various contributions are detailed in this review article, which is an extension of the paper “An update on the topological properties of asynchronous iterations” presented during the Sixth International Conference on Parallel, Distributed, GPU and Cloud Computing (Pareng 2019).
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43

Takahashi, Ryo, Ryohei Urata, Tetsuya Suemitsu y Hiroyuki Suzuki. "A 40-Gb/s Self-Clocked Bidirectional Serial/Parallel Converter for Asynchronous Label Swapping". IEEE Photonics Technology Letters 19, n.º 5 (2007): 294–96. http://dx.doi.org/10.1109/lpt.2007.891239.

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44

Hino, S., M. Togashi y K. Yamasaki. "Asynchronous transfer mode switching LSI chips with 10-Gb/s serial I/O ports". IEEE Journal of Solid-State Circuits 30, n.º 4 (abril de 1995): 348–52. http://dx.doi.org/10.1109/4.375952.

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45

Zhang, Y., R. Dobkin, A. Unikovski, D. Nahmanny, G. Samuel, M. Moyal y R. Ginosar. "A 1.4×FO4 self-clocked asynchronous serial link in 0.18 µm for intrachip communication". Integration 59 (septiembre de 2017): 190–97. http://dx.doi.org/10.1016/j.vlsi.2017.06.007.

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46

Sama, Michael P., Timothy S. Stombaugh y James E. Lumpp. "A hardware method for time-stamping asynchronous serial data streams relative to GNSS time". Computers and Electronics in Agriculture 97 (septiembre de 2013): 56–60. http://dx.doi.org/10.1016/j.compag.2013.07.003.

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47

Oon, Tik-Bin y R. Steele. "Successive serial parallel cancellation and joint detection CDMA systems in flat fading asynchronous channels". Electronics Letters 34, n.º 1 (1998): 42. http://dx.doi.org/10.1049/el:19980031.

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48

Lee, Sang Sik, Ki Young Shin y Joung H. Mun. "Development of a Portable and Wireless Surface EMG". Key Engineering Materials 321-323 (octubre de 2006): 1107–10. http://dx.doi.org/10.4028/www.scientific.net/kem.321-323.1107.

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The objective of this study was to develop a portable, wireless surface EMG of a noninvasive type. The limitations of the existing system include its large size and the necessity of a wire. Therefore, this study focused on the development of a portable and wireless type of EMG. The developed EMG, which has 10 channels, is composed of an electrode for the measurement of the EMG signal, a preamplifier for initial processing, a second amplifier, an A/D converter, and a Bluetooth module for wireless communication. The communication of the developed EMG used a UART (Universal Asynchronous serial Receiver and Transmitter) and Bluetooth protocols. The rate of serial communication was set to 723kbps. This system is able to obtain 2,000 Hz in each channel. The data transfer success rate of the developed EMG is 100%.
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49

SRIVASTAVA, JAIDEEP, JAU-HWANG WANG, KUO WEI HWANG y WEI TEK TSAI. "A TRANSACTION MODEL FOR PARALLEL RULE EXECUTION PART I: MODEL AND ALGORITHMS". International Journal on Artificial Intelligence Tools 02, n.º 03 (septiembre de 1993): 395–429. http://dx.doi.org/10.1142/s0218213093000205.

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This paper introduces a transaction model for parallel production systems, where rules can be fired in a completely asynchronous parallel manner. A model is developed to describe two properties of a serial production system execution, namely, conditional dependence (a rule firing removes another from the conflict set) and prioritization (by the conflict resolution mechanism). These are used as the basis to define the correctness criteria for parallel production execution, namely, conditional serializability, prioritized serializability, and prioritized conditional serializability. A graph model is used to represent production system execution which provides a means of expressing correctness as graph acyclicity, which in turn is used as a basis to develop practical schedulers that manage the concurrent asynchronous production execution and ensure correctness. Two practical schedulers, namely, conditional strict two-phase locking and priority queue scheduler are developed for conditional serializability and prioritized serializability, respectively. They are combined for prioritized conditional serializability.
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50

Huang, Yichen, Hao Lin y Di Zhang. "Analysis of the baud rate of the UART to affects the data". Highlights in Science, Engineering and Technology 61 (30 de julio de 2023): 200–205. http://dx.doi.org/10.54097/hset.v61i.10295.

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This article explores the impact of different baud rates on Universal Asynchronous Receiver/Transmitter (UART) asynchronous serial communication. It discusses the frame format and calculation method of baud rate error, as well as the main reasons for error, such as clock error, sampling error, line noise, data bit error, and software delay. To ensure reliable communication, it is essential to test and debug the actual baud rate and adjust it accordingly. The study found that higher expected baud rates resulted in higher baud rate errors, affecting transmission distance, speed, reliability, and system complexity. The appropriate baud rate should be selected based on specific application scenarios and requirements. Higher baud rates are needed for high-speed transmissions, while lower baud rates are required for long transmission distances or high reliability requirements. However, further research is needed to determine the impact of unallocated baud rates on data. Overall, this article provides valuable insights into the development of UART.
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