Artículos de revistas sobre el tema "Sequential logic circuits"
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JAHANIRAD, HADI y KARIM MOHAMMADI. "SEQUENTIAL LOGIC CIRCUITS RELIABILITY ANALYSIS". Journal of Circuits, Systems and Computers 21, n.º 05 (agosto de 2012): 1250040. http://dx.doi.org/10.1142/s0218126612500405.
Texto completoWatt, A. "Astables and sequential logic circuits". Electronics Education 1990, n.º 2 (1990): 7–8. http://dx.doi.org/10.1049/ee.1990.0021.
Texto completoAndrews, Lauren B., Alec A. K. Nielsen y Christopher A. Voigt. "Cellular checkpoint control using programmable sequential logic". Science 361, n.º 6408 (20 de septiembre de 2018): eaap8987. http://dx.doi.org/10.1126/science.aap8987.
Texto completoUpadhyay, Shipra, R. A. Mishra, R. K. Nagaria y S. P. Singh. "DFAL: Diode-Free Adiabatic Logic Circuits". ISRN Electronics 2013 (10 de febrero de 2013): 1–12. http://dx.doi.org/10.1155/2013/673601.
Texto completoBasu, Shaunak y Subhashree Basu. "Reversible Logic Synthesis of Sequential Circuits". International Journal of Computer Applications 129, n.º 11 (17 de noviembre de 2015): 29–32. http://dx.doi.org/10.5120/ijca2015906999.
Texto completoZhang, Li Min, Zhi Wei Yang, Yao Kun Pang, Tao Zhou, Chi Zhang y Zhong Lin Wang. "Tribotronic triggers and sequential logic circuits". Nano Research 10, n.º 10 (14 de junio de 2017): 3534–42. http://dx.doi.org/10.1007/s12274-017-1564-9.
Texto completoLevin, Iliya, Osnat Keren y Vladimir Ostrovsky. "Synthesis of sequential circuits by using linearization". Facta universitatis - series: Electronics and Energetics 20, n.º 3 (2007): 461–77. http://dx.doi.org/10.2298/fuee0703461l.
Texto completoJagadeesan, Neeraja, B. Saman, M. Lingalugari, P. Gogna y F. Jain. "Sequential Logic Circuits Using Spatial Wavefunction Switched (SWS) FETs". International Journal of High Speed Electronics and Systems 24, n.º 03n04 (septiembre de 2015): 1550011. http://dx.doi.org/10.1142/s0129156415500111.
Texto completoMONTEIRO, JOSÉ, SRINIVAS DEVADAS y ABHIJIT GHOSH. "RETIMING SEQUENTIAL CIRCUITS FOR LOW POWER". International Journal of High Speed Electronics and Systems 07, n.º 02 (junio de 1996): 323–40. http://dx.doi.org/10.1142/s0129156496000141.
Texto completoHudli, Anand V. y Raghu V. Hudli. "Temporal Logic Based Hierarchical Test Generation for Sequential VLSI Circuits". VLSI Design 2, n.º 1 (1 de enero de 1994): 69–80. http://dx.doi.org/10.1155/1994/94514.
Texto completoShieh, M. D., C. L. Wey y P. D. Fisher. "Fault effects in asynchronous sequential logic circuits". IEE Proceedings E (Computers and Digital Techniques) 140, n.º 6 (noviembre de 1993): 327–32. http://dx.doi.org/10.1049/ip-e.1993.0046.
Texto completoChi-Ying Tsui, J. Monteiro, Massoud Pedram, Srinivas Devadas, A. M. Despain y B. Lin. "Power estimation methods for sequential logic circuits". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3, n.º 3 (septiembre de 1995): 404–16. http://dx.doi.org/10.1109/92.406998.
Texto completoSarica, Fatma y Avni Morgül. "Basic circuits for multi-valued sequential logic". Analog Integrated Circuits and Signal Processing 74, n.º 1 (29 de agosto de 2012): 91–96. http://dx.doi.org/10.1007/s10470-012-9946-0.
Texto completoSasipriya, P. y V. S. Kanchana Bhaaskaran. "Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)". Journal of Circuits, Systems and Computers 27, n.º 04 (6 de diciembre de 2017): 1850052. http://dx.doi.org/10.1142/s0218126618500524.
Texto completoJiang, Jin Tao, Li Fang Ye y Jian Ping Hu. "Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration". Applied Mechanics and Materials 39 (noviembre de 2010): 73–78. http://dx.doi.org/10.4028/www.scientific.net/amm.39.73.
Texto completoSaito, Ro, Christopher L. Ayala, Olivia Chen, Tomoyuki Tanaka, Tomohiro Tamura y Nobuyuki Yoshikawa. "Logic Synthesis of Sequential Logic Circuits for Adiabatic Quantum-Flux-Parametron Logic". IEEE Transactions on Applied Superconductivity 31, n.º 5 (agosto de 2021): 1–5. http://dx.doi.org/10.1109/tasc.2021.3061636.
Texto completoJiang, Jin Tao, Yu Zhang y Jian Ping Hu. "P-Type Adiabatic Sequential Circuits for Leakage Reduction of Nanometer Circuits". Advanced Materials Research 159 (diciembre de 2010): 155–61. http://dx.doi.org/10.4028/www.scientific.net/amr.159.155.
Texto completoMadec, Morgan, Elise Rosati y Christophe Lallement. "Feasibility and reliability of sequential logic with gene regulatory networks". PLOS ONE 16, n.º 3 (30 de marzo de 2021): e0249234. http://dx.doi.org/10.1371/journal.pone.0249234.
Texto completoMOHAMMADI, MAJID, ALIAKBAR NIKNAFS, MOHAMMAD ESHGHI y GERHARD W. DUECK. "DESIGN AND OPTIMIZATION OF SINGLE AND MULTIPLE-LOOP REVERSIBLE AND QUANTUM FEEDBACK CIRCUITS". Journal of Circuits, Systems and Computers 21, n.º 03 (mayo de 2012): 1250018. http://dx.doi.org/10.1142/s0218126612500181.
Texto completoAmirany, Abdolah y Ramin Rajaei. "Spin-Based Fully Nonvolatile Full-Adder Circuit for Computing in Memory". SPIN 09, n.º 01 (marzo de 2019): 1950007. http://dx.doi.org/10.1142/s2010324719500073.
Texto completoKAO, CHI-CHOU y YEN-TAI LAI. "IMPROVED TIME-MULTIPLEXED FPGA ARCHITECTURE AND ALGORITHM FOR MINIMIZING COMMUNICATION COST DESIGNS". Journal of Circuits, Systems and Computers 22, n.º 05 (9 de mayo de 2013): 1350033. http://dx.doi.org/10.1142/s0218126613500333.
Texto completoKumaresan, Raja Sekar, Marshal Raj y Lakshminarayanan Gopalakrishnan. "Design and implementation of a nano magnetic logic barrel shifter using beyond-CMOS technology". Journal of Electrical Engineering 73, n.º 1 (1 de febrero de 2022): 1–10. http://dx.doi.org/10.2478/jee-2022-0001.
Texto completoButyrlagin, Nikolay, Nikolay Chernov, Nikolay Prokopenko y Vladislav Yugai. "Linear Logic Synthesis of Multi-Valued Sequential Circuits". Advances in Science, Technology and Engineering Systems Journal 4, n.º 6 (2019): 430–42. http://dx.doi.org/10.25046/aj040654.
Texto completoBrowne, Clarke, Dill y Mishra. "Automatic Verification of Sequential Circuits Using Temporal Logic". IEEE Transactions on Computers C-35, n.º 12 (diciembre de 1986): 1035–44. http://dx.doi.org/10.1109/tc.1986.1676711.
Texto completoWu, S. F. y P. D. Fisher. "Automating the design of asynchronous sequential logic circuits". IEEE Journal of Solid-State Circuits 26, n.º 3 (marzo de 1991): 364–70. http://dx.doi.org/10.1109/4.75015.
Texto completoAssaf, Mansour, Leslie-Ann Moore, Sunil Das, Satyendra Biswas y Scott Morton. "Low-level logic fault testing ASIC simulation environment". World Journal of Engineering 11, n.º 3 (1 de junio de 2014): 279–86. http://dx.doi.org/10.1260/1708-5284.11.3.279.
Texto completoXiao, Lin Rong, Xiang Xu y Shi Yan Ying. "Dual-Edge Triggered T Flip-Flop Structure Using Quantum-Dot Cellular Automata". Advanced Materials Research 662 (febrero de 2013): 562–67. http://dx.doi.org/10.4028/www.scientific.net/amr.662.562.
Texto completoFeldman, Alexander, Ingo Pill, Franza Wotawa, Ion Matei y Johan De Kleer. "Efficient Model-Based Diagnosis of Sequential Circuits". Proceedings of the AAAI Conference on Artificial Intelligence 34, n.º 03 (3 de abril de 2020): 2814–21. http://dx.doi.org/10.1609/aaai.v34i03.5670.
Texto completoSasipriya, P. y V. S Kanchana Bhaaskaran. "Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL)". International Journal of Engineering & Technology 7, n.º 3 (19 de julio de 2018): 1548. http://dx.doi.org/10.14419/ijet.v7i3.14632.
Texto completoMatrosova, Anjela Yu, Evgeny V. Mitrofanov, Sergey A. Ostanin, Nataly B. Butorina, Elena G. Pakhomova y Sergey A. Shulga. "Detection and masking of trojan circuits in sequential logic". Vestnik Tomskogo gosudarstvennogo universiteta. Upravlenie, vychislitel'naya tekhnika i informatika, n.º 42 (1 de febrero de 2018): 89–99. http://dx.doi.org/10.17223/19988605/42/10.
Texto completoPomeranz, Irith. "Invariant States and Redundant Logic in Synchronous Sequential Circuits". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, n.º 6 (junio de 2007): 1171–75. http://dx.doi.org/10.1109/tcad.2006.885832.
Texto completoChen, J. E., C. L. Lee y W. Z. Shen. "Single-fault fault-collapsing analysis in sequential logic circuits". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10, n.º 12 (1991): 1559–68. http://dx.doi.org/10.1109/43.103505.
Texto completoJahanirad, H. "Efficient reliability evaluation of combinational and sequential logic circuits". Journal of Computational Electronics 18, n.º 1 (7 de diciembre de 2018): 343–55. http://dx.doi.org/10.1007/s10825-018-1288-4.
Texto completoDebany, Warren H. "Coverage of Node Shorts Using Internal Access and Equivalence Classes". VLSI Design 1, n.º 1 (1 de enero de 1993): 71–85. http://dx.doi.org/10.1155/1993/42309.
Texto completoStamoulis, Georgios I. "A Monte-Carlo Approach for the Estimation of Average Transition Probabilities in Sequential Logic Circuits". Active and Passive Electronic Components 24, n.º 2 (2001): 69–85. http://dx.doi.org/10.1155/2001/41403.
Texto completoHoushmand, Pouran y Majid Haghparast. "Design of a novel quantum reversible ternary up-counter". International Journal of Quantum Information 13, n.º 05 (agosto de 2015): 1550038. http://dx.doi.org/10.1142/s0219749915500380.
Texto completoJone, Wen-Ben, Nigam Shah, Anita Gleason y Sunil R. Das. "PGEN: A Novel Approach to Sequential Circuit Test Generation". VLSI Design 4, n.º 3 (1 de enero de 1996): 149–65. http://dx.doi.org/10.1155/1996/68463.
Texto completoUemura, Taiki, Yoshiharu Tosaka, Hideya Matsuyama, Keiji Takahisa, Mitsuhiro Fukuda y Kichiji Hatanaka. "Robust Flip-Flop Circuit against Soft Errors for Combinational and Sequential Logic Circuits". Japanese Journal of Applied Physics 48, n.º 4 (20 de abril de 2009): 04C070. http://dx.doi.org/10.1143/jjap.48.04c070.
Texto completoNi, Hai Yan y Jian Ping Hu. "Near-Threshold Flip-Flops Using Clocked Adiabatic Logic in Nanometer CMOS Processes". Key Engineering Materials 460-461 (enero de 2011): 837–42. http://dx.doi.org/10.4028/www.scientific.net/kem.460-461.837.
Texto completoBarkalov, Alexander, Larysa Titarenko, Kazimierz Krzywicki y Svetlana Saburova. "Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment". Electronics 10, n.º 8 (10 de abril de 2021): 901. http://dx.doi.org/10.3390/electronics10080901.
Texto completoAndaloussi, Issam y Moulay Brahim Sedra. "A design of sequential reversible circuits by reversible gates". International Journal of Engineering & Technology 9, n.º 2 (18 de abril de 2020): 397. http://dx.doi.org/10.14419/ijet.v9i2.30451.
Texto completoCao, Ruiping y Jianping Hu. "Near-Threshold Computing and Minimum Supply Voltage of Single-Rail MCML Circuits". Journal of Electrical and Computer Engineering 2014 (2014): 1–10. http://dx.doi.org/10.1155/2014/836019.
Texto completoChi-Ying Tsui, J. Monteiro, M. Pedram, S. Devadas, A. M. Despain y B. Lin. "Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence]". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 4, n.º 4 (diciembre de 1996): 495. http://dx.doi.org/10.1109/tvlsi.1996.544414.
Texto completoVenkatasubramanian, Ramakrishnan, Sujan K. Manohar y Poras T. Balsara. "NEM Relay-Based Sequential Logic Circuits for Low-Power Design". IEEE Transactions on Nanotechnology 12, n.º 3 (mayo de 2013): 386–98. http://dx.doi.org/10.1109/tnano.2013.2252923.
Texto completoHarris, M. S. "Computer-aided design techniques for low power sequential logic circuits". Microelectronics Journal 29, n.º 6 (junio de 1998): 363. http://dx.doi.org/10.1016/s0026-2692(97)00073-6.
Texto completoDe Micheli, G. "Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros". IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 5, n.º 4 (octubre de 1986): 597–616. http://dx.doi.org/10.1109/tcad.1986.1270230.
Texto completoMancini, Toni, Annalisa Massini y Enrico Tronci. "Parallelization of Cycle-Based Logic Simulation". Parallel Processing Letters 27, n.º 02 (junio de 2017): 1750003. http://dx.doi.org/10.1142/s0129626417500037.
Texto completoLiu, Wenting y Qun Sun. "Research on a design method of pneumatic logic control system". Measurement and Control 54, n.º 5-6 (mayo de 2021): 1105–12. http://dx.doi.org/10.1177/00202940211020336.
Texto completoMahmood, Ausif y William I. Baker. "An Evaluation of Parallel Synchronous and Conservative Asynchronous Logic-Level Simulations". VLSI Design 4, n.º 2 (1 de enero de 1996): 91–105. http://dx.doi.org/10.1155/1996/56545.
Texto completoYakunin, A. N., Aung Myo San y Khant Win. "Improving Performance of a Multi-Bit Arithmetic Logic Unit". Proceedings of Universities. Electronics 26, n.º 1 (febrero de 2021): 40–53. http://dx.doi.org/10.24151/1561-5405-2021-26-1-40-53.
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