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1
Said, Nasri. "Evaluation de la robustesse des technologies HEMTs GaN à barrière AlN ultrafine pour l'amplification de puissance au-delà de la bande Ka". Electronic Thesis or Diss., Bordeaux, 2024. http://www.theses.fr/2024BORD0425.
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La filière GaN est stratégique pour l'Union Européenne car elle permet d'améliorer la puissance et le rendement des systèmes radar et de télécommunication, notamment dans les bandes S à Ka (jusqu'à 30 GHz). Pour répondre aux besoins des futures applications, telles que la 5G et les systèmes militaires, le développement des technologies GaN vise à augmenter les fréquences jusqu'aux ondes millimétriques. Cela nécessite d'optimiser l'épitaxie et la réduction de la longueur de grille à moins de 150 nm, ainsi que l'utilisation de barrières ultrafines (<10 nm) pour éviter les effets de canaux courts. La substitution de la barrière AlGaN par du AlN représente une solution pour maintenir de bonnes performances tout en miniaturisant les composants. Dans ces travaux de thèse, plusieurs variantes technologiques à barrière AlN ultrafine (3 nm) sur des canaux GaN non-dopés de différentes épaisseurs, développées par le laboratoire IEMN sont étudiés. L'évaluation des performances et de la robustesse de ces technologies, cruciale pour leur qualification et utilisation dans des missions à long-terme, sont ainsi menées en mode DC et RF afin de définir les zones de sécurité de fonctionnement (SOA) et d’identifier les mécanismes de dégradation.La campagne de caractérisation DC et pulsée a révélé une faible dispersion des composants après leur stabilisation électrique, reflétant une bonne maîtrise technologique : ceci permet par ailleurs des études statistiques et des analyses génériques plus pertinentes sur l’ensemble des lots de composants étudiés. L'analyse de la sensibilité des dispositifs à des températures allant jusqu'à 200°C a prouvé la forte stabilité thermique des performances en mode diode et transistor, en suivant les indicateurs paramétriques représentatifs des modèles électriques des composants (courants de saturation et courants de fuite, tension de seuil, taux de retard aux commandes entrée sortie, …). L’ajout d’une barrière arrière AlGaN sur une couche tampon moyennement dopée C a réglé le compromis entre confinement des électrons et densités de pièges. Les tests de vieillissement accéléré en mode DC à différents points de polarisation et en mode RF par paliers de puissance d’entrée ont montré que la barrière arrière AlGaN confère une meilleure stabilité des courants de fuite et des courbes I(V) statiques, une réduction des effets de piégeage et d'auto-échauffement, ainsi qu'une extension de la SOA-DC opérationnelle. Les tests de vieillissement accéléré en mode dynamique à 10 GHz sur des HEMTs avec différents espacements grille-drain ont montré que la SOA-RF ne dépend pas de cet espacement, mais plutôt de la capacité de la grille à supporter des signaux RF élevés, avant dégradation brutale de cette dernière. En utilisant une méthode de modélisation non linéaire originale, prenant en compte le phénomène d'auto-polarisation, les dispositifs avec barrière AlGaN se sont révélés plus robustes également en RF. Cela se traduit par leur compression plus tardive de gain, allant jusqu’à +10dB et sans dégradation électrique ainsi que structurelle apparente (observée par photoluminescence). Indépendamment de la variante AlN/GaN, le mécanisme de dégradation en stress RF correspond au claquage abrupt de la grille Schottky conduisant à sa défaillance. Ces résultats prouvent que les composants sont plus sensibles aux conditions de polarisation DC qu’au niveau de signal RF injecté [...]The GaN industry is strategic for the European Union because it enhances the power and efficiency of radar and telecommunication systems, especially in the S to Ka bands (up to 30 GHz). To meet the needs of future applications such as 5G and military systems, GaN technology development aims to increase frequencies to the millimeter-wave range. This requires optimizing epitaxy and reducing the gate length to less than 150 nm, as well as using ultrathin barriers (<10 nm) to avoid short-channel effects. Replacing the AlGaN barrier with AlN is a solution to maintain good performance while miniaturizing devices. In this thesis, several technological variants with an ultrathin AlN barrier (3 nm) on undoped GaN channels of various thicknesses, developed by the IEMN laboratory, are studied. The evaluation of the performance and robustness of these technologies, crucial for their qualification and use in long-term profil missions, is conducted in both DC and RF modes to define the safe operating areas (SOA) and identify degradation mechanisms.The DC and pulsed characterization campaign revealed low component dispersion after electrical stabilization, reflecting good technological control. This also allows for more relevant statistical studies and generic analyses across all component batches studied. The sensitivity analysis of the devices at temperatures up to 200°C demonstrated strong thermal stability in diode and transistor modes, following parametric indicators representative of the electrical models of the components (saturation currents and leakage currents, threshold voltage, gate and drain lags rates, ...). The addition of a AlGaN back-barrier on a moderately C-doped buffer layer resolved the trade-off between electron confinement and trap densities. Accelerated aging tests in DC mode at various biasing conditions and in RF mode by input power steps showed that the AlGaN back-barrier provides better stability in leakage currents and static I(V) curves, reduces trapping and self-heating effects, and extends the operational DC-SOA.Dynamic accelerated aging tests at 10 GHz on HEMTs with different gate-drain spacings showed that the RF-SOA does not depend on this spacing but rather on the gate's ability to withstand high RF signals before abrupt degradation occurs. Using an original nonlinear modeling method that considers the self-biasing phenomenon, devices with the AlGaN back-barrier proved to be more robust in RF as well. This is reflected in their later gain compression, up to +10 dB, without apparent electrical or structural degradation (as observed by photoluminescence). Regardless of the AlN/GaN variant, the RF stress degradation mechanism corresponds to the abrupt breakdown of the Schottky gate, leading to its failure. These results indicate that the components are more sensitive to DC bias conditions than to the level of injected RF signals [...]
2
Peng, Hao. "Digital current mode control of DC-DC converters". Diss., Connect to online resource, 2006. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3207767.
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Lau, Wai Keung. "Current-mode DC-DC buck converter with dynamic zero compensation /". View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20LAU.
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Zhang, Ji M. Eng Massachusetts Institute of Technology. "Spread spectrum modulation system for burst mode DC-DC converters". Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/36906.
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Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references (leaves 91-92).
This thesis develops a spread spectrum switching system for DC-DC converters operating in burst mode. Burst mode DC-DC converters have high efficiency under low-power conditions in applications such as cell phones and notebook computers, but often produce noise in the audible range. This thesis explores a frequency modulation scheme and transient control that attenuates audible noise harmonics while minimizing the tradeoff for converter regulation, efficiency, and output voltage ripple.
by Ji Zhang.
M.Eng.
5
Mai, Yuan Yen. "Current-mode DC-DC buck converter with current-voltage feedforward control /". View abstract or full-text, 2006. http://library.ust.hk/cgi/db/thesis.pl?ECED%202006%20MAI.
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Wan, Kai. "Advanced current-mode control techniques for DC-DC power electronic converters". Diss., Rolla, Mo. : Missouri University of Science and Technology, 2009. http://scholarsmine.mst.edu/thesis/pdf/Wan_09007dcc80642d38.pdf.
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Thesis (Ph. D.)--Missouri University of Science and Technology, 2009.Vita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed May 4, 2009) Includes bibliographical references.
7
Mamarelis, Emilio. "Sliding mode control of DC/DC switching converters for photovoltaic applications". Doctoral thesis, Universita degli studi di Salerno, 2013. http://hdl.handle.net/10556/1018.
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2011 - 2012The maximum power point tracking (MPPT) is one of the most important features of a system that process the energy produced by a photovoltaic generator must hold. It is necessary, in fact, to design a controller that is able to set the value of voltage or current of the generator and always ensure the working within its maximum power point. This point can considerably change its position during the day, essentially due to exogenous variations, then sunshine and temperature. The MPPT techniques presented in literature and adopted in commercially devices operate a voltage control of the photovoltaic generator and require careful design of the control parameters. It is in fact complex obtain high performance both in stationary that strongly variable conditions of sunshine without a careful choice of some parameters that affect in both conditions the performance of the algorithm for the MPPT. In this thesis has been addressed the analysis of an innovative current-based MPPT technique: the sensing of the current in the capacitor placed in parallel with the photovoltaic source is one of the innovative aspects of the proposal. The controller is based on a nonlinear control technique called ”sliding mode” of which has been developed an innovative model that allow to obtain a set of conditions and enable the designing of the controller with extreme simplicity. The model also allow to demonstrate how the performance of this MPPT control tecnique are independent not only from the characteristics and operating conditions of the photovoltaic generator, but also by the parameters of the switching converter that implements the control. This property allows a significantly simplification in the designing of the controller and improve the performance in presence of rapid changes of the irradiance. An approach to the dynamic analysis of a class of DC/DC converters controlled by a sliding mode based maximum power point tracking for photovoltaic applications has been also presented. By referring to the boost and SEPIC topologies, which are among the most interesting ones in photovoltaic applications, a simple analytical model is obtained. It accounts for the sliding mode technique that allows to perform the maximum power point tracking of the photovoltaic generator connected at the converters input terminals. Referring to the previous approach, a correction term allowing to have an increased accuracy of the model at high frequencies has been also derived. The control technique proposed has been implemented by means of low cost digital controller in order to exploit the potential offered by the hardware device and optimize the performance of the controller. An extensive experimental analysis has allowed to validate the results of the research. The laboratory measurements were conducted on prototypes of DC/DC converters, boost and SEPIC, carried out by Bitron SpA. There are a considerable experimental tests both in the time and in the frequency domain , both using source generator in laboratory than photovoltaic panels. The results and theoretical simulations have found a large validation through laboratory measurements. [edited by author]
XI n.s.
8
Hekman, Thomas P. "Analysis, simulation, and fabrication of current mode controlled DC-DC power converters". Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1999. http://handle.dtic.mil/100.2/ADA374067.
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Thesis (M.S. in Electrical Engineering) Naval Postgraduate School, December 1999."December 1999". Thesis advisor(s): John G. Ciezki. Includes bibliographical references (p. 91-94). Also available online.
9
Baglan, Fuat Onur. "Design Of An Educational Purpose Multifunctional Dc/dc Converter Board". Master's thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/2/12610103/index.pdf.
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In this thesis a multifunctional DC/DC converter board will be developed for utilization as an educational experiment set in the switched-mode power conversion laboratory of power electronic courses. The board has a generic power-pole structure allowing for easy configuration of various power converter topologies and includes buck, boost, buck-boost, flyback, and forward converter topologies. All the converters can be operated in the open-loop control mode with a switching frequency range of 30-100 kHz and a maximum output power of 20 W. Also the buck converter can be operated in voltage mode control and the buck-boost converter can be operated in peak-current-mode control for the purpose of demonstrating the closed loop control performance of DC/DC converters. The designed board allows for experimentation on the DC/DC converters to observe the macroscopic (steadystate/ dynamic, PWM cycle and low frequency) and microscopic (switching dynamic) behavior of the converters. In the experiments both such characteristics can be clearly observed such that students at basic learning level (involving only the macroscopic behavior), and students at advanced learning level (additionally involving the parasitic effects) can benefit from the experiments. The thesis reviews the switch mode conversion principles, gives the board design and proceeds with the experiments illustrating the capabilities of the experimental system.
10
Saini, Dalvir K. "True-Average Current-Mode Control of DC-DC Power Converters: Analysis, Design, andCharacterization". Wright State University / OhioLINK, 2018. http://rave.ohiolink.edu/etdc/view?acc_num=wright1531776568809249.
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Meola, Marco. "Design and modeling of a digital controller for multi mode DC-DC convertes". Doctoral thesis, Università degli studi di Trieste, 2010. http://hdl.handle.net/10077/3677.
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2008/2009Convertitori dc-dc in grado di fornire una elevata efficienza per un ampio intervallo di valori di carico trovano il loro impiego in tutte quelle applicazioni dove dispositivi alimentati a batteria vengono utilizzati. In particolare, l’ottimizzazione dell’efficienza di tali convertitori per basse correnti di carico `e uno degli argomenti pi`u stimolanti nella progettazione di convertitori dc-dc. Nei convertitori multi-modo tale efficienza viene massimizzata mediante l’utilizzo di strategie di controllo diverse in funzione della corrente di uscita. In quest’ambito, il controllo di convertitori a commutazione `e tradizionalmente ottenuto per via analogica tramite l’impiego di circuiti integrati dedicati. Tuttavia, mano a mano che i sistemi di potenza diventano sempre pi`u complessi e spesso costituiti a loro volta da sotto-sistemi fra loro interagenti, il classico concetto di controllo si `e gradualmente evoluto nella pi`u generale tematica del power management, richiedendo funzionalit`a difficilmente implementabili nei controllori analogici. L’elevata flessibilit`a offerta dai controllori digitali e la loro predisposizione ad implementare sofisticate strategie di controllo, insieme alla programmabilit`a dei parametri del controllore, fanno del controllo digitale una attraente alternativa per il miglioramento delle prestazioni dei convertirori dc-dc multi-modo. Tuttavia, il punto debole pi`u evidente di un controllore digitale risiede nelle prestazioni dinamiche a catena chiusa da esso ottenibili. I tempi impiegati per la conversione analogico-digitale della grandezza da controllare, i ritardi di calcolo cos`ı come i ritardi associati al campionamento pongono limiti severi alla massima banda di controllo ottenibile in un convertitore controllato digitalmente. Ulteriori limitazioni sono inoltre imposte dagli effetti di quantizzazione nella catena di controllo. Per le ragioni sopra esposte, la realizzazione di controllori digitali in grado di essere competitivi (in termini di prestazioni dinamiche) rispetto alle classiche soluzioni analogiche `e materia di 3 intensa attivit`a scientifica nonch´e interesse industriale. Inoltre, sebbene il controllo digitale appare capace di soddisfare le esigenze sopra menzionate, i convertitori dc-dc a controllo analogico dominano ancora il mercato. Infatti, il controllo digitale di convertitori dc-dc soffre della mancanza del solido know-how posseduto dai controllori analogici, risultando cos`ı meno accessibile. Questo lavoro di tesi si inquadra nel contesto cos`ı delineato. L’attivit`a principale svolta riguarda la progettazione e simulazione di controllori dc-dc a controllo digitale con l’obbiettivo di studiare l’ottimizzazione dell’efficienza per piccole correnti di carico. In questa tesi la struttura di un controllore digitale multi-modo per convertitori a basso costo e bassa consumo di potenza `e presentata. Criteri decisionali sulla scelta della strategia di controllo a seconda delle condizioni di carico sono proposti e testati su prototipo sperimentale di convertitore dc-dc dove il controllo digitale `e implementato in una FPGA. Inoltre, lo sviluppo di un modello a larghi segnali a tempo discreto dello stadio di potenza del convertitore, studiato appositamente per modellizzare il comportamento del convertitore nel passaggio da una strategia di controllo all’altra, costituisce un utile strumento per la progettazione di convertitori a commutazione sulla base dei criteri decisionali proposti, mettendo in luce le problematiche della progettazione di sistemi per il power management.
XXII Ciclo
1980
12
Siu, Man. "Design of voltage-mode buck converter with end-point prediction /". View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20SIU.
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Deng, Songquan. "CONTROL AND TOPOLOGY IMPROVEMENTS IN HALF-BRIDGE DC-DC CONVERTERS". Doctoral diss., University of Central Florida, 2005. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2749.
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Efficiency and transient response are two key requirements for DC-DC converters. Topology and control are two key topics in this dissertation. A variety of techniques for DC-DC converter performance improvement are presented in this work. Focusing on the efficiency issue, a variety of clamping techniques including both active and passive methods are presented after the ringing issues in DC-DC converters are investigated. By presenting the clamping techniques, a big variety of energy management concepts are introduced. The active bridge-capacitor tank clamping and FET-diode-capacitor tank clamping are close ideas, which transfer the leakage inductor energy to clamping capacitor to prevent oscillation between leakage inductor and junction capacitor of MOSFETs. The two-FET-clamping tank employs two MOSFETs to freewheeling the leakage current when the main MOSFETs of the half-bridge are both off. Driving voltage variation on the secondary side Synchronous Rectifier (SR) MOSFETs in self-driven circuit due to input voltage variation in bus converter applications is also investigated. One solution with a variety of derivations is proposed using zerner-capacitor combination to clamping the voltage while maintaining reasonable power losses. Another efficiency improvement idea comes from phase-shift concept in DC-DC converters. By employing phase-shift scheme, the primary side and the secondary side two MOSFETs have complementary driving signals respectively, which allow the MOSFET to be turned on with Zero Voltage Switching (ZVS). Simulation verified the feasibility of the proposed phase-shifted DC-DC converter. From the control scheme point of view, a novel peak current mode control concept for half-bridge topologies is presented. Aiming at compensating the imbalanced voltage due to peak current mode control in symmetric half-bridge topologies, an additional voltage compensation loop is used to bring the half-bridge capacitor voltage back to balance. In the proposed solutions, one scheme is applied on symmetric half-bridge topology and the other one is applied on Duty-cycle-shifted (DCS) half-bridge topology. Both schemes employ simple circuitry and are suitable for integration. Loop stability issues are also investigated in this work. Modeling work shows the uncompensated half-bridge topology cannot be stabilized under all conditions and the additional compensation loop helps to prevent the voltage imbalance effectively.Ph.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
14
Tsai, Fu-Sheng. "Constant-frequency, clamped-mode resonant converters". Diss., Virginia Polytechnic Institute and State University, 1989. http://hdl.handle.net/10919/54800.
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Two novel clamped-mode resonant converters are analyzed. These clamped-mode converters operate at a constant frequency while retaining many desired features of conventional resonant converters such as fast responses, zero-voltage turn-on or zero-current turn-off, and low EMI levels, etc. The converters are able to regulate the output from no load to full load and are particularly suitable for off-line, high-power applications.
To provide insights to the operations and derive design guidelines for the clamped-mode resonant converters, a complete dc characterization of both the clamped-mode series-resonant converter and the clamped-mode parallel-resonant converter, operating above and below resonant frequency, is performed. State-plane analysis techniques are employed. By portraying the converters' operation on a state-plane diagram, various circuit operating modes are identified. The boundaries between different operating modes are determined. The regions for natural and force commutation of the active switches are defined. Important dc characteristics, such as control-to-output transfer ratio, rms inductor current, peak capacitor voltage, rms switch currents, average diode currents, switch turn-on currents, and switch turn-off currents are derived to facilitate the converter designs.
To illustrate the converter designs in different operating regions, several design examples are given. Finally, three prototype circuits are built to verify the analytical results.Ph. D.
15
Al-Baidhani, Humam A. "Design and Implementation of Simplified Sliding-Mode Control of PWM DC-DC Converters for CCM". Wright State University / OhioLINK, 2020. http://rave.ohiolink.edu/etdc/view?acc_num=wright1590930594283361.
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劉育廷. "Digital Current Mode DC-DC Converter". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/91935440386309142214.
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Chang, Chia-Hsien y 張嘉顯. "A New Current-mode DC-DC Converter with Adaptive Mode-hopping Mechanisms". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/28313625519805443371.
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碩士元智大學
電機工程學系
96
In this thesis, presented is a high-efficient current-mode DC-DC converter with adaptive mode-hopping mechanism. By employing a current sensing technique, the mode-hopping mechanism enables the mode switching between CCM and DCM according to the load current so as to maintain a high conversion efficiency regardless of the operational status of the applications. Moreover, the level of the load current for mode switching is programmable depending on the applications. Power loss and conversion efficiency analyses are also studied and presented. According to the simulation results, the efficiency of the DC-DC converter can be up to 94% while the maximum peak-to peak output voltage ripple is less than 20mV and the output current ranges between 50mA and 350mA. The DC-DC converter operates at a switching frequency from 0.3 to 1.7MHz from a supply voltage ranging from 2.4 to 4.2V. The DC-DC converter was implemented in TSMC 0.35-μm 2P4M CMOS process with die size of 2.07 mm2. Except the external inductor, capacitor and feedback resistors, all the devices including the power switches are on chip.
18
Chang, Chung-Hsing y 張崇興. "Multiphase DC/DC Converter with Dual Mode Control". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/f5vb22.
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碩士中原大學
電機工程研究所
93
High performance voltage-regulator-modules (VRMs) for the new generation of microprocessors have many strict and challenging specifications that include high power-density, high output-current capability, low output-voltage deviation and fast transient-response. The most popular VRM topology is a multiphase buck DC/DC converter. With traditional voltage-mode and current-mode control schemes, the response is not fast enough during large load transients. The slower response requires more output capacitors with additional cost and space. If switching frequency is increased for faster response, it could cause efficiency and thermal problems. With Hysteretic mode control, its switching frequency is influenced by component tolerance and PCB layout. The operation of wide frequency range causes difficulties in efficiency optimization and Electromagnetic Interference (EMI) treatments. In this thesis, a multiphase DC/DC converter with a dual control mode is studied. The presented scheme combines voltage and Hysteretic control modes and has the merits of high efficiency, simple control and fast transient response. It can be used for single-phase also and built in integrated circuit without additional cost and space. The operating principles and design criteria are analyzed and discussed in detail. A 1.3V four-phase laboratory prototype with 20V input voltage and 80A maximum load was simulated and tested to verify the feasibility of the proposed scheme. The results are satisfactory.
19
Yang, Chih-Wei y 楊智偉. "Terminal Sliding Mode Control of DC-DC Buck Converter". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/40287493094885340856.
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碩士中原大學
電機工程研究所
97
Sliding mode control is widely used in recent years to deal with the control problems of nonlinear systems. In this dissertation we applied terminal sliding mode control (TSMC) which is different from traditional sliding mode control on DC - DC buck converter design. It not only retains the advantages of sliding mode control but also includes terminal convergence characteristics. Furthermore, the system stability is discussed using Lyapunov function analysis. When considering the actual derivation error uncertainty in passive components, the controller is proceeded by adding an adaptive machine into adaptive terminal sliding mode control (ATSMC). As a result, the system uncertainty is allowed, i.e. the controller provides high robustness. In addition, Barbalat's lemma is also applied for stability analysis. To verify the control performances, we first perform simulations in the output voltage control when the load and input source are uncertain, i.e., the load changes and input changes. Next, the DC-DC Buck converter control is implemented. The adaptive terminal sliding mode controller is realized using dSPACE 1104 and Simulink toolbox. Experiment results show satisfactory performance even under load and the input voltage variations.
20
Yu-Hui, Sung y 宋玉惠. "Implementation of 8MHz Current-Mode Buck DC-DC Converter". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/17297645957351678156.
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碩士國立交通大學
電機學院IC設計產業專班
95
This thesis proposes a new DC-DC switching converter with a high switching frequency for reducing the size of the output filter. Owing to the high switching frequency, the on-chip output filter in DC-DC switching converter is possible in the future. Thus, how to develop a DC-DC switching converter with high switching frequency is important in today’s technology. Therefore, a compact solution is needed to effectively reduce the footprint area of the power management module in system-on-chip (SoC) systems. Furthermore, a high performance power converter module is also needed to provide a regulated and stable supply voltage to the SoC systems because the operation voltage of the SoC systems is too low to have a good signal-to-noise ratio. For providing a high performance supply voltage, the current-mode technique is utilized to get better line and load regulations. However, the current sensing accuracy and response time is seriously affected by the high switching frequency. A high accuracy and small response time current sensor is also proposed in this thesis. In thesis, we implement an 8 MHz current-mode buck DC-DC converter with good line and load regulations. The chip is implemented by tsmc 2P4M 0.35u CMOS process. The range of the operation voltage is from 2.6V to 3.3V. The load regulation and line regulation are 0.88uV/mA and 4.67mV/V. The chip features smaller output filter elements and fast response, which makes it suitable for power management in the portable devices.
21
Tso, Chung-Hsien y 左仲先. "HIGH PERFORMANCE CMOS CONTROLLERS FOR SWITCHING-MODE DC-DC CONVERTERS". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/xvfzh6.
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博士國立交通大學
電子工程系所
93
Several high performance controllers for switching-mode DC–DC converter are proposed. In order to achieve fast transient response, high efficiency, stable operation, and low switching noise, analysis and circuit design of the controllers are comprehensively investigated in this dissertation. Controllers are realized by CMOS analog and digital mixed-mode integrated circuits techniques. Free-running control is the simplest among all control topologies of switching power supply. However, the switching frequency depends on the operating conditions and power filters. Thus, the use is limited in noise sensitive devices. Besides, only few related literatures provide analytical insights into this kind of control. Two common free-running control topologies, ripple control and constant on-time control, are investigated. Circuits architectures are proposed to improve these controllers. Switching frequency of the constant on-time regulator can be also stabilized by adjusting the on time according to input and output voltages. Unstable operation of free-running control due to noise on feedback signal is discussed. A novel compensation circuit is proposed to improve the frequency response and noise immunity of constant on-time control. This compensation circuit uses a built-in integrator to generate a ramp signal to trigger the comparator. Therefore, it is less susceptible to noise. Stable operation and fast response are obtained. The proposed control circuits are realized in a 1 um CMOS technology with area of 5.2 mm^2 including the I/O pads. Experimental results showed fast response during load and line transients. Efficiency from 86 % to 93 % is obtained over a load range from 10 mA to 3 A under 5 V input voltage and 2.476 V output voltage. The load and line regulations are 0.032 %/A and 0.034 %/V that are superior to conventional current-mode and voltage-mode PWM control. Switching frequency of the ripple control regulator can be synchronized by a novel method that uses a phase-locked loop to lock the switching signal with an input clock. Voltage-mode and current-mode control circuits are presented for the buck and boost power stages, respectively. Both steady-state response and small-signal model are discussed. Derived transfer functions are useful for designing the control loop and compensation network. By taking linearization of the relationship of switching frequency and delay, a linear model is obtained for loop parameter design and PLL stability analysis. The proposed regulators were simulated in transistor level using SPICE. Input voltage and output voltage are 20 V and 1.5 V respectively for the buck regulator. During the steady state, the switching frequency was locked at 300 kHz. Load regulation is 0.0046 %/A and line regulation is 0.028 %/V. Input voltage and output voltage are 2.4 V and 3.3 V respectively for the boost regulator. During the steady state, the switching frequency was locked at 300 kHz. Load regulation is 0.96 %/A and line regulation is 0.75 %/V. More simulation results are also shown in this dissertation. Analog controllers are sensitive to noise, process, temperature and component variations. Tuning these controllers is quite complicated as well. The uses of digital controllers are limited by their complex circuits and higher cost. In this thesis, the proportional current feedback technique is proposed to accelerate transient response of the voltage-mode switching regulators. With this technique, the complexity of analog-to-digital conversion circuits and digital computation circuits is greatly reduced. Performance can be easily tuned by adjusting the parameters. Instead of transistor-level simulation, a Matlab behavior model is build to simulate time-domain system response. Fast and accurate results can be obtained from this model. The proposed control circuits are realized in a 0.6 um CMOS technology with area of 1.8×1.8 mm^2 including the I/O pads. Experimental results showed the output voltage dropped 150 mV and recovered to static tolerance in 100 us during a load transient from 2 A to 20 A. The performance of the regulator met strict requirements and verified the simulation results.
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Shiau, Jung-yi y 蕭仲義. "Sliding mode voltage control of DC/DC buck-boost converter". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/99441053412284159291.
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碩士正修科技大學
機電工程研究所
97
Comparing with the conventional power converters, switching power converters possess the advantages of high efficiency, small size and wide range of voltage operation, so that they are widely applied in the application of portable electronic products and equipment in recent years. This thesis mainly focuses on the development and implementation of Buck/Boost converter with a sliding mode voltage controller, to achieve the stable desired controlled voltage output. Firstly, the stable sliding surface function is designed due to the control system. It can be observed that the entire controlled region can be divided into three subspaces. Based on Lyapunov stable theory, the controller is proposed to enforce the system trajectory from the arbitrary point toward the sliding surface in the finite time, remain on the surface and slides along to equilibrium point exponentially. In addition, based on a fixed frequency pulse width modulation technology, the proposed controller is realized by controlling the duty cycle of switch device to achieve desired stable voltage output under the influence of loading variation. The hardware system includes the integrated design of converters, controller, sawtooth signal generation circuit and drive circuit. According to the simulation software of PSpice, the, the encouraged system performance is validated by the testing of different loadings. Finally, the hardware system is implemented by analogic circuit to verify feasibility of the proposed control structure according to the different voltage inputs and loading uncertainties.
23
Chen, Chien-cheng y 陳建成. "A High Efficiency Current Mode Control DC-DC Buck Converter". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/07494232505610402844.
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碩士國立中央大學
電機工程研究所
99
In this changing rapidly era of electronic technology, the major demands of portable electronics are short, thin, and full functionalities. These sub-circuits of the portable electronics, which use batteries for power sources, need a stable supply voltage generating by power converters. These power converters must have low power consumption and high efficiency to extend the service time of portable electronics. Thus, a high efficiency current mode buck converter is presented in this thesis. The proposed buck converter uses current-mode controlling mechanism to accelerate the transient response during the transient period. It senses the current variation of the output inductor. Therefore, it achieves low operating current and high efficiency by removing the V-to-I converting circuit. This buck converter has better performance in the specification of efficiency comparing with traditional buck converter with current-mode controlling. This current-mode buck converter is fabricated with TSMC 0.35um 3.3 V CMOS process. In the proposed buck converter, the operation voltage is form 3.8 V to 5.5 V, the output voltage is 3.3 V, the output current is from 0.05 A to 1 A, and the highest efficiency is 97.4 %. The line regulation and load regulation are 17.5 mV/V and 1.15 mV/A, respectively. The chip area is 2.46 mm2.
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Lu, Ju-Ping y 呂如萍. "Common-Mode Noise Reduction Techniques in DC/DC Power Converters". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/52829416950097816084.
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碩士國立成功大學
工程科學系碩博士班
96
Power converters generate rapidly changing voltages and currents due to the switching actions of the power switch. Accordingly, the electromagnetic pollution introduced by line-connected power converters can propagate by conduction on the power line. In this thesis, the measuring principle of the conduction noise, differential/common mode noise separation and the measurement parameters of the spectrum analyzer will be described first. Then, the noise source, coupling paths in a DC/DC power converter, and the suppression methods of them will be discussed. In addition, PSpice simulations and experimental results are used to validate the theoretical analysis. Major noise in power converters arises from the MOSFET switch and rectifier diode. The switching noise generated from MOSFETs is related to the rise/fall time, duty ratio and switching frequency. If the rise/fall time increases properly, the switching noise generated from MOSFET can be effectively suppressed effectively. On the other hand, the switching noise resulted from rectifier diode is related to the sharp edge of the current waveform when diode current returns to zero. If this current change rate di/dt of the recovery current is reduced, the diode switching noise can be thereby suppressed effectively. The common-mode noise conduction interferences are the most difficult problem to be dealt with. They come from the charge and discharge of the parasitic capacitances of the heat sink and transformer windings in the power converter. Since the common-mode current is expressed as i=C(dv/dt)，the static point can be used to achieve dv/dt=0 and thus i=0. Additionally, the transformer winding terminals with high changing voltage can be placed far away from each other to reduce their parasitic capacitances. The balanced circuit method or common-mode current cancellation technique is useful to suppress the noise. Y capacitors or shields can be applied to besiege the common-mode currents. As a result, common-mode currents flowing through the LISN can be reduced. In this thesis, common-mode reduction techniques in DC/DC power converters are investigated and validated by experimental results. For various noise sources and coupling paths, the noise suppression methods proposed in this thesis are beneficial for power engineers who suffer from noise problems in power electronics.
25
Chin-HongChen y 陳津宏. "Average-Current-Mode Non-inverting Buck-Boost DC-DC Converter". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/77890091296649204660.
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碩士國立成功大學
電機工程學系碩博士班
98
With the increasing use of electrical portable devices, an efficient power management solution is needed to extend battery life. Generally, basic switching regulators (e.g., buck, boost) are not capable of using the entire battery output characteristics effectively (e.g., 2.7–4.2 V for Li-ion) to provide a fixed output voltage (e.g., 3.3V). In this work, an average-current-mode non-inverting buck-boost dc-dc converter is introduced, which can use the full-range output voltage of Li-ion battery with the advantages of high power efficiency, faster transient response, and excellent noise immunity. The die area of this chip is 1.9x1.7 , which is fabricated by using Taiwan Semiconductor Manufacturing Company (TSMC) 0.35μm 2P4M 5V mixed-signal polycide process. The converter output is set to 3.3V, and can supply up to 300 mA load current. Its input votlage can range from 2.5V to 5V.
26
楊文魁. "Sliding Mode Control Design of Switching Buck DC-DC Converters". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/23680105019427113826.
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碩士國立中興大學
電機工程學系
90
Abstract This thesis develops modified PID(proportional-integral-derivative)-like sliding mode controllers for single buck DC-DC converter and paralleled buck DC-DC converters. The single buck DC-DC converters can be modeled as linear averaged systems with changeable loads, noise and parameter perturbations of uncertain load. Two models with different chosen state variables are employed to design the sliding mode controllers for buck DC-DC converters; the first one has two state variables of VO and iC and the second one three state variables of VO, iC and iL. These proposed control methods have been verified by computer simulation and their control performance has been shown to be satisfactory. Modified PID-like slide model control laws for parallel connected buck DC-DC converters are presented to achieve both equal output current distribution and robust voltage regulation. Simulation results show that such controllers improve greatly the dynamic performance of parallel buck DC-DC converters, the controlled output voltage is robust against load disturbances and the controlled output current of each converter cell is identical. Finally, an interleave control method is introduced in order to reduce the switching loss and the ripple of output current.
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Chen, Chun-Min y 陳浚敏. "DC-to-DC Switched Power Converter by Sliding-Mode Control". Thesis, 2000. http://ndltd.ncl.edu.tw/handle/33953850600968248809.
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碩士國立交通大學
電機與控制工程系
88
In this thesis, we discuss the application and implementation of the sliding-mode control on the DC-to-DC power converters. Follow the ploe-assignment method based on the specified conditions to find an appropriate sliding function by selecting suitable eigenvalues. According to the sliding-mode theory and Lyapnuov theory, a reaching-and-sliding region and a stable-sliding region will be found. In addition, the variable structure method in phase-plane is recommended to steer the system to this intersection from the initial condition, and get to the equilibrium. We apply this design to DC-to-DC power converters, and the simulation results demonstrate the success of the proposed sliding-mode technique. The controller is carried out to guarantee the feasibility of this theory.
28
Wu, Kun You y 吳坤祐. "Sliding-Mode Control Applied to Buck DC-DC Converter Design". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/90185981336242031257.
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碩士國立交通大學
電機學院碩士在職專班電機與控制組
95
A sliding mode controller with the error integration between output voltage and command voltage for PWM-based Buck DC-DC converter is proposed. Constant switching frequency can be achieved with the proposed approach. For the controller design, this thesis adopts sliding mode control theorem because of its well-know robustness for system uncertainty. Without load estimator in the controller, this closed-loop system ideally should convert power flow into the prescribed form in spite of the load variation. With the unknown load condition we choose a sliding function with an integral term of error function such that the system is stabilized on the sliding surface. Then design the control algorithm such that the system reaches the sliding mode in a finite time. The simulation of the proposed closed-loop control scheme is illustrated to process fast transient response and robustness to load variation.
29
Su, Yu-Cheng y 蘇育正. "Design of The Switched-Mode Boost DC-to-DC Controller". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/7fg5u9.
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碩士國立臺北科技大學
電機工程系所
94
The thesis proposes a switched-mode boost DC-DC converter, which doesn’t need a sawtooth wave generator and a error amplifier. By using a comparator and a fixed-duty-cycle oscillator, the proposed controller will offer a high DC voltage of 15V, for the small size, Liquid Crystal Display (LCD).The proposed structure is different from those who are made with Pulse Width Modulation (PWM) or Pulse Frequency Modulation (PFM) techniques. In traditional PWM or PFM structure, they need to control switch by comparing the sawtooth wave signal with an error signal that provided by an error amplifier. This design is implemented with TSMC 0.35 2P4M mixed-mode process, the area is 1.15×1.27mm2. The chip delivers regulated 15V 1% output voltage from a supply voltage of 3.0V~3.6V, frequency varies from 200KHz to 880KHz, and the power efficiency is greater than 80%, while provided 20mA~50mA of loading current.
30
Mahakhuda, R. K. "Application of sliding mode controller in DC/AC and DC-DC power converter system". Thesis, 2014. http://ethesis.nitrkl.ac.in/5606/1/E-58.pdf.
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Maintaining good voltage regulation at output and having fast dynamic response under sudden load fluctuation are extremely important in distributed generation (DG) as well as uninterrupted power supply (UPS) systems. This work presents a fixed frequency hysteresis current (FFHC) controller, which is implemented on the basis of sliding mode control (SMC) technique and fixed frequency current controller with a hysteresis band. The controller have the benefit of hysteretic current control having fast dynamic responses and reduces the disadvantages of the variable switching frequency. For this work elliptical sliding surface was taken.These have been verified and compared with the carrier based pulse width modulated (PWM) voltage controller under the same load fluctuation. The proposed method is then applied to islanded single phase - voltage source inverter (VSI) system. The results show that the dynamic response is quite faster than that of widely used PWM-controlled inverter systems. The DC voltage that is required for the inverter input is supposed to given from the output of PV panel with buck converter.In PV system sliding mode control is used to track the maximum power point .Here inverter and buck converter connected to PV array are taken separately.
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Hsu, Hsin-Ju y 許昕茹. "Automatic Layout Synthesis Tool for DC-DC Current-Mode Buck Converter". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/64617872141924593723.
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碩士國立中央大學
電機工程學系
105
In our days, lots of electronic product are made of analog/mixed-signal (AMS) intergrated circuits (ICs), such as portable devices, medical equipment, communication product and automobile electronics etc. Nowadays, with the growing demands for portable devices, Time-to-Market cycle still keeps shrinking. Electronic design automation (EDA) tools are the keys to speed up the device process. There are many existing EDA tools for digital circuits on the market. However, the EDA tools for AMS circuits are still not popular. Because analog circuits are often sensitive to small signals response, their layouts are often manually designed by experienced designers. Therefore, AMS circuit design has become the bottleneck in SoC design flow. In order to increase the circuit performance and shorten design process, we perpose an automatic layout synthesis tool for DC-DC current-mode control buck converters in the thesis. This synthesis tool is able to generate the final layout of the target circuit automatically from given specification. The design environment is developed with C++ and Tcl/Tk programming language. The required layout can be generated in Laker automatically and pass the DRC/LVS verification. The post-layout simulation results also satisfy the required specification.
32
Tzeng, Jun-Jie y 曾俊傑. "A Voltage Mode DC-DC Buck Converter with Duty Cycle Detector". Thesis, 2015. http://ndltd.ncl.edu.tw/handle/7e7u5q.
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碩士國立中央大學
電機工程學系
103
The proposed buck converter with duty cycle detector uses the voltage mode control as the feedback loop for system stability. The PID compensator integrated into the chip to reduce the number of passive components. It is good to portable electronic devices design thinness and lightweight. With duty cycle detector, proposed buck converter can detect the load current information to slow down the system operating frequency for reducing power consumption in very light load. The zero current detector prevents the inverse current, and reduces the conduction loss in light load. The dead time detector is used to optimize the dead time of control signal. The efficiency of system can be improved. This buck converter has been fabricated with 0.18 um 3.3 V CMOS process. In the proposed buck converter, the operating voltage is from 2.7 V to 4.2 V, the output voltage is 1 V, the operating frequency is from 0.77 MHz to 1.44 MHz, the load current is from 25 mA to 1 A, and the peak efficiency is 88.87 %. The line regulation and load regulation are 6.67 mV/V and 1.02 mV/A, respectively. The chip area is 1.3225 mm2.
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Lin, Wallance y 林俊宏. "Simulation of Control Characteristics of Current-Mode DC-DC Boost Converters". Thesis, 2007. http://ndltd.ncl.edu.tw/handle/49844798338880989762.
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碩士國立臺灣大學
電機工程學研究所
95
There are two feedback loops, Voltage Control Loop and Current Control Loop, in Current Mode DC-DC Converter. According to Small Signal Model, two groups of Loop-gain function can be obtained, and they are T1 and T2. It can be verified by these two groups of Loop-gain function that whether the whole system is working under stable and reliable condition. In order to build up a stable and reliable system, Voltage Control Loop and Current Control Loop are essential to be understood. Hence, a reliable converter can only be hence designed through T1 and T2, together with Voltage Control Loop and Current Control Loop. In which, T2 can be easily obtained by measurement; however, T1 has yet long been obtained by any measurement or simulation. Most importantly, T1 has been the benchmark of system reliability. In recent years, many researchers make effort to use SIMPLIS software to obtain simulated T1 of Buck Converter, yet this method cannot be applied in Boost Converter since the structure of Boost Converter is different from Buck converter, let alone that Boost Converter has the feature of Position Zero. Position Zero has great influence to reliability from to view of Frequency Response. Therefore, to understand right plane Zero is important to effect of T1 and T2. This dissertation aims to make use of SIMPLIS to simulate T1 in Boost Converter and other important parameters. Then the simulation result will be cross-verified by experiments. The purpose of this dissertation is to research the accuracy of simulation result of SIMPLIS. Although by collocating mathematic equation and MATHCAD, Crossover Frequency and Phase Margin can be obtained in T1 Frequency Response, this method does not consider the influence of MOSFET Turn on Resistance, Operation Amplifier, and Delay based on the reason that mathematic equation is designed under perfect conditions. Therefore, by SIMPLIS simulation, real conditions will be considered into equation in addition to no demand of extra equation. The result is importantly beneficial to recent DC Converter development in high frequency since demand of controlling bandwidth is increasing dramatically. To conclude, this dissertation purpose is to use the change of MOSFET Turn on Resistance to examine and verify that SIMPLIS can prove the accuracy of the result made by mathematic equation and also make it convincing that Loop Gain made by SIMPLIS simulation is reliable.
34
楊隆生. "Modeling and analysis of a new switching mode DC/DC converter". Thesis, 1992. http://ndltd.ncl.edu.tw/handle/48763075155443968228.
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Jiunn-HungShiau y 蕭俊竑. "Current Sensorless Multi-mode Digital DC-DC Controller for DVS Application". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/47390614754488809419.
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Chin-WeiChang y 張晉瑋. "Single-Inductor Four-Switch Voltage-Mode Buck-Boost DC-DC Converter". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/73162145114489630707.
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碩士國立成功大學
電機工程學系碩博士班
98
With the rapid progress of semiconductor technology, all kinds of electronic products, especially portable electronics, appear in the market day by day. The most indispensable component for portable products is the battery that supplies energy, and determines the service life of the product. The supply voltage of the battery will drop gradually with time, which means the input voltage supplying by battery can be higher than, equal to, or lower than the desired voltage. Therefore, a DC-DC converter is required to convert the time-varying battery voltage to a fixed desired output voltage. Moreover, it would be better to have a high-efficiency buck-boost converter that can either step up or step down the battery voltage to a desired voltage. The conventional buck-boost converters include flyback, inverting buck-boost, SEPIC, boost circuit with back end connects a buck circuit, etc. The above mentioned structures are either more complicated, more chip/PCB area, or having poor efficiency. Especially the inverting buck-boost architecture, the polarity of its output voltage is reversed. A four-switch buck-boost DC-DC converter was designed and presented in this thesis. The presented converter improves the efficiency, reduces the external component and chip/PCB area, compared with the above mentioned prototypes. The input voltage range of the presented converter is 2.5~5.0V, its output voltage is set to 3.3V, load current range is 60~300 mA and switching frequency is 1 MHz. The chip was implemented by Taiwan Semiconductor Manufacturing Company (TSMC) 0.35μm 2P4M 5V mixed-signal polycide process, patronized by National Chip Implementation Center (CIC). The die area of the chip is 1.38 ×1.80 mm2, with 40 S/B package.
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Ju, Jian-Liang y 朱建亮. "The Study of Switching Mode DC/DC Converters for Electric Motorcycles". Thesis, 2001. http://ndltd.ncl.edu.tw/handle/44906057000432126459.
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碩士義守大學
電機工程學系
89
A forward converter suitable for electric motorcycles is proposed in this thesis. The converter can always provide a stable constant DC voltage for the motorcycle during accelerating or decelerating operation. Voltage stress suppression and energy recovery are achieved by the passive snubber of the main switch. Operation modes of the proposed circuit are introduced. Experimental results of a 12V, 120W forward converter with maximum efficiency of 90.84% are presented. Both of the voltage-mode controlled and the current-mode controlled forward converters for the operation characters of electric motorcycles are compared. The results of the performance comparison can be the referral to choose converters for electric motorcycles.
38
Lin, Shoei-Chuen y 林水春. "Adaptive Backstepping Sliding Mode Control of PWM Buck DC-DC Converters". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/81375244215126509093.
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碩士國立中興大學
電機工程學系
91
Abstract This thesis develops methodologies and techniques for design and implementation a buck DC-DC converter using a digital signal processor (DSP). The converter is modeled as a linear averaged system with changeable loads. Two models with different chosen state variables are employed to design the backstepping sliding mode controllers for the buck DC-DC converter; the first one has the two state variables of and , and the second one has the two state variables of and . Using singular perturbation method, the reduced order model is derived in order to show that the effect of can be ignored and the buck DC-DC converters can be well approximated by the reduced order model. Based on the reduced order model, novel control approaches are proposed to control a single and parallel-connected buck DC-DC converters. Furthermore, the adaptive backstepping sliding mode control approaches are presented for the output voltage regulation of these buck DC-DC converters, if their system parameters are unknown. These proposed control methods have been verified by computer simulation and implemented utilizing a standalone digital signal processor (DSP) TMS320C542 from Texas Instruments. Experimental results show that the proposed control method is proven to be capable of given satisfactory control performance.
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Pai-YiWang y 王派益. "A Current-Mode DC-DC Buck Converter with Variable-Frequency Controller". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/53741969966548917400.
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碩士國立成功大學
電機工程學系碩博士班
98
A current-mode buck converter with integrated analog variable-frequency controller (VFC) is implemented in this thesis. With the highly growing market of the portable devices, a compact, fast, low cost and high efficiency regulator is needed in power management solutions. Design of the regulator with small inductor can significantly reduce the PCB size and cost; and it is inherently faster than general solutions due to higher filtering bandwidth. But small inductor makes higher output voltage ripple, thus the design of switching frequency is limited by the rated output voltage ripple; faster switching frequency though effectively reduces the output voltage ripple without increasing the output capacitance, but introduces more frequency-dependent power loss such as switching loss and dead-time loss into regulator. By adapting VFC, which can be easily integrated in a chip without complex control circuts, the efficiency can be optimized under rated output voltage ripple with small inductor value. Furthermore, the proposed current-mode regulator provides an improvement of the current sensor, reducing the controller power loss while maintaining sensing accuracy, and eliminating the sensed noise, providing better sensed signal quality to the feedback loop, significantly promoting the performance of current-mode switching regulator. This current-mode buck regulator is fabricated with TSMC 0.35um 3.3/5V Mixed-Signal CMOS process. The total chip area is about 1.06 x 0.995 mm2. Verification results show that power saving at least 5mW and 20mW during light load and heavy load individually.
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Lin, Yu-Min y 林育民. "DESIGN OF DC/DC BUCK CONVERTER WITH TERMINAL SLIDING MODE CONTROL". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/94567133218679607091.
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Su, Chien-Chung y 蘇建中. "Design of a Dual-phase Voltage-mode DC-DC Buck Converter". Thesis, 2019. http://ndltd.ncl.edu.tw/handle/264jbg.
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碩士國立臺灣海洋大學
電機工程學系
107
In recent years, technology has developed rapidly, and electronic products have become thinner and can use many functions at the same time. Lithium batteries need to provide many voltages to different system modules at the same time, and the usage time will be shortened as the power consumption becomes larger. An effective power management system is an important thing in a limited volume and battery capacity. A good power management system can extend the life of the product and reduce the frequency of battery charging. In view of the above mentioned problems, this thesis proposes a dual-phase voltage mode buck converter. The dual-phase converter is connected in parallel with two sets of power transistors. Compared with single phase, it has the advantages of low ripple voltage, large load current, and improving the efficiency of heavy loads. The phase control circuit uses one phase delay circuit to generate another set of switching signals. Since the converter has only one control circuit in dual-phase design, the number of control circuits can be reduced, thus the area of the entire chip can be decreased. The overall design is implemented with the TSMC 0.35um mixed signal 2P4M CMOS 5V process provided by the Taiwan Semiconductor Research Center (TSRI). The converter uses the voltage mode. The input voltage range is 3.3V~4.2V, the output voltage is 1.8V, the operating frequency is 1MHz per phase, the load range is 50mA~1000mA, the output ripple voltage is below 10mV, and the overall maximum efficiency is 92.17%.
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"Fixed-frequency multi-mode multiple-output arbitrary-type DC-DC switching-mode power converters with variable-frequency control". Thesis, 2010. http://library.cuhk.edu.hk/record=b6075258.
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Finally, a four-channel SIMO converter with direct combination but optimal switching sequence for arbitrary converter sequence and converter type is presented. The theoretical optimal 1st-order inductor waveform from this proposed control algorithm is introduced. FCL is involved in this design to realize the algorithm. Moreover, a current-modulated ramp signal, which couples to different controllers, is included to compensate the original deep correlated power stages. By using all of the proposed techniques, Measurement results show that both conduction loss and dynamic loss can be suppressed because of the optimized switching sequence. The load transient response time is around 100mus. The peak efficiency is 89% with a 2.5-V power supply. A maximum output power of 1.66W can be achieved.Firstly, a pseudo-PWM hysteresis voltage-mode buck converter is proposed. It achieves fast transient speed by the hysteresis control, estimable switching spectrum with a locking frequency and fast mode switching between PWM and PFM depending on the loading change. Measurement results show that the recovery time under the load transient is around 5mus, which is 5 times of the switching period. The boundary of the recovery time is defined by the value of the off-chip inductor.
Switching-mode power converter (SMPC) is an important circuit block in electronic systems. In the modem SMPC system, constant frequency voltage or current-mode control technique is commonly used. However, some limitations are raised due to some preliminary settings in the design. In this thesis, the switching frequency or period is no longer a constant but a design variable. Then, an additional frequency-control loop (FCL) is introduced in order to obtain a fixed frequency operation in the steady state. Three individual designs implemented with different types of FCL are proposed to verify the concept.
Then, a four-channel SIMO converter based on FCL is developed, together with auto-phase allocation technique. This circuit not only solves the problem of imbalance loading of different channels, but it also keeps the idle period of the inductor sufficient short in the full operation region. By combining with all channel controllers, FCL makes fast load transient response without degrading the power efficiency. Moreover, linear auto converter-type adaption technique is also used, which makes the converter surviving from a wide input range and output range. Measurement results show that the proposed converter can achieve a peak efficiency of 89%, a total output power of 1.46W, a load transient response time of less than 70muS, and an idle inductor period of <10%.
Zheng, Yanqi.
Adviser: Leung Ka Nang.
Source: Dissertation Abstracts International, Volume: 73-03, Section: B, page: .
Thesis (Ph.D.)--Chinese University of Hong Kong, 2010.
Includes bibliographical references.
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [201-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.
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Yang, Hong-Yuan y 楊鴻源. "Adaptive Capacitor Compensation Control Technique of Hysteretic Current Mode under Continuous Conduction Mode for DC-DC Boost Converters". Thesis, 2009. http://ndltd.ncl.edu.tw/handle/55708484291766282732.
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碩士國立交通大學
電機學院碩士在職專班電機與控制組
98
This paper proposes a modulated hysteretic current control (MHCC) technique to improve transient response of DC-DC boost converters, which suffer from low bandwidth due to the existence of right-half-plane (RHP) zero. The MHCC technique can automatically adjust the on-time value to rapidly increase the inductor current to shorten the transient response time. Besides, based on the characteristic of right-half-plane (RHP) zero, the compensation pole and zero are deliberately adjusted to achieve the system has an ultra-fast transient response in case of load transient condition and an adequate phase margin in steady state. Experimental results show the improvement in transient response is higher than 7.2 times when load current changes from light to heavy or vice versa compared to the conventional boost converter design. The power consumption overhead is merely 1%.
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"Digitally Controlled DC-DC Buck Converters with Lossless Current Sensing". Doctoral diss., 2011. http://hdl.handle.net/2286/R.I.14398.
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abstract: Current sensing ability is one of the most desirable features of contemporary current or voltage mode controlled DC-DC converters. Current sensing can be used for over load protection, multi-stage converter load balancing, current-mode control, multi-phase converter current-sharing, load independent control, power efficiency improvement etc. There are handful existing approaches for current sensing such as external resistor sensing, triode mode current mirroring, observer sensing, Hall-Effect sensors, transformers, DC Resistance (DCR) sensing, Gm-C filter sensing etc. However, each method has one or more issues that prevent them from being successfully applied in DC-DC converter, e.g. low accuracy, discontinuous sensing nature, high sensitivity to switching noise, high cost, requirement of known external power filter components, bulky size, etc. In this dissertation, an offset-independent inductor Built-In Self Test (BIST) architecture is proposed which is able to measure the inductor inductance and DCR. The measured DCR enables the proposed continuous, lossless, average current sensing scheme. A digital Voltage Mode Control (VMC) DC-DC buck converter with the inductor BIST and current sensing architecture is designed, fabricated, and experimentally tested. The average measurement errors for inductance, DCR and current sensing are 2.1%, 3.6%, and 1.5% respectively. For the 3.5mm by 3.5mm die area, inductor BIST and current sensing circuits including related pins only consume 5.2% of the die area. BIST mode draws 40mA current for a maximum time period of 200us upon start-up and the continuous current sensing consumes about 400uA quiescent current. This buck converter utilizes an adaptive compensator. It could update compensator internally so that the overall system has a proper loop response for large range inductance and load current. Next, a digital Average Current Mode Control (ACMC) DC-DC buck converter with the proposed average current sensing circuits is designed and tested. To reduce chip area and power consumption, a 9 bits hybrid Digital Pulse Width Modulator (DPWM) which uses a Mixed-mode DLL (MDLL) is also proposed. The DC-DC converter has a maximum of 12V input, 1-11 V output range, and a maximum of 3W output power. The maximum error of one least significant bit (LSB) delay of the proposed DPWM is less than 1%.Dissertation/Thesis
Ph.D. Electrical Engineering 2011
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Min-Shing, Wu. "Design and Analysis of a Boost Mode Switched-capacitor DC/DC Converter". 2005. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-2206200511305900.
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Ting-Hung, Wang. "Practical Simulations of Control Characteristics of a Current-Mode DC/DC Converter". 2006. http://www.cetd.com.tw/ec/thesisdetail.aspx?etdun=U0001-1107200620251200.
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Lai, Kuo-Ming y 賴國銘. "A Novel Sliding-mode Control of DC-to-DC Switched Power Converters". Thesis, 1998. http://ndltd.ncl.edu.tw/handle/37974898268058102243.
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碩士國立交通大學
電機與控制工程學系
86
This thesis applies the sliding-mode theory to the design of DC- to-DCswitched power converters, which are Buck (with parasitic resistance), Boost and Buck-Boost converters and modeled as bilinear systems. Anew design scheme ofconventional pole- assignment method. Further based on the sliding-modetheory, a reaching-and-sliding region and a stable-sliding region are derived and most importantly the equilibrium point is bounded in theirintersection and shown to be asymptotically stable. In addition,variable structure method in phase-plane is suggested to steer the system into this intersection from the initial condition. One simplesttype of sliding function is also discussed, which only requires the measurement of inductor current. Finally, simulation results demonstratethe success of the proposed sliding-mode technique.
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Chen, Tzu-An y 陳賜安. "The Study of Sliding-Mode control for the DC-DC Buck Converters". Thesis, 2008. http://ndltd.ncl.edu.tw/handle/36600761533747148476.
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碩士中華大學
電機工程學系(所)
96
The converter is a very common device in the electronic products. And the performances of the electronic products are affected heavily on the precision of the output voltage level of the converter. Due to the nonlinear switching characteristic of PWM converter, the design and control of the DC-DC converter is still a problem to be studied. In this study, the time-average model is used to approximate the dynamic behavior of converter, furthermore, the nonlinear state equation can be found as the plant of the control system. For the robust and precise output voltage level and the control of nonlinear characteristic of the converter, the integral sliding-mode control (ISMC) is studied to increase the ability of disturbance and noise rejection and reduce the influences of variations in the parameters and the input voltage level of converter. Finally, the feasibility of the control is verified by the experiments and computer simulations.
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Chiu, Chen-Yu y 邱辰宇. "High Efficiency DC-DC Converter with Voltage Mode Switch on Demand Modulation". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/c4vshv.
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Wang, Ting-Hung y 王珽弘. "Practical Simulations of Control Characteristics of a Current-Mode DC/DC Converter". Thesis, 2006. http://ndltd.ncl.edu.tw/handle/29901368562821291555.
Texto completoResumen
碩士國立臺灣大學
電機工程學研究所
94
In a current-mode controlled DC converter, there are two feedback loops: a current loop and a voltage loop. There are, therefore, two loop-gain functions T1 and T2 involved. Behavior of the two loop-gain functions affects system stability and converter performances. Therefore, knowledge about the actual circuit loop gains is critically important in the design of the converters. Two approaches to the design of current-mode converters are often mentioned. One uses the concept of the two loopgain functions T1 and T2, and the other uses a new converter transfer function Fin to describe the control plant when only the current loop is closed. Fin not only reveals stability issue but also provides information for the design of voltage-loop compensation. Obtaining these three functions under a realistic environment is the main focus of this thesis. In this thesis, procedures were proposed to simulate the two loop-gain functions T1 and T2, the inner loop transfer function Fin, current-loop gain Ti and voltage-loop gain Tv, for a current-mode controlled DC/DC Buck converter using SIMPLIS software. These models are practical to obtain, simple to use, accurate beyond switching frequency and are easily amendable to incorporate new converter configurations and new control schemes. Furthermore, the same SIMPLIS models can also be used to simulate time-domain waveforms without losing PWM switching frequency information. These models should provide useful information for both the converter circuit designers and the IC controller designers. In the thesis, a brief review of the control schemes of both voltage-mode and current-mode is given in Chapter 2. Basic concept of small-signal loop gain transfer functions is reviewed. A detailed description of the two loop gain functions T1 and T2 in current-mode controlled Buck converters in this chapter lays the foundation for Chapter 3, which is the main focus of this thesis. A step-by-step procedure is proposed to simulate loop gain T1 which is difficult to obtain using any other way. These simulation results were verified by using theoretical models. Chapter 4 concludes the thesis and suggests future research topics.