Artículos de revistas sobre el tema "RISC V processor"
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Pitcher, Graham. "RISC-V Powers IoT Apps Processor". New Electronics 51, n.º 4 (27 de febrero de 2018): 7. http://dx.doi.org/10.12968/s0047-9624(23)60141-5.
Texto completoGamino del Río, Iván, Agustín Martínez Hellín, Óscar R. Polo, Miguel Jiménez Arribas, Pablo Parra, Antonio da Silva, Jonatan Sánchez y Sebastián Sánchez. "A RISC-V Processor Design for Transparent Tracing". Electronics 9, n.º 11 (7 de noviembre de 2020): 1873. http://dx.doi.org/10.3390/electronics9111873.
Texto completoHongsheng, Zhang, Zekun Jiang y Yong Li. "Design of a dual-issue RISC-V processor". Journal of Physics: Conference Series 1693 (diciembre de 2020): 012192. http://dx.doi.org/10.1088/1742-6596/1693/1/012192.
Texto completoAn, Hyogeun, Sudong Kang, Guard Kanda y Kwangki Ryoo. "RISC-V Hardware Synthesizable Processor Design Test and Verification Using User-Friendly Desktop Application". Webology 19, n.º 1 (20 de enero de 2022): 4597–620. http://dx.doi.org/10.14704/web/v19i1/web19305.
Texto completoNúñez-Prieto, Ricardo, David Castells-Rufas y Lluís Terés-Terés. "RisCO2: Implementation and Performance Evaluation of RISC-V Processors for Low-Power CO2 Concentration Sensing". Micromachines 14, n.º 7 (4 de julio de 2023): 1371. http://dx.doi.org/10.3390/mi14071371.
Texto completoMichel Deves de Souza, Eduardo, Nathalia Nathalia Adriana de Oliveira, Douglas Almeida dos Santos Almeida dos Santos y Douglas Rossi de Melo. "RVSH - Um processador RISC-V para fins didáticos". Anais do Computer on the Beach 14 (3 de mayo de 2023): 450–52. http://dx.doi.org/10.14210/cotb.v14.p450-452.
Texto completoZhou, Weixin, Dehua Wu, Wan’ang Xiao, Shan Gao y Wanlin Gao. "A Novel Sleep Scheduling Strategy on RISC-V Processor". Journal of Physics: Conference Series 1631 (septiembre de 2020): 012028. http://dx.doi.org/10.1088/1742-6596/1631/1/012028.
Texto completoXue, Wang, Liu, Lv, Wang y Zeng. "An RISC-V Processor with Area-Efficient Memristor-Based In-Memory Computing for Hash Algorithm in Blockchain Applications". Micromachines 10, n.º 8 (16 de agosto de 2019): 541. http://dx.doi.org/10.3390/mi10080541.
Texto completoSantos, Douglas A., André M. P. Mattos, Douglas R. Melo y Luigi Dilillo. "Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip". Electronics 12, n.º 12 (6 de junio de 2023): 2557. http://dx.doi.org/10.3390/electronics12122557.
Texto completoGomes, Tiago, Pedro Sousa, Miguel Silva, Mongkol Ekpanyapong y Sandro Pinto. "FAC-V: An FPGA-Based AES Coprocessor for RISC-V". Journal of Low Power Electronics and Applications 12, n.º 4 (27 de septiembre de 2022): 50. http://dx.doi.org/10.3390/jlpea12040050.
Texto completoPietzsch, Marcus. "RISC-V Processor for Network Platforms According to ISO 26262". ATZelectronics worldwide 16, n.º 11 (noviembre de 2021): 8–13. http://dx.doi.org/10.1007/s38314-021-0691-y.
Texto completoGao, Shan, Wan’ang Xiao, Zhenghong Yang, Dehua Wu y Wanlin Gao. "A fast on-chip debugging design for RISC-V processor". Journal of Physics: Conference Series 1976, n.º 1 (1 de julio de 2021): 012056. http://dx.doi.org/10.1088/1742-6596/1976/1/012056.
Texto completoCheng, Yuan-Hu, Li-Bo Huang, Yi-Jun Cui, Sheng Ma, Yong-Wen Wang y Bing-Cai Sui. "RV16: An Ultra-Low-Cost Embedded RISC-V Processor Core". Journal of Computer Science and Technology 37, n.º 6 (30 de noviembre de 2022): 1307–19. http://dx.doi.org/10.1007/s11390-022-0910-x.
Texto completoJamieson, Peter, Huan Le, Nathan Martin, Tyler McGrew, Yicheng Qian, Eric Schonauer, Alan Ehret y Michel A. Kinsy. "Computer Engineering Education Experiences with RISC-V Architectures—From Computer Architecture to Microcontrollers". Journal of Low Power Electronics and Applications 12, n.º 3 (9 de agosto de 2022): 45. http://dx.doi.org/10.3390/jlpea12030045.
Texto completoB, Rajeshwari, Rithvik Kumar, Shweta P. Hegde, Manav Eswar Prasad, Vandhya D M y Bajrangabali B. "Dual Quaternion Hardware Accelerator for RISC-V based System". International Journal of Research and Scientific Innovation 09, n.º 05 (2022): 77–81. http://dx.doi.org/10.51244/ijrsi.2022.9506.
Texto completoLim, Seung-Ho, WoonSik William Suh, Jin-Young Kim y Sang-Young Cho. "RISC-V Virtual Platform-Based Convolutional Neural Network Accelerator Implemented in SystemC". Electronics 10, n.º 13 (23 de junio de 2021): 1514. http://dx.doi.org/10.3390/electronics10131514.
Texto completoGao, Shan, Dehua Wu, Wan’ang Xiao, Zetao Wang, Zhenghong Yang y Wanlin Gao. "A novel method for on-chip debugging based on RISC-V processor". MATEC Web of Conferences 355 (2022): 03055. http://dx.doi.org/10.1051/matecconf/202235503055.
Texto completoMIYAZAKI, Hiromu, Takuto KANAMORI, Md Ashraful ISLAM y Kenji KISE. "RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining". IEICE Transactions on Information and Systems E103.D, n.º 12 (1 de diciembre de 2020): 2494–503. http://dx.doi.org/10.1587/transinf.2020pap0015.
Texto completoLi, Jiemin, Shancong Zhang y Chong Bao. "DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA". Electronics 11, n.º 1 (30 de diciembre de 2021): 122. http://dx.doi.org/10.3390/electronics11010122.
Texto completoPatrick, Mark. "What's all the Hype About?" New Electronics 53, n.º 14 (11 de agosto de 2020): 22–23. http://dx.doi.org/10.12968/s0047-9624(22)61362-2.
Texto completoKwon, Donghyun, Dongil Hwang y Yunheung Paek. "A Hardware Platform for Ensuring OS Kernel Integrity on RISC-V". Electronics 10, n.º 17 (26 de agosto de 2021): 2068. http://dx.doi.org/10.3390/electronics10172068.
Texto completoCococcioni, Marco, Federico Rossi, Emanuele Ruffaldi y Sergio Saponara. "Vectorizing posit operations on RISC-V for faster deep neural networks: experiments and comparison with ARM SVE". Neural Computing and Applications 33, n.º 16 (28 de febrero de 2021): 10575–85. http://dx.doi.org/10.1007/s00521-021-05814-0.
Texto completoLi, Zhiyu, Yuhao Huang, Longfeng Tian, Ruimin Zhu, Shanlin Xiao y Zhiyi Yu. "A Low-Power Asynchronous RISC-V Processor With Propagated Timing Constraints Method". IEEE Transactions on Circuits and Systems II: Express Briefs 68, n.º 9 (septiembre de 2021): 3153–57. http://dx.doi.org/10.1109/tcsii.2021.3100524.
Texto completoMurabayashi, F., T. Yamauchi, H. Yamada, T. Nishiyama, K. Shimamura, S. Tanaka, T. Hotta, T. Shimizu y H. Sawamoto. "2.5 V CMOS circuit techniques for a 200 MHz superscalar RISC processor". IEEE Journal of Solid-State Circuits 31, n.º 7 (julio de 1996): 972–80. http://dx.doi.org/10.1109/4.508211.
Texto completoZhang, Haifeng, Xiaoti Wu, Yuyu Du, Hongqing Guo, Chuxi Li, Yidong Yuan, Meng Zhang y Shengbing Zhang. "A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System". Sensors 21, n.º 19 (28 de septiembre de 2021): 6491. http://dx.doi.org/10.3390/s21196491.
Texto completoSchmidt, Colin, John Wright, Zhongkai Wang, Eric Chang, Albert Ou, Woorham Bae, Sean Huang et al. "An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET". IEEE Journal of Solid-State Circuits 57, n.º 1 (enero de 2022): 140–52. http://dx.doi.org/10.1109/jssc.2021.3118046.
Texto completoTada, Jubee y Keiichi Sato. "An Implementation of a Grid Square Codes Generator on a RISC-V Processor". International Journal of Networking and Computing 12, n.º 1 (2022): 204–17. http://dx.doi.org/10.15803/ijnc.12.1_204.
Texto completode Oliveira, Adria B., Lucas A. Tambara, Fabio Benevenuti, Luis A. C. Benites, Nemitala Added, Vitor A. P. Aguiar, Nilberto H. Medina, Marcilei A. G. Silveira y Fernanda L. Kastensmidt. "Evaluating Soft Core RISC-V Processor in SRAM-Based FPGA Under Radiation Effects". IEEE Transactions on Nuclear Science 67, n.º 7 (julio de 2020): 1503–10. http://dx.doi.org/10.1109/tns.2020.2995729.
Texto completoCho, Hyungmin. "Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects". IEEE Access 6 (2018): 41302–13. http://dx.doi.org/10.1109/access.2018.2858773.
Texto completoKaneko, Hiroaki y Akinori Kanasugi. "An integrated machine code monitor for a RISC-V processor on an FPGA". Artificial Life and Robotics 25, n.º 3 (9 de marzo de 2020): 427–33. http://dx.doi.org/10.1007/s10015-020-00593-8.
Texto completoGarofalo, Angelo, Manuele Rusci, Francesco Conti, Davide Rossi y Luca Benini. "PULP-NN: accelerating quantized neural networks on parallel ultra-low-power RISC-V processors". Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 378, n.º 2164 (23 de diciembre de 2019): 20190155. http://dx.doi.org/10.1098/rsta.2019.0155.
Texto completoC, Rohan. "Design of a 32-Bit, Dual Pipeline Superscalar RISC-V Processor on FPGA: A Review". International Journal for Research in Applied Science and Engineering Technology 10, n.º 6 (30 de junio de 2022): 4044–46. http://dx.doi.org/10.22214/ijraset.2022.44654.
Texto completoYu, Hongjiang, Guoshun Yuan, Dewei Kong y Chuhuai Chen. "An Optimized Implementation of Activation Instruction Based on RISC-V". Electronics 12, n.º 9 (24 de abril de 2023): 1986. http://dx.doi.org/10.3390/electronics12091986.
Texto completoKalapothas, Stavros, Manolis Galetakis, Georgios Flamis, Fotis Plessas y Paris Kitsos. "A Survey on RISC-V-Based Machine Learning Ecosystem". Information 14, n.º 2 (21 de enero de 2023): 64. http://dx.doi.org/10.3390/info14020064.
Texto completoJaiswal, Nidhi. "Design of High Performance Core Micro-Architecture Based on RISC-V ISA for Low Power Applications". International Journal for Research in Applied Science and Engineering Technology 11, n.º 7 (31 de julio de 2023): 734–42. http://dx.doi.org/10.22214/ijraset.2023.54647.
Texto completoGuangTang, Jiancheng y Li. "Research and design of low-power, high-performance processor based on RISC-V instruction set architecture". Journal of Physics: Conference Series 2221, n.º 1 (1 de mayo de 2022): 012008. http://dx.doi.org/10.1088/1742-6596/2221/1/012008.
Texto completoRagini, Dr K. y Nidhi Jaiswal. "Design of High-Performance Core Micro-Architecture Based on 32- Bit RISC-V Instruction Set Architecture [ISA]". International Journal for Research in Applied Science and Engineering Technology 11, n.º 7 (31 de julio de 2023): 1025–33. http://dx.doi.org/10.22214/ijraset.2023.54791.
Texto completoNişancı, Görkem, Paul G. Flikkema y Tolga Yalçın. "Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms". Cryptography 6, n.º 3 (10 de agosto de 2022): 41. http://dx.doi.org/10.3390/cryptography6030041.
Texto completoAndorno, M., M. Andersen, G. Borghello, A. Caratelli, D. Ceresa, J. Dhaliwal, K. Kloukinas y R. Pejasinovic. "Rad-hard RISC-V SoC and ASIP ecosystems studies for high-energy physics applications". Journal of Instrumentation 18, n.º 01 (1 de enero de 2023): C01018. http://dx.doi.org/10.1088/1748-0221/18/01/c01018.
Texto completoRathi, C. Arul, G. Rajakumar, T. Ananth Kumar y T. S. Arun Samuel. "Design and Development of an Efficient Branch Predictor for an In-order RISC-V Processor". Journal of Nano- and Electronic Physics 12, n.º 5 (2020): 05021–1. http://dx.doi.org/10.21272/jnep.12(5).05021.
Texto completoRAO, Jinli, Tianyong AO, Shu XU, Kui DAI y Xuecheng ZOU. "Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor". IEICE Transactions on Information and Systems E101.D, n.º 11 (1 de noviembre de 2018): 2698–705. http://dx.doi.org/10.1587/transinf.2017icp0019.
Texto completoXin, Guozhu, Jun Han, Tianyu Yin, Yuchao Zhou, Jianwei Yang, Xu Cheng y Xiaoyang Zeng. "VPQC: A Domain-Specific Vector Processor for Post-Quantum Cryptography Based on RISC-V Architecture". IEEE Transactions on Circuits and Systems I: Regular Papers 67, n.º 8 (agosto de 2020): 2672–84. http://dx.doi.org/10.1109/tcsi.2020.2983185.
Texto completoCho, Hyungmin. "Correction to “Impact of Microarchitectural Differences of RISC-V Processor Cores on Soft Error Effects”". IEEE Access 7 (2019): 35034. http://dx.doi.org/10.1109/access.2019.2904033.
Texto completoZhou, Yuzhi, Xi Jin, Tian Xiang y Daolu Zha. "Enhancing energy efficiency of RISC-V processor-based embedded graphics systems through frame buffer compression". Microprocessors and Microsystems 77 (septiembre de 2020): 103140. http://dx.doi.org/10.1016/j.micpro.2020.103140.
Texto completoLe, Anh-Tien, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki y Cong-Kha Pham. "A cross-process Spectre attack via cache on RISC-V processor with trusted execution environment". Computers and Electrical Engineering 105 (enero de 2023): 108546. http://dx.doi.org/10.1016/j.compeleceng.2022.108546.
Texto completoZhou, Ziqiao y Michael K. Reiter. "Interpretable noninterference measurement and its application to processor designs". Proceedings of the ACM on Programming Languages 5, OOPSLA (20 de octubre de 2021): 1–30. http://dx.doi.org/10.1145/3485518.
Texto completoChen, Yuehai, Huarun Chen, Shaozhen Chen, Chao Han, Wujian Ye, Yijun Liu y Huihui Zhou. "DITES: A Lightweight and Flexible Dual-Core Isolated Trusted Execution SoC Based on RISC-V". Sensors 22, n.º 16 (10 de agosto de 2022): 5981. http://dx.doi.org/10.3390/s22165981.
Texto completoTaştan, İbrahim, Mahmut Karaca y Arda Yurdakul. "Approximate CPU Design for IoT End-Devices with Learning Capabilities". Electronics 9, n.º 1 (9 de enero de 2020): 125. http://dx.doi.org/10.3390/electronics9010125.
Texto completoHan, Xiaojing, Liang Liu, Zhe Zhang, Yufeng Sun, Jiahui Zhou y Hao Cai. "Design of a High Performance Vector Processor Based on RISIC-V Architecture". Journal of Physics: Conference Series 2560, n.º 1 (1 de agosto de 2023): 012027. http://dx.doi.org/10.1088/1742-6596/2560/1/012027.
Texto completoMach, Ján, Lukáš Kohútka y Pavel Čičák. "In-Pipeline Processor Protection against Soft Errors". Journal of Low Power Electronics and Applications 13, n.º 2 (10 de mayo de 2023): 33. http://dx.doi.org/10.3390/jlpea13020033.
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