Artículos de revistas sobre el tema "REVERSIBLE MULTIPLIER"
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HAGHPARAST, MAJID, MAJID MOHAMMADI, KEIVAN NAVI y MOHAMMAD ESHGHI. "OPTIMIZED REVERSIBLE MULTIPLIER CIRCUIT". Journal of Circuits, Systems and Computers 18, n.º 02 (abril de 2009): 311–23. http://dx.doi.org/10.1142/s0218126609005083.
Texto completoRashno, Meysam, Majid Haghparast y Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier". International Journal of Quantum Information 18, n.º 03 (abril de 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.
Texto completoRayudu, Kurada Verra Bhoga Vasantha, Dhananjay Ramachandra Jahagirdar y Patri Srihari Rao. "Design and testing of systolic array multiplier using fault injecting schemes". Computer Science and Information Technologies 3, n.º 1 (1 de marzo de 2022): 1–9. http://dx.doi.org/10.11591/csit.v3i1.p1-9.
Texto completoDurgam, Veena y Dr K. Ragini. "Design of 32x32 Reversible Unsigned Multiplier Using Dadda Tree Algorithm". ECS Transactions 107, n.º 1 (24 de abril de 2022): 16251–58. http://dx.doi.org/10.1149/10701.16251ecst.
Texto completoRaviteja, Ragoju, Mittapelli Kalyan Krishna, Gare Sandhya y N. Srinivasa Reddy. "Approximative Signed Wallace Tree Multiplier Using Reversible Logic". International Journal for Research in Applied Science and Engineering Technology 11, n.º 4 (30 de abril de 2023): 2474–78. http://dx.doi.org/10.22214/ijraset.2023.50668.
Texto completoZomorodi Moghadam, Mariam y Keivan Navi. "Ultra-area-efficient reversible multiplier". Microelectronics Journal 43, n.º 6 (junio de 2012): 377–85. http://dx.doi.org/10.1016/j.mejo.2012.02.004.
Texto completoEshack, Ansiya y S. Krishnakumar. "Reversible logic in pipelined low power vedic multiplier". Indonesian Journal of Electrical Engineering and Computer Science 16, n.º 3 (1 de diciembre de 2019): 1265. http://dx.doi.org/10.11591/ijeecs.v16.i3.pp1265-1272.
Texto completoSaravanan. "NOVEL REVERSIBLE VARIABLE PRECISION MULTIPLIER USING REVERSIBLE LOGIC GATES". Journal of Computer Science 10, n.º 7 (1 de julio de 2014): 1135–38. http://dx.doi.org/10.3844/jcssp.2014.1135.1138.
Texto completoAriafar, Zahra y Mohammad Mosleh. "Effective Designs of Reversible Vedic Multiplier". International Journal of Theoretical Physics 58, n.º 8 (24 de mayo de 2019): 2556–74. http://dx.doi.org/10.1007/s10773-019-04145-0.
Texto completoSaiAbhinav, B., M. Jaipal Reddy, Y. Siva Kumar y S. Sivanantham S.Sivanantham. "ASIC Design of Reversible Adder and Multiplier". International Journal of Computer Applications 109, n.º 10 (16 de enero de 2015): 6–10. http://dx.doi.org/10.5120/19222-0638.
Texto completoRashno, Meysam, Majid Haghparast y Mohammad Mosleh. "Designing of Parity Preserving Reversible Vedic Multiplier". International Journal of Theoretical Physics 60, n.º 8 (13 de julio de 2021): 3024–40. http://dx.doi.org/10.1007/s10773-021-04903-z.
Texto completoH.G, Rangaraju, Aakash Babu Suresh y Muralidhara K.N. "Design and Optimization of Reversible Multiplier Circuit". International Journal of Computer Applications 52, n.º 10 (30 de agosto de 2012): 44–50. http://dx.doi.org/10.5120/8242-1523.
Texto completoPourAliAkbar, Ehsan, Keivan Navi, Majid Haghparast y Midia Reshadi. "Novel Optimum Parity-Preserving Reversible Multiplier Circuits". Circuits, Systems, and Signal Processing 39, n.º 10 (8 de abril de 2020): 5148–68. http://dx.doi.org/10.1007/s00034-020-01406-w.
Texto completoBaraniya, Shweta y Sujeet Mishra. "Review Paper on Reversible Multiplier Circuit using Different Programmable Reversible Gate". International Journal of Electrical and Electronics Engineering 2, n.º 10 (25 de octubre de 2015): 16–20. http://dx.doi.org/10.14445/23488379/ijeee-v2i10p104.
Texto completoZhou, Rigui, Yang Shi, Hui’an Wang y Jian Cao. "Transistor realization of reversible “ZS” series gates and reversible array multiplier". Microelectronics Journal 42, n.º 2 (febrero de 2011): 305–15. http://dx.doi.org/10.1016/j.mejo.2010.11.008.
Texto completoRahman, Md M., Md M. Hossain, Lafifa Jamal y S. Nowrin. "Designing of a reversible fault tolerant booth multiplier". Bangladesh Journal of Scientific and Industrial Research 53, n.º 3 (18 de septiembre de 2018): 199–204. http://dx.doi.org/10.3329/bjsir.v53i3.38266.
Texto completoGholpe, Minal y Prasad Sangare. "ASIC Design of Reversible Multiplier Using Adiabatic Technique". International Journal of Computer Applications Technology and Research 6, n.º 2 (20 de febrero de 2017): 117–20. http://dx.doi.org/10.7753/ijcatr0602.1009.
Texto completoPourAliAkbar, Ehsan y Mohammad Mosleh. "An efficient design for reversible Wallace unsigned multiplier". Theoretical Computer Science 773 (junio de 2019): 43–52. http://dx.doi.org/10.1016/j.tcs.2018.06.007.
Texto completoIslam, M. S., M. M. Rahman, Z. Begum y M. Z. Hafiz. "Low Cost Quantum Realization of Reversible Multiplier Circuit". Information Technology Journal 8, n.º 2 (1 de febrero de 2009): 208–13. http://dx.doi.org/10.3923/itj.2009.208.213.
Texto completoH R, Bhagyalakshmi. "Optimized Multiplier Using Reversible Multicontrol Input Toffoli Gates". International Journal of VLSI Design & Communication Systems 3, n.º 6 (31 de diciembre de 2012): 27–40. http://dx.doi.org/10.5121/vlsic.2012.3603.
Texto completoAmrutha, P. y P. A. Sunny Dayal. "A Novel Design of Low Power Reversible Multiplier". IOSR Journal of Electronics and Communication Engineering 9, n.º 3 (2014): 08–14. http://dx.doi.org/10.9790/2834-09350814.
Texto completoSakode, Prof V. M. y Prof A. D. Morankar. "Reversible Multiplier with Peres Gate and Full Adder". IOSR Journal of Electronics and Communication Engineering 9, n.º 3 (2014): 43–50. http://dx.doi.org/10.9790/2834-09364350.
Texto completoSanjeevaiah, Girija y Sangeetha Bhandari Gajanan. "Design of efficient reversible floating-point arithmetic unit on field programmable gate array platform and its performance analysis". International Journal of Electrical and Computer Engineering (IJECE) 13, n.º 1 (1 de febrero de 2023): 697. http://dx.doi.org/10.11591/ijece.v13i1.pp697-708.
Texto completoRajmohan, V. y O. Uma Maheswari. "Design of Compact Baugh-Wooley Multiplier Using Reversible Logic". Circuits and Systems 07, n.º 08 (2016): 1522–29. http://dx.doi.org/10.4236/cs.2016.78133.
Texto completoRaveendran, Sithara, Pranose J. Edavoor, Y. B. Nithin Kumar y M. H. Vasantha. "Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic". IEEE Access 9 (2021): 108119–30. http://dx.doi.org/10.1109/access.2021.3100892.
Texto completoDayal, Anand y Himanshu Shekhar. "A Result Analysis of ASIC Design of Reversible Multiplier Circuit". International Journal of Computer Applications 160, n.º 8 (22 de febrero de 2017): 40–43. http://dx.doi.org/10.5120/ijca2017913071.
Texto completoAlexander, S. "Design and Implementation of Efficient Reversible Multiplier Using Tanner EDA". International Journal of MC Square Scientific Research 5, n.º 1 (6 de junio de 2013): 15–22. http://dx.doi.org/10.20894/ijmsr.117.005.001.003.
Texto completoSagar, Sagar. "Design of Low Power Vedic Multiplier Based on Reversible Logic". International Journal of Engineering Research and Applications 07, n.º 03 (marzo de 2017): 73–78. http://dx.doi.org/10.9790/9622-0703027378.
Texto completoNayeem. "Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography". Journal of Computer Science 5, n.º 1 (1 de enero de 2009): 49–56. http://dx.doi.org/10.3844/jcs.2009.49.56.
Texto completoAnanthaLakshmi, A. V. y G. F. Sudha. "Design of an Efficient Reversible Single Precision Floating Point Multiplier". Journal of Bioinformatics and Intelligent Control 4, n.º 1 (1 de marzo de 2015): 21–30. http://dx.doi.org/10.1166/jbic.2015.1109.
Texto completoNayeem. "Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography". Journal of Computer Science 5, n.º 1 (1 de enero de 2009): 49–56. http://dx.doi.org/10.3844/jcssp.2009.49.56.
Texto completoPandey, Neeta, Nalin Dadhich y Mohd Zubair Talha. "An Optimized and Cost Efficient Realization of Reversible Braun Multiplier". i-manager's Journal on Circuits and Systems 3, n.º 3 (15 de agosto de 2015): 17–24. http://dx.doi.org/10.26634/jcir.3.3.4781.
Texto completoBanerjee, Arindam y Debesh Kumar Das. "The Design of Reversible Signed Multiplier Using Ancient Indian Mathematics". Journal of Low Power Electronics 11, n.º 4 (1 de diciembre de 2015): 467–78. http://dx.doi.org/10.1166/jolpe.2015.1413.
Texto completoHridya, S., Dr S. Bhavani, Dr K. G. Dharani y M. Darani Kumar. "A Multiplier Design based on Ancient Indian Vedic Mathematics Using Reversible Logic: A Review". Journal of Advanced Research in Dynamical and Control Systems 11, n.º 10-SPECIAL ISSUE (31 de octubre de 2019): 911–24. http://dx.doi.org/10.5373/jardcs/v11sp10/20192887.
Texto completoAnitha, R., R. Thenmozhi, M. Madhunila y Sarat Kumar Sahoo. "A Comparitive Study of Vedic BCD Multiplier using Reversible Logic Gates". Research Journal of Applied Sciences, Engineering and Technology 11, n.º 12 (25 de diciembre de 2015): 1298–304. http://dx.doi.org/10.19026/rjaset.11.2238.
Texto completoMukku, Venkateswarlu y Jaddu MallikharjunaReddy. "An Area Efficient and High Speed Reversible Multiplier Using NS Gate". International Journal of Engineering Research and Applications 7, n.º 01 (enero de 2017): 29–33. http://dx.doi.org/10.9790/9622-0701042933.
Texto completoPChavan, Arunkumar, Prakash Pawar y Varun R. "Design of Pulse Detectors and Unsigned Sequential Multiplier using Reversible Logic". International Journal of Computer Applications 92, n.º 4 (18 de abril de 2014): 11–17. http://dx.doi.org/10.5120/15996-4891.
Texto completoNandal, Amita, T. Vigneswaran y Ashwani Rana. "Optimized Reversible Logic Based Add and Shift Multiplier Using Linear Transformation". Advanced Science, Engineering and Medicine 5, n.º 5 (1 de mayo de 2013): 431–35. http://dx.doi.org/10.1166/asem.2013.1282.
Texto completoPankaj, N. Rajeev, P. Venugopal y Prasanthi Mortha. "Design of quantum cost efficient reversible multiplier using Reed-Muller expressions". International Journal of Computing Science and Mathematics 7, n.º 3 (2016): 221. http://dx.doi.org/10.1504/ijcsm.2016.077861.
Texto completoKamaraj, A. y P. Marichamy. "Design of fault-tolerant reversible Vedic multiplier in quantum cellular automata". Journal of the National Science Foundation of Sri Lanka 47, n.º 4 (17 de diciembre de 2019): 371. http://dx.doi.org/10.4038/jnsfsr.v47i4.9677.
Texto completoKumar, Ravi. "Implementation of the Binary Multiplier on CPLD Using Reversible Logic Gates". IOSR Journal of Electronics and Communication Engineering 12, n.º 01 (marzo de 2017): 40–42. http://dx.doi.org/10.9790/2834-1201034042.
Texto completoGowthami, Nekkanti y K. Srilakshmi. "Design and Implementation of Reversible Multiplier using optimum TG Full Adder". IOSR Journal of Electronics and Communication Engineering 12, n.º 03 (julio de 2017): 81–89. http://dx.doi.org/10.9790/2834-1203048189.
Texto completoAhmad, Nabihah, Ahmad Hakimi Mokhtar, Nurmiza binti Othman, Chin Fhong Soon y Ab Al Hadi Ab Rahman. "VLSI Implementation of Fault Tolerance Multiplier based on Reversible Logic Gate". IOP Conference Series: Materials Science and Engineering 226 (agosto de 2017): 012140. http://dx.doi.org/10.1088/1757-899x/226/1/012140.
Texto completoShukla, Vandana, O. P. Singh, G. R. Mishra y R. K. Tiwari. "Reversible Realization of 4-Bit Vedic Multiplier Circuit with Optimized Performance Parameters". Sensor Letters 17, n.º 10 (1 de octubre de 2019): 826–31. http://dx.doi.org/10.1166/sl.2019.4155.
Texto completoD.V.R, Mohan, Vidyamadhuri K, RamaLakshmanna Y y K. H. S. Suresh kumar. "Design of Low Power Multiplier using Reversible logic: A Vedic Mathematical Approach". IJARCCE 6, n.º 3 (30 de marzo de 2017): 96–102. http://dx.doi.org/10.17148/ijarcce.2017.6321.
Texto completoS M, Mayur. "Design of a Low Power Vedic Multiplier using BKG Reversible Logic Gate". International Journal for Research in Applied Science and Engineering Technology 6, n.º 6 (30 de junio de 2018): 1586–90. http://dx.doi.org/10.22214/ijraset.2018.6232.
Texto completoYogeswari, K. "Design and Performance Comparison of 16-Bit UT Multiplier using Reversible Logic". International Journal for Research in Applied Science and Engineering Technology 7, n.º 4 (30 de abril de 2019): 903–11. http://dx.doi.org/10.22214/ijraset.2019.4161.
Texto completoK N, Hemalatha y Sangeetha B G. "Efficient Design of Compact 8-bit Wallace Tree Multiplier Using Reversible Logic". International Journal of Engineering and Manufacturing 12, n.º 4 (8 de agosto de 2022): 29–36. http://dx.doi.org/10.5815/ijem.2022.04.03.
Texto completoAkbar, Ehsan Pour Ali, Majid Haghparast y Keivan Navi. "Novel design of a fast reversible Wallace sign multiplier circuit in nanotechnology". Microelectronics Journal 42, n.º 8 (agosto de 2011): 973–81. http://dx.doi.org/10.1016/j.mejo.2011.05.007.
Texto completoNandal, Amita. "Booth Multiplier using Reversible Logic with Low Power and Reduced Logical Complexity". Indian Journal of Science and Technology 7, n.º 4 (20 de abril de 2014): 525–29. http://dx.doi.org/10.17485/ijst/2014/v7i4.15.
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