Literatura académica sobre el tema "Resistive memories (RRAMs)"

Abstract In this study, sol–gel-processed amorphous-phase ZrO2 was used as an active channel material to improve the resistive switching properties of resistive random access memories (RRAMs). ITO/ZrO2/Ag RRAM devices exhibit the properties of bipolar RRAMs. The effect of the post-annealing temperature on the electrical properties of the ZrO2 RRAM was investigated. Unlike the ZrO2 films annealed at 400 and 500 °C, those annealed at 300 °C were in amorphous phase. The RRAM based on the amorphous-phase ZrO2 exhibited an improved high-resistance state (HRS) to low-resistance state ratio (over 106) as well as promising retention and endurance characteristics without deterioration. Furthermore, its disordered nature, which causes efficient carrier scattering, resulted in low carrier mobility and the lowest leakage current, influencing the HRS values.

: In this work, the resistive switching characteristics of resistive random access memories (RRAMs) containing Sm2O3 and V2O5 films were investigated. All the RRAM structures made in this work showed stable resistive switching behavior. The High-Resistance State and Low-Resistance State of Resistive memory (RHRS/RLRS) ratio of the RRAM device containing a V2O5/Sm2O3 bilayer is one order of magnitude higher than that of the devices containing a single layer of V2O5 or Sm2O3. We also found that the stacking sequence of the Sm2O3 and V2O5 films in the bilayer structure can affect the switching features of the RRAM, causing them to exhibit both bipolar resistive switching (BRS) behavior and self-compliance behavior. The current conduction mechanisms of RRAM devices with different film structures were also discussed.

A methodology to estimate the device temperature in resistive random access memories (RRAMs) is presented. Unipolar devices, which are known to be highly influenced by thermal effects in their resistive switching operation, are employed to develop the technique. A 3D RRAM simulator is used to fit experimental data and obtain the maximum and average temperatures of the conductive filaments (CFs) that are responsible for the switching behavior. It is found that the experimental CFs temperature corresponds to the maximum simulated temperatures obtained at the narrowest sections of the CFs. These temperature values can be used to improve compact models for circuit simulation purposes.

The ubiquitous use of critical and private data in electronic format requires reliable and secure embedded systems for IoT devices. In this context, RRAMs (Resistive Random Access Memories) arises as a promising alternative to replace current memory technologies. However, their suitability for this kind of application, where the integrity of the data is crucial, is still under study. Among the different typology of attacks to recover information of secret data, laser attack is one of the most common due to its simplicity. Some preliminary works have already addressed the influence of laser tests on RRAM devices. Nevertheless, the results are not conclusive since different responses have been reported depending on the circuit under testing and the features of the test. In this paper, we have conducted laser tests on individual RRAM devices. For the set of experiments conducted, the devices did not show faulty behaviors. These results contribute to the characterization of RRAMs and, together with the rest of related works, are expected to pave the way for the development of suitable countermeasures against external attacks.

Abstract Resistance switching (RS) in 2D molybdenum disulfide (MoS2) was recently discovered. Since the discovery, many reports demonstrating MoS2 resistive random-access memory (RRAM) with synapse-like behavior have been published. These reports strongly justify applications of MoS2 RRAM in neuromorphic hardware as well as an alternative to conventional binary memories. In this work, we unveil the effect of RS, induced by current–voltage hysteresis cycles across CVD-grown monolayer MoS2-based gated RRAM, on its transistor’s electrical and reliability characteristics. A unique gate voltage dependence on the RS is identified which has a remarkable impact on the switching performance of MoS2 RRAM. RS behavior was found to be significantly dependent on the charge conduction in the channel. Moreover, we have shown a potential device-forming event when MoS2-gated RRAMs were subjected to a steady-state electrical stress. Both hysteresis and steady-state electrical stress were found to disturb the transistor action of these gated RRAMs, which can in fact be used as a signature of RS. Interestingly, current–voltage hysteresis resulted in unipolar RS, whereas steady-state electrical stress before RS measurement led to bipolar RS. Moreover, successive stress cycles of such electrical stress lead to multiple resistance states, a behavior similar to synaptic properties such as long-term potentiation and long-term depression, typically found in memristors. We find that the charge transport mechanism dominant in the MoS2 FET, in conjunction with steady-state stress-induced device forming, determine the extent of RS induced in thes MoS2-based gated RRAMs. Finally, on the basis of insights developed from the dependence on the charge transport mechanism and steady-state stress-induced forming of the MoS2 channel, we propose a certain steady-state electrical stress condition which can be used as a ‘forming’ process, employed prior to the use of MoS2-based binary RRAMs for improved switching performance.

Resistive random access memories (RRAMs) are a type of resistive memory with two metal electrodes and a semi-insulating switching material in-between. As the persistent technology node downscaling continues in transistor technologies, RRAM designers also face similar device scaling challenges in simple cross-point arrays. For this reason, a cost-effective 3D vertical RRAM (VRRAM) structure which requires a single pivotal lithography step is attracting significant attention from both the scientific community and the industry. Integrating an extremely thin plane electrode to such a structure is a difficult but necessary step to enable high memory density. In addition, experimentally verifying and modeling such devices is an important step to designing RRAM arrays with a high noise margin, low resistive-capacitive (RC) delays, and stable switching characteristics. In this work, we conducted an electromagnetic analysis on a 3D vertical RRAM with atomically thin graphene electrodes and compared it with the conventional metal electrode. Based on the experimental device measurement results, we derived a theoretical basis and models for each VRRAM design that can be further utilized in the estimation of graphene-based 3D memory at the circuit and architecture levels. We concluded that a 71% increase in electromagnetic field strength was observed in a 0.3 nm thick graphene electrode when compared to a 5 nm thick metal electrode. Such an increase in the field led to much lower energy consumption and fluctuation range during RRAM switching. Due to unique graphene properties resulting in improved programming behavior, the graphene-based VRRAM can be a strong candidate for stacked storage devices in new memory computing platforms.

State-of-the-art IoT technologies request novel design solutions in edge computing, resulting in even more portable and energy-efficient hardware for in-the-field processing tasks. Vision sensors, processors, and hardware accelerators are among the most demanding IoT applications. Resistance switching (RS) two-terminal devices are suitable for resistive RAMs (RRAM), a promising technology to realize storage class memories. Furthermore, due to their memristive nature, RRAMs are appropriate candidates for in-memory computing architectures. Recently, we demonstrated a CMOS compatible silicon nitride (SiNx) MIS RS device with memristive properties. In this paper, a report on a new photodiode-based vision sensor architecture with in-memory computing capability, relying on memristive device, is disclosed. In this context, the resistance switching dynamics of our memristive device were measured and a data-fitted behavioral model was extracted. SPICE simulations were made highlighting the in-memory computing capabilities of the proposed photodiode-one memristor pixel vision sensor. Finally, an integration and manufacturing perspective was discussed.

In the past decade, halide perovskites (HPs) have shot to fame in the genre of optoelectronics and photovoltaics owing to their large absorption co-effcient, high color purity, tunable bandgap and long charge diffusion lengths. Besides these traits, HPs also possess innumerable charge transport pathways, inherent hysteresis, high charge-carrier and ionic mobilities which render them as ideal candidates for resistive random access switching memories (RRAMs). However owing to material and electrical instability associated with HP thin-film devices, the figures-of-merits (FOMs) namely retention, endurance and switching speed were not up to the state of-the-art standard until recently. In order to revolutionize HP Re-RAMs we devised a unique device structure where we replaced the thin-film architecture with vertically aligned high density HP nanowires and quantum wires embedded in a porous alumina membrane (PAM) sandwiched between metallic silver and aluminum contacts. The excellent passivation provided by the PAM imparted the requisite electrical and material stability to the environmentally delicate HPs by drastically reducing the surface diffusion pathways and thereby thwarting the moisture induced attacks. Extrapolated retention time as high as 28.3 years and measured device endurance of a million cycles were obtained. Utilizing the single crystalline HP nanowires and quantum wires and their associated high ionic and electronic mobilities, switching speed as fast as 100 ps was also obtained. These FOMs represent record values for HP RRAMs ever reported. Furthermore a 14 nm lateral size HP quantum wire RRAM cell was fabricated and a cross-bar device architecture with a unique sneaky path mitigation scheme were developed, which successfully exhibited the scalability potential of our devices. We further coupled the optoelectronic and switching behaviors and were able to obtain optical programmability among the low resistance states. Besides data storage, the HP nanowires and quantum wires were employed in developing neuromorphic devices enabled with low power and high precision computing capabilities. Specifically, we obtained robust multi-level states in two types of brain-inspired devices capable of performing analog processing tasks by using silver as the top electrode and precisely controlling the current injection in the monocrytalline switching medium and by using indium doped tin oxide as the top electrode and inducing a novel valence change mechanism in the HP nanowires triggering the gradual conductance change. All in all, our nanowire and quantum wire devices propel HP RRAMs to the state-of-the-art standard in multifarious applications concerning future data storage and neuromorphic computing.

Abstract Low-power memristive devices embedded on graphics or central processing units logic core are a very promising non-von-Neumann approach to improve significantly the speed and power consumption of deep learning accelerators, enhancing their deployment on embedded systems. Among various non-ideal emerging neuromorphic memory devices, synaptic weight hardware implementation using resistive random-access memories (RRAMs) within 1T1R architectures promises high performance on low precision binarized neural networks (BNN). Taking advantage of the RRAM capabilities and allowing to substantially improve the density thanks to the ovonic threshold selector (OTS) selector, this work proposes to replace the standard 1T1R architecture with a denser 1S1R crossbar system, where an HfO2-based resistive oxide memory (OxRAM) is co-integrated with a Ge-Se-Sb-N-based OTS. In this context, an extensive experimental study is performed to optimize the 1S1R stack and programming conditions for extended read window margin and endurance characteristics. Focusing on the standard machine learning MNIST image recognition task, we perform offline training simulations in order to define the constraints on the devices during the training process. A very promising bit error rate of ∼10−3 is demonstrated together with 1S1R 104 error-free programming endurance characteristics, fulfilling the requirements for the application of interest. Based on this simulation and experimental study, BNN figures of merit (system footprint, number of weight updates, accuracy, inference speed, electrical consumption per image classification and tolerance to errors) are optimized by engineering the number of learnable parameters of the system. Altogether, an inherent BNN resilience to 1S1R parasitic bit errors is demonstrated.

De nombreuses applications (internet des objets, systèmes embarqués automobiles et médicales, intelligence artificielle) ont besoin d’un circuit intégré (ou SoC pour System on Chip) avec des mémoires non volatiles embarquées performantes pour fonctionner de manière optimale. Bien que la mémoire Flash soit largement utilisée aujourd'hui, cette technologie nécessite une tension élevée pour les opérations de programmation et présente des problèmes de fiabilité difficiles à gérer au-delà du nœud technologique 18 nm, augmentant les coûts de conception et de fabrication des circuits. Dans ce contexte, l'industrie du semi-conducteur est à la recherche d’une mémoire non volatile alternative pouvant remplacer les mémoires Flash. Parmi les candidats actuellement étudiés (MRAM - mémoire à accès aléatoire magnétique, PCM - mémoire à changement de phase, FeRAM - mémoire à accès aléatoire Ferroélectrique), les mémoires résistives (RRAM) offrent de meilleures performances sur différents points capitaux : compatibilité avec le processus de fabrication standard CMOS, consommation de courant, rapidité de fonctionnement, etc. La technologie RRAM peut être aisément introduite dans n'importe quel flot de conception ouvrant la voie au développement de nouvelles architectures qui répondent à l’engorgement des systèmes classiques Von Neumann. Dans cette thèse, l'objet principal est de montrer le potentiel d’intégration des dispositifs RRAM avec la technologie CMOS, à l’aide de simulation et de mesures électriques, afin d’élaborer différentes structures hybrides : mémoires à accès aléatoire statique (SRAM) non volatiles, générateurs de nombres aléatoires (TRNG) et réseaux de neurones artificiels
Many diversified applications (internet of things, embedded systems for automotive and medical applications, artificial intelligence) require an integrated circuit (SoC, System on Chip) with high-performance non-volatile memories to operate optimally. Although Flash memory is widely used today, this technology needs high voltage for programing operations and has reliability issues that are hard to handle beyond 18 nm technological node, increasing the cost of circuit design and fabrication. In this context, the semiconductor industry seeks an alternative non-volatile memory that can replace Flash memories. Among possible candidates (MRAM - Magnetic Random Access Memory, PCM - Phase Change Memory, FeRAM - Ferroelectric Random Access Memory), Resistive memories (RRAMs) offer superior performances on essential key points: compatibility with CMOS manufacturing processes, scalability, current consumption (standby and active), operational speed. Due to its relatively simple structure, RRAM technology can be easily integrated in any design flow opening the way for the development of new architectures that answer Von Neumann bottleneck. In this thesis, the main object is to show the integration abilities of RRAM devices with CMOS technology, using circuit design and electrical measurements, in order to develop different hybrid structures: non-volatile Static Random Access Memories (SRAM), True Random Number Generator (TRNG) and artificial neural networks

L’enorme mole di dati prodotta dai dispositivi per l’Internet of Things richiede una trasformazione dell’attuale infrastruttura di cloud computing: lo spostamento di parte dell’elaborazione dove i dati vengono generati (edge computing). Per attuare questo cambio di paradigma, lo sviluppo di nuove soluzioni hardware per l’elaborazione dei dati più efficienti è fondamentale. Inoltre, il sopraggiungere del limite fisico di miniaturizzazione dei transistor implica la necessità di sviluppare nuovi nanodispositivi e nuove architetture di calcolo, che si scostano dalla tradizionale architettura di von Neumann. Inoltre, i sempre più stringenti requisiti di sicurezza richiedono l’introduzione di primitive di sicurezza direttamente a livello hardware. Le tecnologie emergenti nell’ambito delle memorie non volatili (eNVM) permettono l’implementazione di paradigmi di elaborazione in memoria, che eliminano il principale collo di bottiglia delle architetture di von Neumann, ovvero l’inefficiente scambio di dati tra la memoria e l’unità di elaborazione. Tuttavia, la natura stocastica dei dispositivi di eNVM influisce sulla funzionalità e sull'affidabilità di questi circuiti, complicandone la progettazione. D'altra parte, questi fenomeni stocastici possono essere sfruttati per implementare primitive di sicurezza a livello hardware. Pertanto, per sfruttare le potenzialità delle eNVM sono fondamentali nuovi strumenti e nuove metodologie di progettazione. L’obiettivo di questa tesi di dottorato è l'ottimizzazione di strumenti per la simulazione circuitale e lo sviluppo di metodologie appropriate per l’analisi ed il miglioramento di circuiti innovativi basati sulle eNVM per applicazioni di elaborazione e sicurezza. In particolare, viene proposto un modello compatto di RAM resistiva (RRAM) (modello compatto UniMORE), sviluppato a partire da una versione prototipale esistente e perfezionato per includere in modo autoconsistente il ruolo della variabilità, degli effetti termici e del Random Telegraph Noise (RTN). Inoltre, viene descritta una procedura di estrazione dei parametri semi-automatica che richiede solo i risultati di alcuni esperimenti comunemente impiegati durante la caratterizzazione dei dispositivi, e che è stata validata sia sperimentalmente che su tre tecnologie RRAM dalla letteratura. Grazie al modello compatto calibrato, vengono analizzate le prestazioni e l’affidabilità circuitale di diversi paradigmi di elaborazione in memoria. Mediante simulazioni circuitali di circuiti Logic-in-Memory (LiM) basati sulla logica di implicazione materiale (IMPLY) e sulla tecnologia RRAM, sono state sviluppate procedure di progettazione volte a massimizzarne l’affidabilità circuitale. Inoltre, è stata sviluppata una nuova architettura LiM chiamata smart IMPLY (SIMPLY), che risolve i problemi di affidabilità comunemente presenti nei circuiti convenzionali. L'affidabilità e le prestazioni dell'architettura SIMPLY sono state studiate dettagliatamente considerando diverse tecnologie RRAM e l’esecuzione di operazioni complesse. Inoltre, tramite simulazioni circuitali sono stati analizzati acceleratori hardware di reti neurali a bassa precisione, evidenziandone i compressi esistenti tra affidabilità ed elevate prestazioni. Viene anche presentato un nuovo acceleratore hardware che combina sullo stesso array di memoria due diversi paradigmi di elaborazione in memoria, ovvero SIMPLY e l’accelerazione in analogico del prodotto matrice vettore. Infine, vengono discusse le sfide e le opportunità per i circuiti True Random Number Generators basati su RTN, mediante i risultati di simulazioni circuitali che sfruttano segnali RTN misurati sperimentalmente da diverse tecnologie RRAM.
The number of smart devices for the Internet of Things (IoT) is rapidly growing, and by 2025 almost 80 ZB of data per year will be generated by IoT devices alone, challenging the current cloud computing infrastructure. Thus, a shift to the edge computing paradigm, in which data are processed near their sources, is critical, but its implementation requires new energy efficient computing hardware. The approaching downscaling limit of transistor size implies the need for new nanoscale technologies and a departure from the conventional von Neumann architecture. Also, in-hardware security primitives need to be introduced at the silicon level. Among the possible technologies, emerging non-volatile memories (eNVMs) are very promising and enable the realization of in-memory computing paradigms, in which computation is executed directly inside the memory, therefore bypassing the slow and energy inefficient data exchange over a communication bus, i.e., the main bottleneck of von Neumann architectures. However, the intrinsic stochastic nature of eNVMs presents several challenges which can impact the circuit functionality and reliability. On the other hand, it can be exploited to implement hardware-level security primitives such as True Random Number Generators (TRNGs) and Physical Unclonable Functions (PUF). Thus, appropriate design tools and methodologies are needed to help circuit designers exploit eNVMs strengths while consciously addressing their limitations. The optimization of circuit simulation tools and the development of appropriate methodologies to analyze and improve innovative circuits based on eNVMs for computing and security applications is the goal of this Ph.D. thesis. Specifically, a physics-based Resistive RAM (RRAM) compact model (UniMORE compact model), was developed starting from a prototypical existing version and refined to include self-consistently the role of variability, thermal effects, and Random Telegraph Noise (RTN). In addition, a self-automated parameter extraction procedure is developed and included. Such procedure requires only the results of a few experiments that are commonly employed in the device characterization, and was validated both experimentally and on three RRAM technologies from the literature. The procedure allows quick model calibration and helps in determining the strengths and weaknesses of different RRAM technologies for a dependable device-circuit co-optimization. The calibrated compact model is used to analyze the performance and reliability trade-offs of different in-memory computing paradigms. Specifically, the results of circuits simulations of state-of-the-art Logic-in-Memory (LiM) circuits based on the material implication (IMPLY) logic and RRAM technology enabled the development of design procedures for optimizing their reliability, which are here discussed. Also, a novel smart IMPLY (SIMPLY) LiM architecture, which solves the circuit reliability issues of conventional IMPLY architectures, was developed. The reliability and performances of the SIMPLY architecture were thoroughly investigated considering different RRAM technologies and benchmarked on complex operations. Furthermore, the results of the study on RRAM-based low-bit precision neural networks (NNs) analog hardware accelerators are presented, highlighting specific reliability and performance trade-offs. Also, a novel hybrid in-memory computing hardware accelerator in which both SIMPLY and the analog vector matrix multiplication framework coexist on the same memory crossbar array is demonstrated. Finally, challenges and opportunities for RTN-based TRNG circuits are discussed, by exploiting the results of circuit simulations in which experimentally measured RTN data from different RRAM technologies are used.

Alors que les mémoires non-volatiles conventionnelles, telles que les mémoires flash à grille flottante, deviennent de plus en plus complexes à intégrer et souffrent de performances et d’une fiabilité de plus en plus réduite, les mémoires à variation de résistance (RRAM) telles que les OxRAM, CBRAM, MRAM ou PCM sont vues dans la communauté scientifique comme une alternative crédible. Cependant, les architectures de RRAM standard (telles que la 1Transistor-1RRAM) ne sont pas compétitives avec les mémoires flash sur le terrain de la densité. Ainsi, cette thèse se propose d’explorer le potentiel des architectures RRAM sans transistor que sont l’architecture Crosspoint et l’architecture VRRAM.Dans un premier temps, le positionnement des architectures Crosspoint et VRRAM dans la hiérarchie mémoire est étudié. De nouvelles problématiques, telles que les courant de sneakpath, la chute de tension dans les métaux ou la surface des circuits périphériques sont identifiées et modélisées. Dans un second temps, des solutions circuit répondant aux problématiques évoquées précédemment sont proposées. Finalement, cette thèse se propose d’explorer les opportunités ouvertes par l’utilisation de transistors innovants pour améliorer la densité ou les performances des architectures mémoires utilisant des RRAM
While conventional non-volatiles memories, such as floating gate Flash memories, are becoming more and more difficult and costly to integrate and suffer of reduced performances and reliability, emerging resistive switching memories (RRAM), such as OxRAM, CBRAM, MRAM or PCM, are seen in the scientific community as a good way for tomorrow’s high-density memories. However, standard RRAM architectures (such as 1 Transistor-1 RRAM) are not competitive with flash technology in terms of density. Thereby, this thesis proposes to explore the opportunities opened by transistor-less RRAM architectures: Crosspoint and Vertical RRAM (VRRAM) architectures.First, the positioning of Crosspoint and VRRAM architectures in the memory hierarchy is studied. New constraints such as the sneakpath currents, the voltage drop through the metal lines or the periphery area overhead are identified and modeled. In a second time, circuit solutions answering to previously mentioned effects are proposed. Finally, this thesis proposes to explore new opportunities opened by the use of innovative transistors to improve the density or the performances of RRAM-based memory architectures

Alors que les mémoires non-volatiles conventionnelles, telles que les mémoires flash à grille flottante, deviennent de plus en plus complexes à intégrer et souffrent de performances et d’une fiabilité de plus en plus réduite, les mémoires à variation de résistance (RRAM) telles que les OxRAM, CBRAM, MRAM ou PCM sont vues dans la communauté scientifique comme une alternative crédible. Cependant, les architectures de RRAM standard (telles que la 1Transistor-1RRAM) ne sont pas compétitives avec les mémoires flash sur le terrain de la densité. Ainsi, cette thèse se propose d’explorer le potentiel des architectures RRAM sans transistor que sont l’architecture Crosspoint et l’architecture VRRAM.Dans un premier temps, le positionnement des architectures Crosspoint et VRRAM dans la hiérarchie mémoire est étudié. De nouvelles problématiques, telles que les courant de sneakpath, la chute de tension dans les métaux ou la surface des circuits périphériques sont identifiées et modélisées. Dans un second temps, des solutions circuit répondant aux problématiques évoquées précédemment sont proposées. Finalement, cette thèse se propose d’explorer les opportunités ouvertes par l’utilisation de transistors innovants pour améliorer la densité ou les performances des architectures mémoires utilisant des RRAM
While conventional non-volatiles memories, such as floating gate Flash memories, are becoming more and more difficult and costly to integrate and suffer of reduced performances and reliability, emerging resistive switching memories (RRAM), such as OxRAM, CBRAM, MRAM or PCM, are seen in the scientific community as a good way for tomorrow’s high-density memories. However, standard RRAM architectures (such as 1 Transistor-1 RRAM) are not competitive with flash technology in terms of density. Thereby, this thesis proposes to explore the opportunities opened by transistor-less RRAM architectures: Crosspoint and Vertical RRAM (VRRAM) architectures.First, the positioning of Crosspoint and VRRAM architectures in the memory hierarchy is studied. New constraints such as the sneakpath currents, the voltage drop through the metal lines or the periphery area overhead are identified and modeled. In a second time, circuit solutions answering to previously mentioned effects are proposed. Finally, this thesis proposes to explore new opportunities opened by the use of innovative transistors to improve the density or the performances of RRAM-based memory architectures

abstract: Chalcogenide glass (ChG) materials have gained wide attention because of their applications in conductive bridge random access memory (CBRAM), phase change memories (PC-RAM), optical rewritable disks (CD-RW and DVD-RW), microelectromechanical systems (MEMS), microfluidics, and optical communications. One of the significant properties of ChG materials is the change in the resistivity of the material when a metal such as Ag or Cu is added to it by diffusion. This study demonstrates the potential radiation-sensing capabilities of two metal/chalcogenide glass device configurations. Lateral and vertical device configurations sense the radiation-induced migration of Ag+ ions in germanium selenide glasses via changes in electrical resistance between electrodes on the ChG. Before irradiation, these devices exhibit a high-resistance `OFF-state' (in the order of 10E12) but following irradiation, with either 60-Co gamma-rays or UV light, their resistance drops to a low-resistance `ON-state' (around 10E3). Lateral devices have exhibited cyclical recovery with room temperature annealing of the Ag doped ChG, which suggests potential uses in reusable radiation sensor applications. The feasibility of producing inexpensive flexible radiation sensors has been demonstrated by studying the effects of mechanical strain and temperature stress on sensors formed on flexible polymer substrate. The mechanisms of radiation-induced Ag/Ag+ transport and reactions in ChG have been modeled using a finite element device simulator, ATLAS. The essential reactions captured by the simulator are radiation-induced carrier generation, combined with reduction/oxidation for Ag species in the chalcogenide film. Metal-doped ChGs are solid electrolytes that have both ionic and electronic conductivity. The ChG based Programmable Metallization Cell (PMC) is a technology platform that offers electric field dependent resistance switching mechanisms by formation and dissolution of nano sized conductive filaments in a ChG solid electrolyte between oxidizable and inert electrodes. This study identifies silver anode agglomeration in PMC devices following large radiation dose exposure and considers device failure mechanisms via electrical and material characterization. The results demonstrate that by changing device structural parameters, silver agglomeration in PMC devices can be suppressed and reliable resistance switching may be maintained for extremely high doses ranging from 4 Mrad(GeSe) to more than 10 Mrad (ChG).
Dissertation/Thesis
Ph.D. Electrical Engineering 2013

AbstractMemristor-based hardware accelerators play a crucial role in achieving energy-efficient big data processing and artificial intelligence, overcoming the limitations of traditional von Neumann architectures. Resistive-switching memories (RRAMs) combine a simple two-terminal structure with the possibility of tuning the device conductance. This Chapter revolves around the topic of emerging memristor-related technologies, starting from their fabrication, through the characterization of single devices up to the development of proof-of-concept experiments in the field of in-memory computing, hardware accelerators, and brain-inspired architecture. Non-volatile devices are optimized for large-size crossbars where the devices’ conductance encodes mathematical coefficients of matrices. By exploiting Kirchhoff’s and Ohm’s law the matrix–vector-multiplication between the conductance matrix and a voltage vector is computed in one step. Eigenvalues/eigenvectors are experimentally calculated according to the power-iteration algorithm, with a fast convergence within about 10 iterations to the correct solution and Principal Component Analysis of the Wine and Iris datasets, showing up to 98% accuracy comparable to a floating-point implementation. Volatile memories instead present a spontaneous change of device conductance with a unique similarity to biological neuron behavior. This characteristic is exploited to demonstrate a simple fully-memristive architecture of five volatile RRAMs able to learn, store, and distinguish up to 10 different items with a memory capability of a few seconds. The architecture is thus tested in terms of robustness under many experimental conditions and it is compared with the real brain, disclosing interesting mechanisms which resemble the biological brain.

The constant scaling of the conventional field-effect transistors (FETs) over the last half century has permitted the development of memory elements with enhanced density. However, since continuous miniaturization is practically impossible, novel device architectures have been proposed. Among them, resistive switching memories (RRAMs) emerge as quite promising candidates due to their simple structure, which permits aggressive scaling, and inherent stochastic performance, which is leveraged for the implementation of neuromorphic functionalities. Along these lines, a detailed analysis from a material point of view is presented, as far as the fabrication of SiO2-based resistive switching elements is concerned. The incorporation of metal nanoparticles (NPs) with various surface densities, as well as the employment of bilayer configurations, is thoroughly investigated in enhancing the total memory performance. More specifically, low-power operation (∼ 200 mV), enhanced variability (σ/μ < 0.2) and multibit capabilities (4 bits) were demonstrated. Moreover, the manifestation of two switching modes (bipolar and threshold) was leveraged to emulate artificial neuron and synaptic functionalities. As a result, integrate and fire (IF) properties were produced from single memristive cells, whereas enhanced analog synaptic weight modulation was also recorded. Physics-driven device engineering is thus of great importance for attaining reconfigurable memory and neuromorphic properties.