Tesis sobre el tema "Reconfiguration Time"
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Thompson, Dean (Dean Barrie) 1974. "Dynamic reconfiguration under real-time constraints". Monash University, School of Computer Science and Software Engineering, 2002. http://arrow.monash.edu.au/hdl/1959.1/7991.
Texto completoParrott, Curtis Alan. "Real-time reconfiguration of programmable logic controller communication paths". Diss., Rolla, Mo. : Missouri University of Science and Technology, 2009. http://scholarsmine.mst.edu/thesis/pdf/Parrott_09007dcc806c2c91.pdf.
Texto completoVita. The entire thesis text is included in file. Title from title screen of thesis/dissertation PDF file (viewed November 17, 2009) Includes bibliographical references (p. 53).
Bowen, John Kipp. "Dynamic Module Library Generation for FPGA-based Run-Time Reconfigurable Systems". Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/31088.
Texto completoMaster of Science
Hansen, Sindre. "Self Reconfiguration of Clock Networks on FPGA : Methodology for partial reconfiguration of synchronous modules at run-time". Thesis, Norges teknisk-naturvitenskapelige universitet, Institutt for elektronikk og telekommunikasjon, 2011. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-13641.
Texto completoGuo, Guanghao. "Evaluation of FPGA Partial Reconfiguration : for real-time Vision applications". Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-279957.
Texto completoAnvändningen av programmerbara logiska resurser i Field Programmable Gate Arrayer, även känd som FPGA:er, har ökat mycket nyligen på grund av komplexiteten hos algoritmerna, speciellt för vissa datorvisningsalgoritmer. På grund av detta är det ibland inte tillräckligt med hårdvaruresurser i FPGA:n. Partiell omkonfiguration ger oss möjlighet att lösa detta problem. Partiell omkonfigurering är en teknik som kan användas för att omkonfigurera specifika delar av FPGA:n under körtid. Genom att använda denna teknik kan vi minska behovet av programmerbara logiska resurser. Det här mastersprojektet syftar till att utforma ett programvaru-ramverk för partiell omkonfiguration som kan ladda en uppsättning processkomponenter / algoritmer (t.ex. objektdetektering, optiskt flöde, Harris-Corner detection etc) i FPGA- området utan att påverka statiska realtids-komponenter såsom kamerafångst, grundläggande bildfiltrering och färgkonvertering som körs kontinuerligt. Partiell omkonfiguration har tillämpats på två olika videoprocessnings-pipelines, en direkt-strömmande respektive en rambuffert-strömmande arkitektur. Resultatet visar att omkonfigurationstiden är förutsägbar och att partiell omkonfiguration kan användas i realtids-tillämpningar.
Khan, Asif H. "Analysis of time varying load for minimum loss distribution reconfiguration". Diss., This resource online, 1992. http://scholar.lib.vt.edu/theses/available/etd-06062008-171313/.
Texto completoHeron, Jean-Paul Stephen. "Design and implementation of reconfigurable DSP circuit architectures on FPGA". Thesis, Queen's University Belfast, 1998. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.266712.
Texto completoPuett, Ronnie Douglas. "Reconfiguration in robust distributed real-time systems based on global checkpoints". Thesis, Monterey, California. Naval Postgraduate School, 1991. http://hdl.handle.net/10945/26720.
Texto completoMahmood, Waqar. "Intelligent modeling for control, reconfiguration and optimization of discrete event systems". Diss., Georgia Institute of Technology, 1997. http://hdl.handle.net/1853/15014.
Texto completoBallagh, Jonathan Bartlett. "An FPGA-based Run-time Reconfigurable 2-D Discrete Wavelet Transform Core". Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/33649.
Texto completoMaster of Science
Courtney, T. E. G. "Exploring run-time reconfiguration on programmable logic for DSP and telecommunications applications". Thesis, Queen's University Belfast, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.273222.
Texto completoCelik, Guner Dincer. "Scheduling algorithms for throughput maximization in time-varying networks with reconfiguration delays". Thesis, Massachusetts Institute of Technology, 2012. http://hdl.handle.net/1721.1/78442.
Texto completoCataloged from PDF version of thesis.
Includes bibliographical references (p. 247-258).
We consider the control of possibly time-varying wireless networks under reconfiguration delays. Reconfiguration delay is the time it takes to switch network resources from one subset of nodes to another and it is a widespread phenomenon observed in many practical systems. Optimal control of networks has been studied to a great extent in the literature, however, the significant effects of reconfiguration delays received limited attention. Moreover, simultaneous presence of time-varying channels and reconfiguration delays has never been considered and we show that it impacts the system fundamentally. We first consider a Delay Tolerant Network model where data messages arriving randomly in time and space are collected by mobile collectors. In this setting reconfiguration delays correspond to travel times of collectors. We utilize a combination of wireless transmission and controlled mobility to improve the system delay scaling with load [rho] from [theta](1/(1-[rho])²) to [theta](1/1-[rho]), where the former is the delay for the corresponding system without wireless transmission. We propose control algorithms that stabilize the system whenever possible and have optimal delay scaling. Next, we consider a general queuing network model under reconfiguration delays and interference constraints which includes wireless, satellite and optical networks as special cases. We characterize the impacts of reconfiguration delays on system stability and delay, and propose scheduling algorithms that persist with service schedules for durations of time based on queue lengths to minimize negative impacts of reconfiguration delays. These algorithms provide throughput-optimality without requiring knowledge of arrival rates since they dynamically adapt inter-switching durations to stochastic arrivals. Finally, we present optimal scheduling under time-varying channels and reconfiguration delays, which is the main contribution of this thesis. We show that under the simultaneous presence of these two phenomenon network stability region shrinks, previously suggested policies are unstable, and new algorithmic approaches are necessary. We propose techniques based on state-action frequencies of Markov Decision Process theory to characterize the network stability region and propose throughput-optimal algorithms. The state-action frequency technique is applicable to a broad class of systems with or without reconfiguration delays, and provides a new framework for characterizing network stability region and developing throughput-optimal scheduling policies.
by Güner Dinc̦er C̦elik.
Ph.D.
Belaggoun, Amel. "Adaptability and reconfiguration of automotive embedded systems". Thesis, Paris 6, 2017. http://www.theses.fr/2017PA066252/document.
Texto completoModern vehicles have become increasingly computerized to satisfy the more strict safety requirements and to provide better driving experiences. Therefore, the number of electronic control units (ECUs) in modern vehicles has continuously increased in the last few decades. In addition, advanced applications put higher computational demand on ECUs and have both hard and soft timing constraints, hence a unified approach handling both constraints is required. Moreover, economic pressures and multi-core architectures are driving the integration of several levels of safety-criticality onto the same platform. Such applications have been traditionally designed using static approaches; however, static approaches are no longer feasible in highly dynamic environments due to increasing complexity and tight cost constraints, and more flexible solutions are required. This means that, to cope with dynamic environments, an automotive system must be adaptive; that is, it must be able to adapt its structure and/or behaviour at runtime in response to frequent changes in its environment. These new requirements cannot be faced by the current state-of-the-art approaches of automotive software systems. Instead, a new design of the overall Electric/Electronic (E/E) architecture of a vehicle needs to be developed. Recently, the automotive industry agreed upon changing the current AUTOSAR platform to the “AUTOSAR Adaptive Platform”. This platform is being developed by the AUTOSAR consortium as an additional product to the current AUTOSAR classic platform. This is an ongoing feasibility study based on the POSIX operating system and uses service-oriented communication to integrate applications into the system at any desired time. The main idea of this thesis is to develop novel architecture concepts based on adaptation to address the needs of a new E/E architecture for Fully Electric Vehicles (FEVs) regarding safety, reliability and cost-efficiency, and integrate these in AUTOSAR. We define the ASLA (Adaptive System Level in AUTOSAR) architecture, which is a framework that provides an adaptive solution for AUTOSAR. ASLA incorporates tasks-level reconfiguration features such as addition, deletion and migration of tasks in AUTOSAR. The main difference between ASLA and the Adaptive AUTOSAR platform is that ASLA enables the allocation of mixed critical functions on the same ECU as well as time-bound adaptations while adaptive AUTOSAR separates critical, hard real-time functions (running on the classic platform) from non-critical/soft-real-time functions (running on the adaptive platform). To assess the validity of our proposed architecture, we provide an early prototype implementation of ASLA and evaluate its performance through experiments
Liu, Ming. "Adaptive Computing based on FPGA Run-time Reconfigurability". Doctoral thesis, KTH, Elektroniksystem, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-33866.
Texto completoQC 20110531
Schneider, Etienne. "A middleware approach for dynamic real-time software : reconfiguration on distributed embedded systems". Université Louis Pasteur (Strasbourg) (1971-2008), 2004. https://publication-theses.unistra.fr/public/theses_doctorat/2004/SCHNEIDER_Etienne_2004.pdf.
Texto completoDynamic software reconfiguration is a useful tool to adapt and maintain software systems. In most approaches, the system has to be stopped while the reconfiguration is in progress. This is not suitable for real-time systems. Timing constraints must be met even while the system is reconfiguring. Our approach is based on the real-time middleware OSA+. Our main objective is to be able to reconfigure one (or more) service during the run-time, with a predictable and predefined blackout time (the time the systems does not react due to the reconfiguration). Three different approaches concerning the blocking or non-blocking state of a service are presented. These approaches can be used to realize a tradeoff between the reconfiguration time and the blackout time
Bittner, Ray Albert Jr. "Wormhole Run-Time Reconfiguration: Conceptualization and VLSI Design of a High Performance Computing System". Diss., Virginia Tech, 1997. http://hdl.handle.net/10919/30499.
Texto completoPh. D.
Lehn, David Ilan. "Framework for a Context-Switching Run-Time Reconfigurable System". Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/32300.
Texto completoThe reprogrammable nature of configurable computing machines has led to a wealth of research in run-time reconfigurable systems and applications. A limitation often encountered in this research is the slow configuration time with respect to the system clock speed. One technique to deal with these configuration delays has been to develop devices that can hold multiple rapidly interchangeable configurations. This technique is known as context-switching.
This thesis discusses the development of a framework to support applications which execute on a run-time reconfigurable system containing context-switching devices. The framework is divided into a number of layers: hardware, middleware, software, and applications. The design, implementation, and details of each layer are presented.
Master of Science
Templin, Joshua R. "Design of an Adaptable Run-Time Reconfigurable Software-Defined Radio Processing Architecture". DigitalCommons@USU, 2010. https://digitalcommons.usu.edu/etd/810.
Texto completoZhu, Dan. "Electric Distribution Reliability Analysis Considering Time-varying Load, Weather Conditions and Reconfiguration with Distributed Generation". Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/26557.
Texto completoPh. D.
Iskander, Yousef Shafik. "Improved Abstractions and Turnaround Time for FPGA Design Validation and Debug". Diss., Virginia Tech, 2012. http://hdl.handle.net/10919/28716.
Texto completoPh. D.
Scalera, Kevin R. "A Comparison of Control Allocation Methods for the F-15 ACTIVE Research Aircraft Utilizing Real-Time Piloted Simulations". Thesis, Virginia Tech, 1999. http://hdl.handle.net/10919/34113.
Texto completoMaster of Science
Rubattu, Claudio. "Response time analysis of parameterized dataflow applications on heterogeneous SW/HW systems". Thesis, Rennes, INSA, 2020. http://www.theses.fr/2020ISAR0005.
Texto completoIn contexts such as embedded and cyber-physical systems, the design of a desired functionality under constraints increasingly requires a parallel execution of different tasks on heterogeneous architectures. The nature of such parallel systems implies a huge complexity in understanding and predicting performance in terms of response time. Indeed, response time depends on many factors associated with the characteristics of both the functionality and the target architecture. State-of-the art strategies derive response time by examining the operations required by each task for both processing and accessing shared resources. This procedure is often followed by the addition or elimination of potential interferences due to task concurrency. However, such approaches require an advanced knowledge of the software and hardware details, rarely available in practice. This thesis provides an alternative "topdown" strategy aimed at extending the cases in which hardware and software response times can be analyzed and predicted. The proposed strategy leverages on dataflow-based application representations and focuses on the response time estimation of reconfigurable applications mapped on both general-purpose and specialized processing elements
Mégel, Thomas. "Placement, ordonnancement et mécanismes de migration de tâches temps-réel pour des architectures distribuées multicoeurs". Thesis, Toulouse, INPT, 2012. http://www.theses.fr/2012INPT0027/document.
Texto completoCritical real-time embedded systems are integrating an increasing number of functionalities, as shown in automotive domain or aeronautics. These systems require high dependability including mechanisms to handle possible failures and have to be effective, meeting hard real-time constraints. These systems are also constrained by their embedded nature : resources are limited, such as their memory and their computing capacities. In this thesis, we focus on two main problems for this type of systems. The first one is about a way to bring a better fault-tolerance in distributed real-time systems when multiple and permanent hardware failures can occur. In classical systems, the design is limited to a static task assignment. A more flexible approach exploiting reconfigurations is useful if it allows to optimize assignment at each failure for the remaining resources. We propose an off-line approach to obtain an adapted sizing taking into account necessary resources to execute these actions. These reconfigurations may require to reallocate tasks or replicas if memory capacities are limited. In a hard real-time context, we define mechanisms and migration techniques to guarantee global schedulability of the system. The second problem focus on optimizing performance to run tasks at a local level in a multicore preemptive context. We propose an optimal scheduling method allowing a better scalability than existing approaches by minimizing overheads : the number of context switches (local preemptions and migrations) and the scheduler complexity
Boukhanoufa, Mohamed-Lamine. "Adaptabilité et reconfiguration des systèmes temps-réel embarqués". Phd thesis, Université Paris Sud - Paris XI, 2012. http://tel.archives-ouvertes.fr/tel-00758807.
Texto completoKidane, Hiliwi Leake. "Run-time scalable NoC for virtualized FPGA based accelerators as cloud services". Thesis, Bourgogne Franche-Comté, 2018. http://www.theses.fr/2018UBFCK032.
Texto completoIn the last few years, cloud providers and data centers have been integrating FPGAs in their environment for acceleration purpose. This is due to the fact that FPGA based accelerator are known for their lower power and good performance per watt. Moreover, the introduction of the ability for dynamic partial reconfiguration (DPR) of some FPGAs trigger researchers in both industry and academics to propose DPR based virtualized FPGA (vFPGA) cloud services. In most of the existing works, the interconnection between the vFPGAs relies either on BUS or OpenFlow networks. However, both the bus and OpenFlow are not virtualization-aware and optimal solutions. In this thesis, we have proposed a virtualization-aware dynamically scalable NoC for virtualized FPGA accelerators in cloud computing. The NoC components will adapt to the number of active virtualized accelerator dynamically by adding and removing sub-NoCs. To minimize the complexity of NoC architecture design at a low level (HDL implementation), we have proposed a Model-Driven Engineering (MDE) based high-level unified modeling language (UML). A UML/MARTE and IP-XACT based approach are used to define the NoC Topology components at a high-level and generate the required HDL files. Experiment results show that the dynamically scalable NoC can reduce the power consumption by 17%. The MDE based high-level modeling based NoC characterization also reduce the design time by 25%
Hendry, James Hugh. "The Effects of Caching on Reconfigurable Adaptive Computing Systems". Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9682.
Texto completoMaster of Science
Puttegowda, Kiran. "Context Switching Strategies in a Run-Time Reconfigurable system". Thesis, Virginia Tech, 2002. http://hdl.handle.net/10919/32043.
Texto completoMaster of Science
Wilson, Andrew Elbert. "Dynamic Reconfigurable Real-Time Video Processing Pipelines on SRAM-based FPGAs". BYU ScholarsArchive, 2020. https://scholarsarchive.byu.edu/etd/8620.
Texto completoZhou, Ruoxing. "Dynamic Partial Reconfigurable FPGA". Thesis, Linköpings universitet, Datorteknik, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-74486.
Texto completoKahne, Brian C. "A Genetic Algorithm-Based Place-and-Route Compiler For A Run-time Reconfigurable Computing System". Thesis, Virginia Tech, 1997. http://hdl.handle.net/10919/36521.
Texto completoMaster of Science
Naz, André. "Algorithmique distribuée pour grands ensembles de robots : centralité, synchronisation et auto-reconfiguration". Thesis, Bourgogne Franche-Comté, 2017. http://www.theses.fr/2017UBFCD027/document.
Texto completoTechnological advances especially in the miniaturization of robotic devices foreshadow the emergence of large-scale ensembles of small-size resource-constrained robots that distributively cooperate to achieve complex tasks (e.g., modular self-reconfigurable robots, swarm robotic systems, distributed microelectromechanical systems, etc.). These ensembles are formed from independent, intelligent and communicating units which act as a whole ensemble. These units cooperatively self-organize themselves to achieve common goals. These systems are tought to be more versatile and more robust than conventional robotic systems while having at the same time a lower cost.These ensembles form complex asynchronous distributed systems in which every unit is an embedded system with its own but limited capabilities. Coordination of such large-scale distributed embedded systems poses significant algorithmic issues and open for new opportunities in distributed algorithms. In my thesis, I defend the idea that distributed algorithmic primitives suitable for the coordination of these ensembles should be both identified and designed.In this work, we focus on a specific class of modular robotics systems, namely large-scale distributed modular robotic ensembles composed of resource-constrained modules that are organized in a lattice structure and which can only communicate with neighboring modules. We identified and implemented three building blocks, namely centrality-based leader election, time synchronization and self-reconfiguration.We propose a collection of distributed algorithms to realize these primitives. We evaluate them using both hardware experiments and simulations on systems ranging from a dozen of modules to more than a dozen of thousands of modules. We show that our algorithms scale well and are suitable for large-scale embedded distributed systems with scarce memory and computing resources
Fazzoletto, Emilio. "Characterization of Partial and Run-Time Reconfigurable FPGAs". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-202724.
Texto completoFPGA-baserade system har tidigare främst använts för snabb och kostnadseffektiv konstruktion av prototyper vid framtagandet av applikationsspecika integrerade kretsar (ASIC). På senare år har användandet av FPGA:er i inbyggda system för implementation av hårdvaruacceleratorers såväl som huvudsaklig beräkningsenhet ökat. Denna ökning har möjliggjorts mycket tack vare den utveckling som har skett av rekonfigurerbara integrerade kretsar: från de mer traditionella Complex Programmable Logic Devices (CPLD) till helt CMOS-baserade FPGA:er. Nu inleds en ny era för FPGA-baserade system tack vare möjligheten att under körning rekonfigurera delar av FPGA:n genom så kallad partial run-time reconguration(RTR) - en teknik som redan idag finns tillgänglig i produkter på marknaden. Tidigare forskning visar att användandet av en RTR-baserad hårdvaruarkitektur kan ha en positiv effekt med avseende på prestanda såväl som strömförbrukning. Att använda RTR-baserad hårdvara innebär dock flera utmaningar: En ej försumbar rekonfigurationstid måste tas i beaktning, så även den icke-deterministiska exekveringstiden som en rekonfiguration kan innebära. Vidare måste anpassningar av mjukvaran göras för att fungera med en hårdvaruplattform som förändras över tid. Denna uppsats syftar till att undersöka prestandan hos ett modernt RTRbaserat SoC (Xilinx Zynq 7020) med fokus på rekonfigurationstider och dess förutsägbarhet, prestanda ökning, begränsningar samt nödvändiga kompromisser som denna arkitektur innebär. Huruvida en applikation kan dra nytta av en RTR-baserad arkitektur eller inte kan vara svårt att avgöra. Den insamlade datan som presenteras i denna rapport kan dock fungera som stöd för hårdvarukonstruktörer som önskar använda en RTR-baserad plattform.
Nilsson, Daniel y Henrik Norin. "Adaptive QoS Management in Dynamically Reconfigurable Real-Time Databases". Thesis, Linköping University, Department of Computer and Information Science, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-2800.
Texto completoDuring the last years the need for real-time database services has increased due to the growing number of data-intensive applications needing to enforce real-time constraints. The COMponent-based Embedded real-Time database (COMET) is a real-time database developed to meet these demands. COMET is developed using the AspeCtual COmponent-based Real-time system Development (ACCORD) design method, and consists of a number of components and aspects, which can be composed into a number of different configurations depending on system demands, e.g., Quality of Service (QoS) management can be used in unpredictable environments.
In embedded systems with requirementson high up-time it may not be possible to temporarily shut down the system for reconfiguration. Instead it is desirable to enable dynamic reconfiguration of the system, exchanging components during run-time. This in turn sets demands on the feedback control of the system to adjust to these new conditions, since a new time variant system has been created.
This thesis project implements improvements in COMET to create a more stable database suitable for further development. A mechanism for dynamic reconfiguration of COMET is implemented, thus, enabling components and aspects to be swapped during run-time. Adaptive feedback control algorithms are also implemented in order to better adjust to workload variations and database reconfiguration.
Gammoudi, Aymen. "Stratégie de placement et d'ordonnancement de taches logicielles pour architectures reconfigurables sous contrainte énergétique". Thesis, Rennes 1, 2018. http://www.theses.fr/2018REN1S030/document.
Texto completoThe design of embedded real-time systems is developing more and more with the increasing integration of critical functionalities for monitoring applications, particularly in the biomedical, environmental, home automation, etc. The developement of these systems faces various challenges particularly in terms of minimizing energy consumption. Managing such autonomous embedded devices, requires solving various problems related to the amount of energy available in the battery and the real-time scheduling of tasks that must be executed before their deadlines, to the reconfiguration scenarios, especially in the case of adding tasks, and to the communication constraint to be able to ensure messages exchange between cores, so as to ensure a lasting autonomy until the next recharge, while maintaining an acceptable level of quality of services for the processing system. To address this problem, we propose in this work a new strategy of placement and scheduling of tasks to execute real-time applications on an architecture containing heterogeneous cores. In this thesis, we have chosen to tackle this problem in an incremental manner in order to deal progressively with problems related to real-time, energy and communication constraints. First of all, we are particularly interested in the scheduling of tasks for single-core architecture. We propose a new scheduling strategy based on grouping tasks in packs to calculate the new task parameters in order to re-obtain the system feasibility. Then we have extended it to address the scheduling tasks on an homogeneous multi-core architecture. Finally, an extension of the latter will be achieved in order to realize the main objective, which is the scheduling of tasks for the heterogeneous architectures. The idea is to gradually take into account the constraints that are more and more complex. We formalize the proposed strategy as an optimization problem by using integer linear programming (ILP) and we compare the proposed solutions with the optimal results provided by the CPLEX solver. Inaddition, the validation by simulation of the proposed strategies shows that they generate a respectable gain compared with the criteria considered important in embedded systems, in particular the cost of communication between cores and the rate of new tasks rejection
Iturbe, Xabier. "Design and implementation of a reliable reconfigurable real-time operating system (R3TOS)". Thesis, University of Edinburgh, 2013. http://hdl.handle.net/1842/9413.
Texto completoXia, Tian. "Research on virtualisation technlogy for real-time reconfigurable systems". Thesis, Rennes, INSA, 2016. http://www.theses.fr/2016ISAR0009/document.
Texto completoThis thesis describes an original micro-kernel that manages virtualization and that provides an environment for real-time virtual machines. We have simplified the micro-kernel architecture by only keeping critical features required for virtualization, and massively reduced the kernel design complexity. Based on this micro-kernel, we have introduced a framework capable of DPR resource management in a virtual machine system. DPR accelerators are mapped as ordinary devices in each VM. Through dedicated memory management, our framework automatically detects the request for DPR resources and allocates them dynamically. According to various experiments and evaluations on the Zynq-7000 platform we have shown that Ker-ONE causes very low virtualization overheads, which can generally be ignored in real applications. We have also studied the real-time schedulability in virtual machines. The results show that RTOS tasks are guaranteed to be scheduled while meeting their intra-VM timing constraints. We have also demonstrated that the proposed framework is capable of virtual machine DPR allocation with low overhead
Blumer, Aric David. "Register Transfer Level Simulation Acceleration via Hardware/Software Process Migration". Diss., Virginia Tech, 2007. http://hdl.handle.net/10919/29380.
Texto completoPh. D.
Kojima, Leandro. "Metodologia de projeto de sistemas dinamicamente reconfiguráveis". Universidade de São Paulo, 2007. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-01082007-174443/.
Texto completoDynamically Reconfigurable Field Programmable Gate Arrays (DR-FPGAs) are promising solutions for many embedded systems due to the potential silicon area reduction. Design methodologies and related CAD tools are still very limited to assist designers to encounter dynamically reconfigurable solutions for different applications. This work proposes a design methodology that combines high level SystemC models and design techniques with the low level modular design proposed by Xilinx. SystemC has been used to represent the high level untimed non-RTL behavior as well as the low level RTL-DCS (Dynamic Circuit Switching). A Bluetooth Baseband unit case study was performed. Two temporal-functional partitions were evaluated on nine different target DR-FPGAs. The design space exploration showed that 33% of the investigated solutions complied with the 625µs Bluetooth packet time frame specification leaving different amounts if free resources that may be explored to accommodate other IP modules of more complex systems on the same device.
Zhao, Yue. "Automatic Prevention and Recovery of Aircraft Loss-of-Control by a Hybrid Control Approach". Ohio University / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1458728101.
Texto completoMarques, Sampaio Daniel. "Space and time in the making : urban reconfigurations of South and Southeast London". Thesis, Brunel University, 2003. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.249732.
Texto completoPabit, Sersita Suzette Atienza. "Fast dynamics in protein folding time-resolved fluorescence and absorbance studies of polypeptide reconfigurations /". [Gainesville, Fla.] : University of Florida, 2004. http://purl.fcla.edu/fcla/etd/UFE0004296.
Texto completoJara, Mario Andrés Raffo. "Desenvolvimento de um sistema dinamicamente reconfigurável baseado em redes intra-chip e ferramenta para posicionamento de módulos". Universidade de São Paulo, 2010. http://www.teses.usp.br/teses/disponiveis/3/3140/tde-11082010-100838/.
Texto completoDynamically Reconfigurable Systems (DRSs) are an alternative for developing Systems on a Programmable Chip (SoPC), being the efficient use of device\'s area one of its main advantages. Circuits implemented as DRSs represent tasks which must be active in specific times into the system operation, allowing area and energy saving, which is an important goal for portable systems. This has generated interests on the design methodology using Dynamically Reconfigurable Field Programmable Gate Arrays (DRFPGAs) and on the definition of communication systems for handling data transfer between static and reconfigurable partitions. However, these tasks, as well as the communication structure, are still carried out manually due to lack of design methodologies and CAD tools applied to DRSs design. This work focuses on the one of main drawbacks to the adoption of dynamic reconfiguration methods: the absence of CAD tools which support DRS designs, specifically, in the module positioning task, included, for those based on Network-on-Chip (NoCs). In this work, an architecture for DRSs based on NoCs is presented and an algorithm for module positioning is developed in a tool called DynoPlace as well, based on real specifications of DRFPGAs families. It is also developed a run-time simulation and validation model for DRSs, through a dynamic circuit switching technique. For the validation of architecture and methodology study case, an application test based on arithmetic operations has been proposed. The simulations methodology allows to determine the reconfiguration time and verify the DRS behavior at the moment of reconfiguration. The DynoPlace tool allows to generate User Constraint File (UCF) of DRS\'s modules positioning for the DRFPGA Virtex-4LX25. This file contains information of modules positioning in the system, of the devices used for inputs and outputs of the system, and the positioning of bus-macros. After the files generation by the methodology, and the DynoPlace tool, it is possible to successfully execute the Early Access scripts for generating the DRS automatically.
Coqblin, Mathias. "Optimisation du débit pour des applications linéaires multi-tâches sur plateformes distribuées incluant des temps de reconfiguration". Thesis, Besançon, 2015. http://www.theses.fr/2015BESA2059/document.
Texto completoIn this document we tackle scheduling problems of multitask linear workflow applications ondistributed platforms. In our particular problem the number of available machines on the platformis lower than the number of stages within the pipeline. The machines are then assumed to be able toperform any kind of task on the application given the appropriate reconfiguration (or setup), the catchbeing that any reconfiguration is time consuming. The problem that we try to solve is to maximizethe throughput of such applications, i.e., the mean amount of outputs per unit of time, or to minimizeits period, i.e., the average time between two outputs. As a result this problem is split into two subproblems:mapping tasks onto different machines of the platform (most machines will likely handleseveral tasks), and find an optimal schedule within a machine while taking setup times into account.To solve this we introduce buffers, which are spaces available for each machine to store temporaryproduction results and avoid reconfiguring after each task execution, and which may or may notbe already allocated for each stage. If those buffers are not already allocated to each task then athird problem must be solved to properly allocate the available space onto each buffer, as differentbuffer configurations have a huge impact on the scheduling of a machine. This document presentsan exhaustive coverage of the different problems that are associated with the heterogeneity of theapplication; the problems with homogeneous buffer capacities and setup times are rather simple tosolve, but they get a lot more complex as heterogeneity increases. We study the three main subproblemsfor each heterogeneity combination, and offer heuristic solution to solve them when anoptimal solution cannot be reasonably found
Andrés, Martínez David de. "Speeding-up model-based fault injection of deep-submicron CMOS fault models through dynamic and partially reconfigurable FPGAS". Doctoral thesis, Universitat Politècnica de València, 2008. http://hdl.handle.net/10251/1943.
Texto completoAndrés Martínez, DD. (2007). Speeding-up model-based fault injection of deep-submicron CMOS fault models through dynamic and partially reconfigurable FPGAS [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/1943
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Huang, Yongliang. "Une approche incrémentale pour l’extraction de séquences de franchissement dans un Réseau de Petri Temporisé : application à la reconfiguration des systèmes de production flexibles". Thesis, Ecole centrale de Lille, 2013. http://www.theses.fr/2013ECLI0018/document.
Texto completoThis PhD thesis is dedicated to the generation of firing sequences in Timed Petri Net (TPN) using an incremental approach. To reduce the influence of the well-known combinatorial explosion issue, a unique sequence of timed steps is introduced to represent implicitly the underlying reachability graph of the TPN, without needing its whole construction. This sequence of timed steps is developed based on the logical abstraction technique. The advantage of the incremental approach is that it can express any state just from the last step information, instead of representing all states before.Several incremental search algorithms are introduced to improve the efficiency of our methodology. Constraint programming techniques are used to model and solve our incremental model, in which search strategies are developed that can search for solutions more efficiently. Our methodology can be used to add specific constraints to model realistic systems. Token identification techniques are developed to handle token confusion issues that appear when addressing the reconfiguration of manufacturing systems. Experimental benchmarks illustrate the effectiveness of approaches proposed in this thesis
Gicquel, Céline. "MIP models and exact methods for the Discrete Lot-sizing and Scheduling Problem with sequence-dependent changeover costs and times". Phd thesis, Ecole Centrale Paris, 2008. http://tel.archives-ouvertes.fr/tel-00375964.
Texto completoLange, Sebastian y Martin Middendorf. "Hyperreconfigurable architectures for fast run time reconfiguration". 2004. https://ul.qucosa.de/id/qucosa%3A32843.
Texto completoSELVI, DANIELA. "Real-Time Control Reconfiguration for Active Disturbance Attenuation". Doctoral thesis, 2015. http://hdl.handle.net/2158/1003142.
Texto completoTseng, Chi-Hua y 曾啟華. "Reconfiguration Overhead Reduction and Hiding of Run-Time Reconfigurable System". Thesis, 2003. http://ndltd.ncl.edu.tw/handle/72639710189266801319.
Texto completo國立交通大學
資訊工程系
92
In run-time reconfigurable system, the whole partial reconfigurable hardware is viewed as a reconfiguration and execution unit traditionally. Therefore, execution cannot start until the finish reconfiguration of the whole partial reconfigurable hardware. We virtually divide the partial reconfigurable hardware into several equal-size blocks. The reconfiguration and execution unit is smaller. This can make reconfiguration of one block overlap with execution of other blocks. And this can hide some reconfiguration overhead. Doing so will bring a new problem which is partitions-to-blocks scheduling. We design a two phases scheduler. Phase I will generate one highest priority partition from un-scheduled partitions. There are three considerations of the partition’s priority. One is the partition is on current critical path or not. Another is the number of outgoing edges and released partitions of the partition. The other is the execution time of the partition. We have two partition selection policies including of critical first and utilization first. Phase II will assign one block to the highest priority partition generated from Phase I. If the partition is the latest partition, we will assign one block to the partition so that the partition can finish execution earliest. If the partition is not the latest partition, we will look ahead one next future partition into consideration together. Choose one block to the primary partition so that these two partitions can release maximal resource with time. The result shows that utilization first is better than critical first. And view a part of the whole partial reconfigurable hardware as a reconfiguration and execution unit can improve completion time of run-time reconfigurable system.
Lo, Hsin-I. y 羅信易. "Real-Time Dynamic Partial Reconfiguration Platform For Implementation Digital Image Processing Application". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/70588048564477845138.
Texto completo元智大學
資訊工程學系
98
This paper raises an image processing application which utilizes a platform of dynamic real-time partial reconfiguration. Initially, design a platform of dynamic real-time partial reconfiguration platform and hereby use it to conduct image processing of dilation and erosion as exemplifications here[1].In the algorithm of image processing, morphing of dilation and erosion would be functions of Maximum Filter and Minimum Filter respectively. The platform of real-time partial reconfiguration is composed of a Microprocessor (MicroBlaze)[2] as the core of this system and of both Maximum and Minimum Filters, formed with two modules which are respectively built according to the differences of them executing comparator and are switched to the region based on the concept of partial reconfiguration. On the side of implementation, the Microprocessor (MicroBlaze) is designed in Xilinx XPS 9.2[3] and functions of two filters are programmed by Verilog in Xilinx ISE 9.2i. Eventually, implement the function of system onto Xilinx Virtex-5 ML-506[4] as verification.