Artículos de revistas sobre el tema "Reconfigurable Hardware Architecture"
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Thomas, Alexander, Michael Rückauer y Jürgen Becker. "HoneyComb: An Application-Driven Online Adaptive Reconfigurable Hardware Architecture". International Journal of Reconfigurable Computing 2012 (2012): 1–17. http://dx.doi.org/10.1155/2012/832531.
Texto completoSiddiqui, Ali Shuja, Yutian Gui y Fareena Saqib. "Secure Boot for Reconfigurable Architectures". Cryptography 4, n.º 4 (25 de septiembre de 2020): 26. http://dx.doi.org/10.3390/cryptography4040026.
Texto completoFabiani, Erwan. "Experiencing a Problem-Based Learning Approach for Teaching Reconfigurable Architecture Design". International Journal of Reconfigurable Computing 2009 (2009): 1–11. http://dx.doi.org/10.1155/2009/923415.
Texto completoPionteck, Thilo, Roman Koch, Carsten Albrecht y Erik Maehle. "A Design Technique for Adapting Number and Boundaries of Reconfigurable Modules at Runtime". International Journal of Reconfigurable Computing 2009 (2009): 1–10. http://dx.doi.org/10.1155/2009/942930.
Texto completoGöhringer, Diana, Thomas Perschke, Michael Hübner y Jürgen Becker. "A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip". International Journal of Reconfigurable Computing 2009 (2009): 1–11. http://dx.doi.org/10.1155/2009/395018.
Texto completoWijtvliet, Mark, Henk Corporaal y Akash Kumar. "CGRA-EAM—Rapid Energy and Area Estimation for Coarse-grained Reconfigurable Architectures". ACM Transactions on Reconfigurable Technology and Systems 14, n.º 4 (31 de diciembre de 2021): 1–28. http://dx.doi.org/10.1145/3468874.
Texto completoVoss, Nils, Bastiaan Kwaadgras, Oskar Mencer, Wayne Luk y Georgi Gaydadjiev. "On Predictable Reconfigurable System Design". ACM Transactions on Architecture and Code Optimization 18, n.º 2 (marzo de 2021): 1–28. http://dx.doi.org/10.1145/3436995.
Texto completoCraven, Stephen y Peter Athanas. "Dynamic Hardware Development". International Journal of Reconfigurable Computing 2008 (2008): 1–10. http://dx.doi.org/10.1155/2008/901328.
Texto completoNAKANO, KOJI. "A BIBLIOGRAPHY OF PUBLISHED PAPERS ON DYNAMICALLY RECONFIGURABLE ARCHITECTURES". Parallel Processing Letters 05, n.º 01 (marzo de 1995): 111–24. http://dx.doi.org/10.1142/s0129626495000102.
Texto completoPurohit, Gaurav, Kota Solomon Raju y Vinod Kumar Chaubey. "XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware". International Journal of Reconfigurable Computing 2016 (2016): 1–8. http://dx.doi.org/10.1155/2016/9128683.
Texto completoDUAN, Tong, Julong LAN, Yuxiang HU y Shiran LIU. "A Reconfigurable Hardware Architecture for Packet Processing". Chinese Journal of Electronics 27, n.º 2 (1 de marzo de 2018): 428–32. http://dx.doi.org/10.1049/cje.2017.08.018.
Texto completoIrmak, Hasan, Federico Corradi, Paul Detterer, Nikolaos Alachiotis y Daniel Ziener. "A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs". Journal of Low Power Electronics and Applications 11, n.º 3 (17 de agosto de 2021): 32. http://dx.doi.org/10.3390/jlpea11030032.
Texto completoMAJZOUB, S. y H. DIAB. "INSTRUCTION-SET EXTENSION FOR CRYPTOGRAPHIC APPLICATIONS ON RECONFIGURABLE PLATFORM". Journal of Circuits, Systems and Computers 16, n.º 06 (diciembre de 2007): 911–27. http://dx.doi.org/10.1142/s0218126607004076.
Texto completoDas, Nitish y Aruna Priya P. "FPGA Implementation of an Improved Reconfigurable FSMIM Architecture Using Logarithmic Barrier Function Based Gradient Descent Approach". International Journal of Reconfigurable Computing 2019 (1 de abril de 2019): 1–17. http://dx.doi.org/10.1155/2019/3727254.
Texto completoLe, Shu Ping, Zhi Wen Xiong y Hong Zeng. "Design and Implement of the Reconfigurable Algorithm Based on uC/OS-II". Applied Mechanics and Materials 198-199 (septiembre de 2012): 1372–77. http://dx.doi.org/10.4028/www.scientific.net/amm.198-199.1372.
Texto completoSandres, Paulo Renato de Souza Silva, Nadia Nedjah y Luiza de Macedo Mourelle. "Reconfigurable hardware for fuzzy controller". International Journal of High Performance Systems Architecture 4, n.º 3 (2013): 144. http://dx.doi.org/10.1504/ijhpsa.2013.055225.
Texto completoVranjković, Vuk S., Rastislav J. R. Struharik y Ladislav A. Novak. "Reconfigurable Hardware for Machine Learning Applications". Journal of Circuits, Systems and Computers 24, n.º 05 (8 de abril de 2015): 1550064. http://dx.doi.org/10.1142/s0218126615500644.
Texto completoPerin, Guilherme, Daniel Gomes Mesquita y João Baptista Martins. "Montgomery Modular Multiplication on Reconfigurable Hardware: Systolic versus Multiplexed Implementation". International Journal of Reconfigurable Computing 2011 (2011): 1–10. http://dx.doi.org/10.1155/2011/127147.
Texto completoGarzia, Fabio, Roberto Airoldi y Jari Nurmi. "Implementation of FFT on General-Purpose Architectures for FPGA". International Journal of Embedded and Real-Time Communication Systems 1, n.º 3 (julio de 2010): 24–43. http://dx.doi.org/10.4018/jertcs.2010070102.
Texto completoBelaid, Ikbel, Fabrice Muller y Maher Benjemaa. "Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices". International Journal of Reconfigurable Computing 2011 (2011): 1–28. http://dx.doi.org/10.1155/2011/591983.
Texto completoLopes, João D., Mário P. Véstias, Rui Policarpo Duarte , Horácio C. Neto y José T. de Sousa. "Coarse-Grained Reconfigurable Computing with the Versat Architecture". Electronics 10, n.º 6 (12 de marzo de 2021): 669. http://dx.doi.org/10.3390/electronics10060669.
Texto completoReza. "Reconfigurable Hardware Architecture for Network Intrusion Detection System". American Journal of Applied Sciences 9, n.º 10 (1 de octubre de 2012): 1618–24. http://dx.doi.org/10.3844/ajassp.2012.1618.1624.
Texto completoKorat, Uday A. y Amirhossein Alimohammad. "A Reconfigurable Hardware Architecture for Principal Component Analysis". Circuits, Systems, and Signal Processing 38, n.º 5 (11 de octubre de 2018): 2097–113. http://dx.doi.org/10.1007/s00034-018-0953-y.
Texto completoHwang, Wen-Jyi, Wei-Hao Lee, Shiow-Jyu Lin y Sheng-Ying Lai. "Efficient Architecture for Spike Sorting in Reconfigurable Hardware". Sensors 13, n.º 11 (1 de noviembre de 2013): 14860–87. http://dx.doi.org/10.3390/s131114860.
Texto completoRedif, Soydan y Server Kasap. "Novel Reconfigurable Hardware Architecture for Polynomial Matrix Multiplications". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, n.º 3 (marzo de 2015): 454–65. http://dx.doi.org/10.1109/tvlsi.2014.2312997.
Texto completoKaufmann, Paul, Kyrre Glette, Marco Platzner y Jim Torresen. "Compensating Resource Fluctuations by Means of Evolvable Hardware". International Journal of Adaptive, Resilient and Autonomic Systems 3, n.º 4 (octubre de 2012): 17–31. http://dx.doi.org/10.4018/jaras.2012100102.
Texto completoLi, Peng, Hongyi Jin, Wei Xi, Changbao Xu, Hao Yao y Kai Huang. "A Reconfigurable Hardware Architecture for Miscellaneous Floating-Point Transcendental Functions". Electronics 12, n.º 1 (3 de enero de 2023): 233. http://dx.doi.org/10.3390/electronics12010233.
Texto completoUchevler, Bahram N. y Kjetil Svarstad. "Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions". International Journal of Reconfigurable Computing 2018 (10 de julio de 2018): 1–25. http://dx.doi.org/10.1155/2018/3276159.
Texto completoDrzevitzky, Stephanie, Uwe Kastens y Marco Platzner. "Proof-Carrying Hardware: Concept and Prototype Tool Flow for Online Verification". International Journal of Reconfigurable Computing 2010 (2010): 1–11. http://dx.doi.org/10.1155/2010/180242.
Texto completoBobda, Christophe, Kevin Cheng, Felix Mühlbauer, Klaus Drechsler, Jan Schulte, Dominik Murr y Camel Tanougast. "Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware". International Journal of Reconfigurable Computing 2009 (2009): 1–9. http://dx.doi.org/10.1155/2009/161458.
Texto completoDEL CAMPO, INÉS, JAVIER ECHANOBE, KOLDO BASTERRETXEA y GUILLERMO BOSQUE. "SCALABLE ARCHITECTURE FOR HIGH-SPEED MULTIDIMENSIONAL FUZZY INFERENCE SYSTEMS". Journal of Circuits, Systems and Computers 20, n.º 03 (mayo de 2011): 375–400. http://dx.doi.org/10.1142/s0218126611007359.
Texto completoAl-Wattar, A., S. Areibi y G. Grewal. "An Efficient Evolutionary Task Scheduling/Binding Framework for Reconfigurable Systems". International Journal of Reconfigurable Computing 2016 (2016): 1–24. http://dx.doi.org/10.1155/2016/9012909.
Texto completoS, Suji y Radhika P. "Design of Reconfigurable Block FIR Filter Architecture and Implementation on Hardware". International Journal of Engineering & Technology 7, n.º 3.12 (20 de julio de 2018): 826. http://dx.doi.org/10.14419/ijet.v7i3.12.16511.
Texto completoOU, CHIEN-MIN. "EFFICIENT MUSIC RETRIEVAL SYSTEMS DESIGN BASED ON RECONFIGURABLE HARDWARE". Journal of Circuits, Systems and Computers 20, n.º 05 (agosto de 2011): 927–42. http://dx.doi.org/10.1142/s0218126611007694.
Texto completoSO, K., J. KIM, W. K. CHO, Y. S. KIM y D. Y. SUH. "Reconfigurable Inner Product Hardware Architecture for Increased Hardware Utilization in SDR Systems". IEICE Transactions on Communications E89-B, n.º 12 (1 de diciembre de 2006): 3242–49. http://dx.doi.org/10.1093/ietcom/e89-b.12.3242.
Texto completoSankara Phani, T. Siva, M. Sujatha, K. Hari Kishore y M. Durga Prakash. "Implementation of FPGA based MRPMA for high performance applications". International Journal of Engineering & Technology 7, n.º 1.5 (31 de diciembre de 2017): 158. http://dx.doi.org/10.14419/ijet.v7i1.5.9139.
Texto completoAn, Fubang, Lingli Wang y Xuegong Zhou. "A High Performance Reconfigurable Hardware Architecture for Lightweight Convolutional Neural Network". Electronics 12, n.º 13 (27 de junio de 2023): 2847. http://dx.doi.org/10.3390/electronics12132847.
Texto completoOu, Chien-Min, Tsung-Yi yu, Wen-Jyi Hwang y Tsung-Che Chiang. "Efficient Architecture For Island Genetic Algorithm in Reconfigurable Hardware". Intelligent Automation & Soft Computing 18, n.º 4 (enero de 2012): 413–30. http://dx.doi.org/10.1080/10798587.2012.10643252.
Texto completoKim, Y. y H. Jung. "Reconfigurable hardware architecture for faster descriptor extraction in SURF". Electronics Letters 54, n.º 4 (febrero de 2018): 210–12. http://dx.doi.org/10.1049/el.2017.3133.
Texto completoJosé Garcia Neto Segundo, Edgar, Nadia Nedjah y Luiza de Macedo Mourelle. "A scalable parallel reconfigurable hardware architecture for DNA matching". Integration 46, n.º 3 (junio de 2013): 240–46. http://dx.doi.org/10.1016/j.vlsi.2013.01.002.
Texto completoLe Ly, Daniel y Paul Chow. "High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines". IEEE Transactions on Neural Networks 21, n.º 11 (noviembre de 2010): 1780–92. http://dx.doi.org/10.1109/tnn.2010.2073481.
Texto completoRavi, Aadithya, Easwara E. A. Moorthy, D. Vidya y G. Mahesh Kumar. "Hybrid Reconfigurable PC Add-on Card for Parallel Image Processing". Applied Mechanics and Materials 110-116 (octubre de 2011): 5057–62. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.5057.
Texto completoEddine, Khamlich Salah, Khamlich Fathallah, Issam Atouf y Benrabh Mohamed. "Parallel Implementation of Nios Ii Multiprocessors, Cepstral Coefficients of Mel Frequency and MLP Architecture in Fpga: the Application of Speech Recognition". WSEAS TRANSACTIONS ON SIGNAL PROCESSING 16 (13 de enero de 2021): 146–54. http://dx.doi.org/10.37394/232014.2020.16.16.
Texto completoJameil, Ahmed K., Yassir A. Ahmed y Saad Albawi. "Efficient FIR Filter Architecture using FPGA". Recent Advances in Computer Science and Communications 13, n.º 1 (13 de marzo de 2020): 91–98. http://dx.doi.org/10.2174/2213275912666190603115506.
Texto completoBelaid, Ikbel, Fabrice Muller y Maher Benjemaa. "New Three-Level Resource Management Enhancing Quality of Offline Hardware Task Placement on FPGA". International Journal of Reconfigurable Computing 2010 (2010): 1–20. http://dx.doi.org/10.1155/2010/980762.
Texto completoDalbouchi, Roukaya, Salah Dhahri, Majdi Elhajji y Abdelkrim Zitouni. "New Hardware Static and Reconfigurable Architectures for Video Watermarking System". Journal of Circuits, Systems and Computers 29, n.º 10 (20 de diciembre de 2019): 2050168. http://dx.doi.org/10.1142/s0218126620501686.
Texto completoXiong, Hao, Kelin Sun, Bing Zhang, Jingchuan Yang y Huiping Xu. "Deep-Sea: A Reconfigurable Accelerator for Classic CNN". Wireless Communications and Mobile Computing 2022 (2 de febrero de 2022): 1–23. http://dx.doi.org/10.1155/2022/4726652.
Texto completoQIAO, CHUNMING. "ON DESIGNING COMMUNICATION-INTENSIVE ALGORITHMS FOR A SPANNING OPTICAL BUS BASED ARRAY". Parallel Processing Letters 05, n.º 03 (septiembre de 1995): 499–511. http://dx.doi.org/10.1142/s012962649500045x.
Texto completoSeo, Jungwon, Jamie Paik y Mark Yim. "Modular Reconfigurable Robotics". Annual Review of Control, Robotics, and Autonomous Systems 2, n.º 1 (3 de mayo de 2019): 63–88. http://dx.doi.org/10.1146/annurev-control-053018-023834.
Texto completoMelnyk, Viktor A. y Vladyslav V. Hamolia. "Investigation of reconfigurable hardware platforms for 5G protocol stack functions acceleration". Applied Aspects of Information Technology 6, n.º 1 (10 de abril de 2023): 84–99. http://dx.doi.org/10.15276/aait.06.2023.7.
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