Literatura académica sobre el tema "Progettistica hardware e software"
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Artículos de revistas sobre el tema "Progettistica hardware e software"
Breazeale, Vicki. "Software/Hardware". Journal of Nutrition Education 17, n.º 4 (octubre de 1985): 162. http://dx.doi.org/10.1016/s0022-3182(85)80086-8.
Texto completoKellerhoff, Peter. "Software überflügelt Hardware". VDI nachrichten 74, n.º 28-29 (2020): 3. http://dx.doi.org/10.51202/0042-1758-2020-28-29-3.
Texto completoGupta, P. "Hardware-software codesign". IEEE Potentials 20, n.º 5 (2002): 31–32. http://dx.doi.org/10.1109/45.983337.
Texto completoJerraya, A. "Hardware-software codesign". IEEE Design and Test of Computers 17, n.º 1 (enero de 2000): 92–99. http://dx.doi.org/10.1109/mdt.2000.825680.
Texto completoHarris, I. G. "Hardware/software covalidation". IEE Proceedings - Computers and Digital Techniques 152, n.º 3 (2005): 380. http://dx.doi.org/10.1049/ip-cdt:20045095.
Texto completoPerel, Morton L. "Hardware, Software, Brainware". Implant Dentistry 16, n.º 1 (2007): 1. http://dx.doi.org/10.1097/id.0b013e3180327609.
Texto completoRandell, Brian. "Hardware/software tradeoffs". ACM SIGARCH Computer Architecture News 13, n.º 2 (junio de 1985): 19–21. http://dx.doi.org/10.1145/1296935.1296938.
Texto completoDay, Charles. "Software Makes Hardware". Computing in Science & Engineering 10, n.º 6 (noviembre de 2008): 104. http://dx.doi.org/10.1109/mcse.2008.156.
Texto completoGramm, Andreas. "Hardware & Software". LOG IN 31, n.º 2-3 (enero de 2011): 118–21. http://dx.doi.org/10.1007/bf03323739.
Texto completoBray-Garretson, Helen y Richard O'Connor. "Hardware, Software, Etc." Contemporary Psychology: A Journal of Reviews 38, n.º 2 (febrero de 1993): 214–15. http://dx.doi.org/10.1037/033080.
Texto completoTesis sobre el tema "Progettistica hardware e software"
Taylor, Ramsay G. "Verification of hardware dependent software". Thesis, University of Sheffield, 2012. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.575744.
Texto completoHilton, Adrian J. "High integrity hardware-software codesign". Thesis, Open University, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.402249.
Texto completoEdmison, Joshua Nathaniel. "Hardware Architectures for Software Security". Diss., Virginia Tech, 2006. http://hdl.handle.net/10919/29244.
Texto completoPh. D.
Blaha, Vít. "Hardware a software inteligentního spotřebiče". Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221136.
Texto completoFigueiredo, Boneti Carlos Santieri de. "Exploring coordinated software and hardware support for hardware resource allocation". Doctoral thesis, Universitat Politècnica de Catalunya, 2009. http://hdl.handle.net/10803/6018.
Texto completoThis thesis targets to narrow the gap between the software and the hardware, with respect to the hardware resource allocation, by proposing a new explicit resource allocation hardware mechanism and novel schedulers that use the currently available hardware resource allocation mechanisms.
It approaches the problem in two different types of computing systems: on the high performance computing domain, we characterize the first processor to present a mechanism that allows the software to bias the allocation hardware resources, the IBM POWER5. In addition, we propose the use of hardware resource allocation as a way to balance high performance computing applications. Finally, we propose two new scheduling mechanisms that are able to transparently and successfully balance applications in real systems using the hardware resource allocation. On the soft real-time domain, we propose a hardware extension to the existing explicit resource allocation hardware and, in addition, two software schedulers that use the explicit allocation hardware to improve the schedulability of tasks in a soft real-time system.
In this thesis, we demonstrate that system performance improves by making the software aware of the mechanisms to control the amount of resources given to each running thread. In particular, for the high performance computing domain, we show that it is possible to decrease the execution time of MPI applications biasing the hardware resource assignation between threads. In addition, we show that it is possible to decrease the number of missed deadlines when scheduling tasks in a soft real-time SMT system.
Nilsson, Per. "Hardware / Software co-design for JPEG2000". Thesis, Linköping University, Department of Electrical Engineering, 2006. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-5796.
Texto completoFor demanding applications, for example image or video processing, there may be computations that aren’t very suitable for digital signal processors. While a DSP processor is appropriate for some tasks, the instruction set could be extended in order to achieve higher performance for the tasks that such a processor normally isn’t actually design for. The platform used in this project is flexible in the sense that new hardware can be designed to speed up certain computations.
This thesis analyzes the computational complex parts of JPEG2000. In order to achieve sufficient performance for JPEG2000, there may be a need for hardware acceleration.
First, a JPEG2000 decoder was implemented for a DSP processor in assembler. When the firmware had been written, the cycle consumption of the parts was measured and estimated. From this analysis, the bottlenecks of the system were identified. Furthermore, new processor instructions are proposed that could be implemented for this system. Finally the performance improvements are estimated.
Endresen, Vegard Haugen. "Hardware-software intercommunication in reconfigurable systems". Thesis, Norwegian University of Science and Technology, Department of Electronics and Telecommunications, 2010. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-10762.
Texto completoIn this thesis hardware-software intercommunication in a reconfigurable system has been investigated based on a framework for run time reconfiguration. The goal has been to develop a fast and flexible link between applications running on an embedded processor and reconfigurable accelerator hardware in form of a Xilinx Virtex device. As a start the link was broken down into hardware and software components based on constraints from earlier work and a general literature search. A register architecture for reconfigurable modules, a reconfigurable interface and a backend bridge linking reconfigurable hardware with the system bus were identified as the main hardware components whereas device drivers and a hardware operating system were identified as software components. These components were developed in a bottom-up approach, then deployed, tested and evaluated. Synthesis and simulation results from this thesis suggest that a hybrid register architecture, a mix of shift based and addressable register architecture might be a good solution for a reconfigurable module. Such an architecture enables a reconfigurable interface with full duplex capability with an initially small area overhead compared to a full scale RAM implementation. Although the hybrid architecture might not be very suitable for all types of reconfigurable modules it can be a nice compromise when attempting to achieve a uniform reconfigurable interface. Backend bridge solutions were developed assuming the above hybrid reconfigurable interface. Three main types were researched: a software register backend, a data cache backend and an instruction and data cache backend. Performance evaluation shows that the instruction and data cache outperforms the other two with an average acceleration ratio of roughly 5-10. Surprisingly the data cache backend performs worst of all due to latency ratios and design choices. Aside from the BRAM component required for the cache backends, resource consumption was shown to be only marginally larger than a traditional software register solution. Caching using a controller in the backend-bridge can thus provide good speedup for little cost as far as BRAM resources are not scarce. A software-to-hardware interface has been created has been created through Linux character device driver and a hardware operating system daemon. While the device drivers provide a middleware layer for hardware access the HWOS separates applications from system management through a message queue interface. Performance testing shows a large increase in delay when involving the Linux device drivers and the HWOS as compared to calls directly from the kernel. Although this is natural, the software components are very important when providing a high performance platform. As additional work specialized cell handling for reconfigurable modules has been addressed in the context of a MPEG-4 decoder. Some light has also been shed on design of reconfigurable modules in Xilinx ISE which can radically improve development time and decrease complexity compared to a Xilinx Platform Studio flow. In the process of demonstrating run time reconfigurations it was discovered that a clock signal will resist being piped through bus macros. Also broken functionality has been shown when applying run time reconfiguration to synchronous designs using the framework for self reconfiguration.
Lu, Yandong. "Hardware/Software Partitioning of Embedded Svstems". Thesis, University of Manchester, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.520747.
Texto completoKing, Myron Decker. "A methodology for hardware-software codesign". Thesis, Massachusetts Institute of Technology, 2013. http://hdl.handle.net/1721.1/84891.
Texto completoCataloged from PDF version of thesis.
Includes bibliographical references (pages 150-156).
Special purpose hardware is vital to embedded systems as it can simultaneously improve performance while reducing power consumption. The integration of special purpose hardware into applications running in software is difficult for a number of reasons. Some of the difficulty is due to the difference between the models used to program hardware and software, but great effort is also required to coordinate the simultaneous execution of the application running on the microprocessor with the accelerated kernel(s) running in hardware. To further compound the problem, current design methodologies for embedded applications require an early determination of the design partitioning which allows hardware and software to be developed simultaneously, each adhering to a rigid interface contract. This approach is problematic because often a good hardware-software decomposition is not known until deep into the design process. Fixed interfaces and the burden of reimplementation prevent the migration of functionality motivated by repartitioning. This thesis presents a two-part solution to the integration of special purpose hardware into applications running in software. The first part addresses the problem of generating infrastructure for hardware-accelerated applications. We present a methodology in which the application is represented as a dataflow graph and the computation at each node is specified for execution either in software or as specialized hardware using the programmer's language of choice. An interface compiler as been implemented which takes as input the FIFO edges of the graph and generates code to connect all the different parts of the program, including those which communicate across the hardware/software boundary. This methodology, which we demonstrate on an FPGA platform, enables programmers to effectively exploit hardware acceleration without ever leaving the application space. The second part of this thesis presents an implementation of the Bluespec Codesign Language (BCL) to address the difficulty of experimenting with hardware/software partitioning alternatives. Based on guarded atomic actions, BCL can be used to specify both hardware and low-level software. Based on Bluespec SystemVerilog (BSV) for which a hardware compiler by Bluespec Inc. is commercially available, BCL has been augmented with extensions to support more efficient software generation. In BCL, the programmer specifies the entire design, including the partitioning, allowing the compiler to synthesize efficient software and hardware, along with transactors for communication between the partitions. The benefit of using a single language to express the entire design is that a programmer can easily experiment with many different hardware/software decompositions without needing to re-write the application code. Used together, the BCL and interface compilers represent a comprehensive solution to the task of integrating specialized hardware into an application.
by Myron King.
Ph.D.
Nagaonkar, Yajuvendra. "FPGA-based Experiment Platform for Hardware-Software Codesign and Hardware Emulation". Diss., CLICK HERE for online access, 2006. http://contentdm.lib.byu.edu/ETD/image/etd1294.pdf.
Texto completoLibros sobre el tema "Progettistica hardware e software"
Ecker, Wolfgang, Wolfgang Müller y Rainer Dömer, eds. Hardware-dependent Software. Dordrecht: Springer Netherlands, 2009. http://dx.doi.org/10.1007/978-1-4020-9436-1.
Texto completoEngineers, Society of Automotive y SAE World Congress (2005 : Detroit, Mich.), eds. Software/hardware systems. Warrendale, Pa: SAE International, 2005.
Buscar texto completoGorsline, G. W. Computer organization: Hardware/software. 2a ed. Englewood Cliffs, N.J: Prentice-Hall, 1986.
Buscar texto completoMicheli, Giovanni y Mariagiovanna Sami, eds. Hardware/Software Co-Design. Dordrecht: Springer Netherlands, 1996. http://dx.doi.org/10.1007/978-94-009-0187-2.
Texto completoTeich, Jürgen. Digitale Hardware/Software-Systeme. Berlin, Heidelberg: Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/978-3-662-06740-6.
Texto completoHaubelt, Christian y Jürgen Teich. Digitale Hardware/Software-Systeme. Berlin, Heidelberg: Springer Berlin Heidelberg, 2010. http://dx.doi.org/10.1007/978-3-642-05356-6.
Texto completoCady, Fredrick M. Software and hardware engineering. New York: Oxford University Press, 1997.
Buscar texto completoM, Sibigtroth James, ed. Software and hardware engineering. New York: Oxford University Press, 2000.
Buscar texto completoGorsline, George W. Computer organization: Hardware/software. 2a ed. London: Prentice-Hall, 1986.
Buscar texto completoBenjamin, Zee, ed. Computer hardware/software architecture. Englewood Cliffs, N.J: Prentice-Hall, 1986.
Buscar texto completoCapítulos de libros sobre el tema "Progettistica hardware e software"
Zemanek, Heinz. "Hardware — Software". En Foundations of Computer Science, 9–19. Berlin, Heidelberg: Springer Berlin Heidelberg, 1997. http://dx.doi.org/10.1007/bfb0052073.
Texto completoMurata, Satoshi y Haruhisa Kurokawa. "Hardware and Software". En Springer Tracts in Advanced Robotics, 211–33. Tokyo: Springer Tokyo, 2012. http://dx.doi.org/10.1007/978-4-431-54055-7_9.
Texto completoMaul, Harald y Georg Ziemes. "Software-Hardware-Schnittstellen". En PLOTGRAF, 277–91. Wiesbaden: Vieweg+Teubner Verlag, 1987. http://dx.doi.org/10.1007/978-3-322-86095-8_5.
Texto completoSucaet, Yves y Wim Waelput. "Hardware and Software". En Digital Pathology, 15–29. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-08780-1_2.
Texto completoBähring, Helmut. "Hardware/Software-Schnittstelle". En Springer-Lehrbuch, 141–215. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/978-3-662-12500-7_3.
Texto completoBund, Elmar. "Hardware und Software". En Einführung in die Rechtsinformatik, 13–18. Berlin, Heidelberg: Springer Berlin Heidelberg, 1991. http://dx.doi.org/10.1007/978-3-642-76103-4_3.
Texto completoEles, Petru, Krzysztof Kuchcinski y Zebo Peng. "Hardware/Software Partitioning". En System Synthesis with VHDL, 275–99. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2789-0_8.
Texto completoNiemann, Ralf. "Hardware/Software Partitioning". En Hardware/Software Co-Design for Data Flow Dominated Embedded Systems, 47–131. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-2803-3_4.
Texto completoDi Cataldo, Giuseppe. "Hardware and Software". En Stack Frames, 1–19. Berkeley, CA: Apress, 2016. http://dx.doi.org/10.1007/978-1-4842-2181-5_1.
Texto completoSchaumont, Patrick R. "Hardware/Software Interfaces". En A Practical Introduction to Hardware/Software Codesign, 259–301. Boston, MA: Springer US, 2010. http://dx.doi.org/10.1007/978-1-4419-6000-9_9.
Texto completoActas de conferencias sobre el tema "Progettistica hardware e software"
Lee, Robert P., Konstantinos Markantonakis y Raja Naeem Akram. "Provisioning Software with Hardware-Software Binding". En ARES '17: International Conference on Availability, Reliability and Security. New York, NY, USA: ACM, 2017. http://dx.doi.org/10.1145/3098954.3103158.
Texto completoStitt, Greg, Frank Vahid, Gordon McGregor y Brian Einloth. "Hardware/software partitioning of software binaries". En the 3rd IEEE/ACM/IFIP international conference. New York, New York, USA: ACM Press, 2005. http://dx.doi.org/10.1145/1084834.1084905.
Texto completoStitt, Greg y Frank Vahid. "Hardware/software partitioning of software binaries". En the 2002 IEEE/ACM international conference. New York, New York, USA: ACM Press, 2002. http://dx.doi.org/10.1145/774572.774596.
Texto completoReddi, Vijay Janapa, Meeta S. Gupta, Michael D. Smith, Gu-yeon Wei, David Brooks y Simone Campanoni. "Software-assisted hardware reliability". En the 46th Annual Design Automation Conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1629911.1630114.
Texto completoKeutzer, Kurt. "Hardware/software co-simulation". En the 31st annual conference. New York, New York, USA: ACM Press, 1994. http://dx.doi.org/10.1145/196244.196458.
Texto completoMills, Mike y Greg Peterson. "Hardware/software co-design". En the 1998 annual ACM SIGAda international conference. New York, New York, USA: ACM Press, 1998. http://dx.doi.org/10.1145/289524.289528.
Texto completoDalpasso, Marcello, Alessandro Bogliolo y Luca Benini. "Hardware/software IP protection". En the 37th conference. New York, New York, USA: ACM Press, 2000. http://dx.doi.org/10.1145/337292.337588.
Texto completoScheeline, Alexander. "Hardware, software, brainware, noware". En Photonics West '95, editado por Gerald E. Cohn, Jeremy M. Lerner, Kevin J. Liddane, Alexander Scheeline y Steven A. Soper. SPIE, 1995. http://dx.doi.org/10.1117/12.206025.
Texto completoStitt, Greg, Roman Lysecky y Frank Vahid. "Dynamic hardware/software partitioning". En the 40th conference. New York, New York, USA: ACM Press, 2003. http://dx.doi.org/10.1145/775832.775896.
Texto completoHummer, James y Loïc Briand. "When hardware becomes software". En the conference. New York, New York, USA: ACM Press, 1992. http://dx.doi.org/10.1145/143557.144016.
Texto completoInformes sobre el tema "Progettistica hardware e software"
Leson, Joel L. Microcomputer Hardware and Software Management Program. Fort Belvoir, VA: Defense Technical Information Center, febrero de 2001. http://dx.doi.org/10.21236/ada402387.
Texto completoSprinkle, Jonathan y Brandon Eames. Multicore Hardware Experiments in Software Producibility. Fort Belvoir, VA: Defense Technical Information Center, junio de 2009. http://dx.doi.org/10.21236/ada502782.
Texto completoAggarwal, Aneesh. Low Overhead Software/Hardware Mechanisms for Software Assurance and Producibility. Fort Belvoir, VA: Defense Technical Information Center, febrero de 2007. http://dx.doi.org/10.21236/ada464355.
Texto completoLei, Li. Hardware/Software Interface Assurance with Conformance Checking. Portland State University Library, enero de 2000. http://dx.doi.org/10.15760/etd.2320.
Texto completoHopper, G. Future possibilities: Data, hardware, software and people. Office of Scientific and Technical Information (OSTI), enero de 1985. http://dx.doi.org/10.2172/6566336.
Texto completoKoch, Ed, Francis Rubinstein y Kiliccote Sila. Hardware/Software Solution Unifying DALI, IBECS, and BACnet. Office of Scientific and Technical Information (OSTI), diciembre de 2004. http://dx.doi.org/10.2172/878328.
Texto completoFriedman, M. A., P. Y. Tran y P. L. Goddard. Reliability Techniques for Combined Hardware and Software Systems. Fort Belvoir, VA: Defense Technical Information Center, febrero de 1992. http://dx.doi.org/10.21236/ada256347.
Texto completoMinker. Parallellogic Programming and Parallel System Software and Hardware. Fort Belvoir, VA: Defense Technical Information Center, diciembre de 1990. http://dx.doi.org/10.21236/ada239228.
Texto completoLi, Juncao. An Automata-Theoretic Approach to Hardware/Software Co-verification. Portland State University Library, enero de 2000. http://dx.doi.org/10.15760/etd.12.
Texto completoKlymenko, Mykola V. y Andrii M. Striuk. Development of software and hardware complex of GPS-tracking. CEUR Workshop Proceedings, marzo de 2021. http://dx.doi.org/10.31812/123456789/4430.
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