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Literatura académica sobre el tema "Power MOSFETs"

Autor: Grafiati

Publicado: 4 de junio de 2021

Última modificación: 14 de marzo de 2023

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Artículos de revistas sobre el tema "Power MOSFETs"

1

Lichtenwalner, Daniel J., Brett Hull, Vipindas Pala, Edward Van Brunt, Sei-Hyung Ryu, Joe J. Sumakeris, Michael J. O’Loughlin, Albert A. Burk, Scott T. Allen y John W. Palmour. "Performance and Reliability of SiC Power MOSFETs". MRS Advances 1, n.º 2 (2016): 81–89. http://dx.doi.org/10.1557/adv.2015.57.

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ABSTRACTDue to the wide bandgap and other key materials properties of 4H-SiC, SiC MOSFETs offer performance advantages over competing Si-based power devices. For example, SiC can more easily be used to fabricate MOSFETs with very high voltage ratings, and with lower switching losses. Silicon carbide power MOSFET development has progressed rapidly since the market release of Cree’s 1200V 4H-SiC power MOSFET in 2011. This is due to continued advancements in SiC substrate quality, epitaxial growth capabilities, and device processing. For example, high-quality epitaxial growth of thick, low-doped SiC has enabled the fabrication of SiC MOSFETs capable of blocking extremely high voltages (up to 15kV); while dopant control for thin highly-doped epitaxial layers has helped enable low on-resistance 900V SiC MOSFET production. Device design and processing improvements have resulted in lower MOSFET specific on-resistance for each successive device generation. SiC MOSFETs have been shown to have a long device lifetime, based on the results of accelerated lifetime testing, such as high-temperature reverse-bias (HTRB) stress and time-dependent dielectric breakdown (TDDB).

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2

Funaki, Tsuyoshi, Yuki Nakano y Takashi Nakamura. "Comparative Study of SiC MOSFETs in High Voltage Switching Operation". Materials Science Forum 717-720 (mayo de 2012): 1081–84. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1081.

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SiC power device is expected to have high breakdown voltage with low on resistance, which cannot be attainable for conventional Si device. This study evaluates the switching performance of high voltage SiC MOSFETs with comparing to that of conventional Si power MOSFET having equivalent breakdown voltage. To this end, turn-on and turn-off switching operation of MOSFETs are assessed with resistive load for same conduction current density. Though the on resistance of SiC MOSFETs are quite lower than Si MOSFET, especially for trench gate type. But, SiC MOSFETs have larger terminal capacitance. Therefore, SiC MOSFETs show slower switching speed than Si MOSFETs for same current density condition.

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Ejury, Jens. "Advanced Thermal Simulation Model for Power MOSFETs". International Symposium on Microelectronics 2013, n.º 1 (1 de enero de 2013): 000598–603. http://dx.doi.org/10.4071/isom-2013-wa64.

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Modern Power MOSFETs are widely used for high efficiency SMPS applications. Also, they provide very low on-resistance which reduces conduction losses in Oring or eFuse applications. These applications as well as others have transition states in which they drive the MOSFET in linear mode operation during turn-on and turn-off events respectively. The high cell density in modern Power MOSFETs provokes uneven current distribution in linear mode operation which locally stresses certain cell areas more than others. To prevent destruction, the SOA of these MOSFETs has a thermal limit line boundary imposed. With existing L3 MOSFET models it is possible to simulate temperature rise and power loss of the entire MOSFET. However, the local heating effect is not represented in this model. Here, a wrapper is being introduced. It converts a standard L3-model into a model that incorporates a dynamic representation of the entire SOA diagram. The temperature rise follows the hottest cell so that simulations in linear mode become a valid way to predict the highest junction temperature. The limitations of this approach will be outlined.

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4

Prado, Edemar O., Pedro C. Bolsi, Hamiltom C. Sartori y José R. Pinheiro. "An Overview about Si, Superjunction, SiC and GaN Power MOSFET Technologies in Power Electronics Applications". Energies 15, n.º 14 (20 de julio de 2022): 5244. http://dx.doi.org/10.3390/en15145244.

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This work presents a comparative analysis among four power MOSFET technologies: conventional Silicon (Si), Superjunction (SJ), Silicon Carbide (SiC) and Gallium Nitride (GaN), indicating the voltage, current and frequency ranges of the best performance for each technology. For this, a database with 91 power MOSFETs from different manufacturers was built. MOSFET losses are related to individual characteristics of the technology: drain-source on-state resistance, input capacitance, Miller capacitance and internal gate resistance. The total losses are evaluated considering a drain-source voltage of 400 V, power levels from 1 kW to 16 kW (1 A–40 A) and frequencies from 1 kHz to 500 kHz. A methodology for selecting power MOSFETs in power electronics applications is also presented.

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5

Matocha, Kevin, Peter A. Losee, Arun Gowda, Eladio Delgado, Greg Dunne, Richard Beaupre y Ljubisa Stevanovic. "Performance and Reliability of SiC MOSFETs for High-Current Power Modules". Materials Science Forum 645-648 (abril de 2010): 1123–26. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1123.

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We address the two critical challenges that currently limit the applicability of SiC MOSFETs in commercial power conversion systems: high-temperature gate oxide reliability and high total current rating. We demonstrate SiC MOSFETs with predicted gate oxide reliability of >106 hours (100 years) operating at a gate oxide electric field of 4 MV/cm at 250°C. To scale to high total currents, we develop the Power Overlay planar packaging technique to demonstrate SiC MOSFET power modules with total on-resistance as low as 7.5 m. We scale single die SiC MOSFETs to high currents, demonstrating a large area SiC MOSFET (4.5mm x 4.5 mm) with a total on-resistance of 30 m, specific on-resistance of 5 m-cm2 and blocking voltage of 1400V.

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6

Jadli, Utkarsh, Faisal Mohd-Yasin, Hamid Amini Moghadam, Peyush Pande, Mayank Chaturvedi y Sima Dimitrijev. "A Method for Selection of Power MOSFETs to Minimize Power Dissipation". Electronics 10, n.º 17 (3 de septiembre de 2021): 2150. http://dx.doi.org/10.3390/electronics10172150.

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A balance between static and dynamic losses of a power MOSFET is always desirable for accomplishing the maximum efficiency for a specific power converter. The standard semiconductor theory suggests that a minimum power dissipation in a MOSFET can be achieved by selecting a specific device active area. However, for power circuit designers, the active device area is unknown given that only datasheet parameters are available. Hence, in this paper, we propose a simple method, based on semiconductor theory, to select optimum power MOSFET from a family of MOSFETs using only datasheet parameters. By applying this optimization method to the specific power supply circuit under development, power engineers can select the best transistors to yield lowest power losses for the systems under development.

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7

Lichtenwalner, Daniel J., Akin Akturk, James McGarrity, Jim Richmond, Thomas Barbieri, Brett Hull, Dave Grider, Scott Allen y John W. Palmour. "Reliability of SiC Power Devices against Cosmic Ray Neutron Single-Event Burnout". Materials Science Forum 924 (junio de 2018): 559–62. http://dx.doi.org/10.4028/www.scientific.net/msf.924.559.

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High-energy neutrons produced by cosmic ray interactions with our atmosphere are known to cause single-event burnout (SEB) failure in power devices operating at high fields. We have performed accelerated high-energy neutron SEB testing of SiC and Si power devices at the Los Alamos Neutron Science Center (LANCSE). Comparing Wolfspeed SiC MOSFETs having different voltage (900V – 3300V) and current (3.5A – 72A) ratings, we find a universal behavior when scaling failure rates by active area, and scaling drain bias by avalanche voltage. Moreover, diodes and MOSFETs behave similarly, revealing that the SiC drift dominates the failure characteristics for both device types. This universal scaling holds for SiC MOSFETs from other manufacturers as well. The SEB characteristics of Si power IGBT and MOSFET devices show that near their rated voltages failure rates of Si devices can be 10X higher than that of comparable SiC MOSFET devices. Thus, Si devices are more susceptible to SEB failure from voltage overshoot conditions.

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8

Kampitsis, Georgios E., Stavros A. Papathanassiou y Stefanos N. Manias. "Comparative Analysis of the Thermal Stress of Si and SiC MOSFETs during Short Circuits". Materials Science Forum 856 (mayo de 2016): 362–67. http://dx.doi.org/10.4028/www.scientific.net/msf.856.362.

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In this paper, the performance of silicon (Si) and silicon carbide (SiC) power MOSFETs during short circuits is investigated. The response of both semiconductors is examined under hard switch fault and fault under load conditions using a short circuit tester board. In addition, their failure mechanism is recorded and analyzed. Examination results show that the SiC MOSFET fails in the energy limiting mode, due to gate oxide rupture, while the Si MOSFET is destructed during the power limiting mode, at the beginning of the fault. The electro-thermal characterization of these devices is performed through three-dimensional finite element analysis, utilizing the experimentally extracted power dissipation for each transistor. Simulation results confirm the exceptional ruggedness that SiC power MOSFETs exhibit outside their safe operating area.

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Kannan, Ramani, Saranya Krishnamurthy, Chay Che Kiong y Taib B. Ibrahim. "Impact of gamma-ray irradiation on dynamic characteristics of Si and SiC power MOSFETs". International Journal of Electrical and Computer Engineering (IJECE) 9, n.º 2 (1 de abril de 2019): 1453. http://dx.doi.org/10.11591/ijece.v9i2.pp1453-1460.

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Power electronic devices in spacecraft and military applications requires high radiation tolerant. The semiconductor devices face the issue of device degradation due to their sensitivity to radiation. Power MOSFET is one of the primary components of these power electronic devices because of its capabilities of fast switching speed and low power consumption. These abilities are challenged by ionizing radiation which damages the devices by inducing charge built-up in the sensitive oxide layer of power MOSFET. Radiations degrade the oxides in a power MOSFET through Total Ionization Dose effect mechanism that creates defects by generation of excessive electron–hole pairs causing electrical characteristics shifts. This study investigates the impact of gamma ray irradiation on dynamic characteristics of silicon and silicon carbide power MOSFET. The switching speed is limit at the higher doses due to the increase capacitance in power MOSFETs. Thus, the power circuit may operate improper due to the switching speed has changed by increasing or decreasing capacitances in power MOSFETs. These defects are obtained due to the penetration of Cobalt60 gamma ray dose level from 50krad to 600krad. The irradiated devices were evaluated through its shifts in the capacitance-voltage characteristics, results were analyzed and plotted for the both silicon and silicon carbide power MOSFET.

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Bottaro, Enrico, Santi Agatino Rizzo y Nunzio Salerno. "Circuit Models of Power MOSFETs Leading the Way of GaN HEMT Modelling—A Review". Energies 15, n.º 9 (7 de mayo de 2022): 3415. http://dx.doi.org/10.3390/en15093415.

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Gallium nitride high-electron-mobility transistor (GaN HEMT) is a key enabling technology for obtaining high-efficient and compact power electronic systems. At the design stage of a power converter, the proper modelling of the GaN HEMT is essential to benefit from their good features and to account for the limits of the current technology. Circuit models of power MOSFETs have been deeply investigated by academia and industry for a long time. These models are able to emulate the datasheet information, and they are usually provided by device manufacturers as netlists that can be simulated in any kind of SPICE-like software. This paper firstly highlights the similarities and differences between MOSFETs and GaN HEMTs at the datasheet level. According to this analysis, the features of MOSFET circuit models that can be adopted for GaN HEMT modelling are discussed. This task has been accomplished by overviewing the literature on MOSFETs circuit models as well as analysing manufacturers netlists, thus highlighting the models MOSFETs valid or adaptable to GaN HEMTs. The study has revealed show that some models can be adapted for the GaN HEMT devices to emulate static characteristics at room temperature while the MOSFET models of dynamic characteristics can be used for GaN HEMT devices. This study enables the devices modellers to speed up the GaN HEMT modelling thanks to the use of some well-established MOSFET models. In this perspective, some suggestions to develop accurate GaN HEMT models are also provided.

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Tesis sobre el tema "Power MOSFETs"

1

Amberetu, Mathew Atekwana. "Lateral superjunction power MOSFETs". Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ63012.pdf.

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2

Dharmawardana, Kahanawita Gamaethiralalage Padmapani. "High performance power MOSFETs". Thesis, University of Cambridge, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.621963.

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3

Leedham, Robert John. "High frequency switching with power MOSFETs". Thesis, University of Cambridge, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.627468.

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4

Chen, Yuhui. "Resonant Gate Drive Techniques for Power MOSFETs". Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/10099.

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With the use of the simplistic equivalent circuits, loss mechanism in conventional power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) gate drive circuits is analyzed. Resonant gate drive techniques are investigated and a new resonant gate drive circuit is presented. The presented circuit adds minor complexity to conventional gate drivers but reduces the MOSFET gate drive loss very effectively. To further expand its use in driving Half-Bridge MOSFETs, another circuit is proposed in this thesis. The later circuit simplifies the isolation circuitry for the top MOSFET and meanwhile consumes much lower power than conventional gate drivers.
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5

Xiangxiang, Fang. "Characterization and Modeling of SiC Power MOSFETs". The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1354687371.

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6

Liu, Jingjing Michelle. "Strain induced effects on lateral power MOSFETs". [Gainesville, Fla.] : University of Florida, 2009. http://purl.fcla.edu/fcla/etd/UFE0041290.

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7

Zupac, Dragan 1961. "ESD-induced noncatastrophic damage in power MOSFETs". Thesis, The University of Arizona, 1990. http://hdl.handle.net/10150/291470.

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Electrostatic discharge (ESD) may, depending on the energy of the pulse, cause either catastrophic failures or degradation of MOSFETs. Effects of noncatastrophic positive Human-Body Model (HBM) ESD stress at the gate of power MOSFETs are investigated in this work. Noncatastrophic damage is manifested in the form of positive charge trapping in the gate oxide. In p-channel devices used in this study, the charge injection and trapping occur predominantly in the gate oxide areas lying above the p-body region. In p-channel devices used, the charge is injected mainly from the p-drain region. Based on the polarity of the pulse and the regions observed to contribute to charge injection, a model of ESD-induced charge injection from the silicon into the oxide is proposed. Finally, the effects of noncatastrophic ESD events on the radiation response of n-channel power MOSFETs are reported.

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8

DE, GASPERI SERGIO. "Integrated health condition monitoring for power MOSFETs". Doctoral thesis, Università degli Studi di Milano-Bicocca, 2022. http://hdl.handle.net/10281/392351.

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I semiconduttori di potenza hanno un ruolo cruciale nella conversione e distribuzione dell'energia elettrica. I MOSFET di potenza, in particolare, possono essere trovati in una grande varietà di applicazioni, quali elettronica di consumo, settore automotive o nella rete elettrica. Una tecnologia così obiquitaria è naturalmente soggetta a incesstanti sforzi di ottimizzazione dei costi di produzione. La minimizzazione dell'impiego di materiali è il modo più diretto per ottimizzare i costi, ed implica una riduzione dell'area di silicio utilizzata per ogni dispositivo. Questo a sua volta porta ad un aumento delle densità di potenza termica dissipata. Di conseguenza, i MOSFET di potenza devono poter operare sopportando intensi stress termomeccanici, che costituiscono un importante rischio di affidabilità in molti campi di applicazione. Questa tesi incentrata su una tecnologia DMOS verticale, per la quale per la quale la degradazione della metallitazione di potenza è la principale causa di rottura tra quelle legate a stress termomeccanico. Un metodo percorribile per il miglioramento dell'affidabilità dei dispositivi presi in considerazione è l'implementazione di capacità di prognosi delle condizioni di integrità del dispositivo. In questa tesi è proposta un'indagine sperimentale di due metodi di implementazione. Il primo metodo consiste nella realizzazione di una struttura non vitale per il funzionamento del dispositivo di potenza. Tale struttura, come la metallizazione di potenza, si degrada a causa dello stress termomeccanico, che provoca cortocircuiti nella struttura stessa. Il secondo metodo proposto si affida alla misura della temperatura del dispositivo in diversi punti durante un transiente di potenza. La degradazione della metallizazione di potenza porta alla rottura del dispositivo proprio perché induce dei cambiamenti nelle proprietà termiche dello stesso, pertanto, delle misure termiche possono consentire di monitorare i risultati del processo di degradazione. Gli esperimenti hanno parzialmente confermato la validità dei metodi presi in considerazione, ma le forme di implementazione testate non sono applicabili in un contesto industriale. Per entrambi gli esperimenti condotti, sia i limiti di tempo che la necessità di affrontare campi molto diversi tra loro (circuit design, technology development, test engineering, scienze dei materiali) hanno costituito una sfida significativa. L'esperienza acquisita nello sviluppo delle due tecniche ha portato, come risultato, alla definizione di un concept per una terza tecnica, descritta nell'ultimo capitolo della tesi. Concludendo, questa tesi dimostra la possibilità di sviluppare tecniche innovative per la soluzione del problema posto, e i risultati ottenuti pongono le basi per eventuali future indagini, che potrebbero avere maggiore successo nella realizzazione di implementazioni efficaci.
Power semiconductors have a crucial role in conversion and distribution of electric energy. Power MOSFETs, especially, can be found in a large variety of applications, like consumer electronics, automotive or grid applications. Such an ubiquitous technology is indeed subject to unceasing cost-optimization efforts. Minimization of materials usage is the most straightforward way to cost optimization, and it comes together with a decrease in the footprint size of devices. This comes at cost of an increase in power densities, and therfore an increase in heat dissipation per unit area. As a result, during operation, power MOSFETs need to withstand intense thermo-mechanical stress, which is the main reliability concern on many application fields. This thesis is focused on a vertical DMOS technology, for which power metallization degradation is the main stress-related failure cause. A possible way to improve reliability of power MOSFETs is to implement in-situ prognostic health management capabilities: in this thesis, two implementation methods are experimentally investigated. The first method consists of building a non-vital structure that shares the same degradation driving force as power metallization, although the degradation process is different. Thermo-mechanical stress results in the formation of short circuits into the non-vital structure, which are electrically detectable. The second method here proposed relies on local temperature measurements in different spots of the DMOS during power transients. Power metallization degradation leads to failure precisely because it modifies the thermal behavior of the device, therefore, temperature measurements may allow to directly observe the outcome of degradation. Experiments partially validate the investigated health monitoring principles, but the implementation tested so far are not reliable enough for industrial application. For both experiments, time limitations and the need for different actions in very diverse fields (circuit design, technology development, test engineering, materials science) posed a remarkable challenge. As a result, the experience acquired in the development of the two techniques shaped a concept for a third solution, that is only conceptually described in the last part of this thesis. As a conclusion, this thesis demonstrates that innovative solutions to the problem can be developed through an effort on different fields of expertise, and the achieved preliminary results pose a promising outlook for further investigations, which may successfully develop robust and reliable implementations.

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9

Safarjameh, Kourosh 1961. "Fast-neutron-induced resistivity change in power MOSFETs". Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277011.

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Fast neutron irradiation tests were performed to determine the correlation of change of drain-source resistance and neutron fluence for power MOSFETs. The Objectives of the tests were: (1) to detect and measure the degradation of critical MOSFET device parameters as a function of neutron fluence (2) to compare the experimental results and the theoretical model. In general, the drain-source resistance increased from 1 Ohm to 100 Ohm after exposure to fast neutron fluence of 3 x 1014 neut/cm2, and decreased by a factor of five after high temperature annealing.

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10

Fayyaz, Asad. "Performance and robustness characterisation of SiC power MOSFETs". Thesis, University of Nottingham, 2018. http://eprints.nottingham.ac.uk/48937/.

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Over the last few years, significant advancements in the SiC power MOSFET fabrication technology has led to their wide commercial availability from various manufacturers. As a result, they have now transitioned from being a research activity to becoming an industrial reality. SiC power MOSFET technology offers great benefits in the electrical energy conversion domain which have been widely discussed and partially demonstrated. Superior material properties of SiC and the consequent advantages are both later discussed here. For any new device technology to be widely implemented in power electronics applications, it’s crucial to thoroughly investigate and then validate for robustness, reliability and electrical parameter stability requirements set by the industry. This thesis focuses on device characterisation of state-of-the-art SiC power MOSFETs from different manufacturers during short circuit and avalanche breakdown operation modes under a wide range of operating conditions. The functional characterisation of packaged DUTs was thoroughly performed outside of the safe operating area up until failure test conditions to obtain absolute device limitations. For structural characterisation, Infrared thermography on bare die DUTs was also performed with an aim to observe hotspots and/or degradation of the structural features of the device. The experimental results are also complemented by 2D TCAD simulation results in order to get a further insight into the underlying physical mechanisms behind failure during such operation regimes. Moreover, the DUTs were also tested for body diode characterisation with an aim to observe degradation and instability of electrical device parameters which may adversely affect the performance of the overall system. Such investigations are really important and act as a feedback to device manufacturers for further technological improvements in order to overcome the highlighted issues with an aim to bring about advancements in device design to meet the ever-increasing demands of power electronics.

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Libros sobre el tema "Power MOSFETs"

1

(Firm), Harris Semiconductor. Power MOSFETs: Buffered MOSFETs, intelligent discretes. Melbourne, Florida: Harris Semiconductor, 1994.

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2

Korec, Jacek. Low Voltage Power MOSFETs. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9320-5.

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3

Baliga, Jayant. Silicon RF power MOSFETs. Singapore: World Scientific, 2005.

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Silicon RF power MOSFETS. Singapore: World Scientific, 2005.

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5

Amberetu, Mathew Atekwana. Lateral superjunction power MOSFETs. Ottawa: National Library of Canada, 2001.

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6

1945-, Gowar John, ed. Power MOSFETS: Theory and applications. New York: Wiley, 1989.

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7

Corporation, Toshiba. Power MOSFETs: SMD, high-voltage. Tokyo: Toshiba Corporation, 1992.

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8

Groves, N. High speed drive circuits for power MOSFETs. Leatherhead: ERA Technology, 1989.

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9

(Firm), Harris Semiconductor. Power MOSFETS for commercial and high reliability applications. Melbourne, Florida: Harris Semiconductor, 1991.

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10

Korec, Jacek. Low voltage power MOSFETs: Design, performance and applications. New York: Springer, 2011.

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Capítulos de libros sobre el tema "Power MOSFETs"

1

Singh, Ranbir y B. Jayant Baliga. "Power Mosfets". En Cryogenic Operation of Silicon Power Devices, 65–81. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4615-5751-7_6.

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Baliga, B. Jayant. "Power MOSFETs". En Fundamentals of Power Semiconductor Devices, 276–503. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-47314-7_6.

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Baliga, B. Jayant. "Power MOSFETs". En Fundamentals of Power Semiconductor Devices, 283–520. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-93988-9_6.

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Dimitrijev, S., H. B. Harrison, P. Tanner, K. Y. Cheong y J. Han. "Oxidation, MOS Capacitors, and MOSFETs". En SiC Power Materials, 345–73. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-662-09877-6_9.

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Rossi, D. "Power Mosfets Driving Circuits and Protection Techniques". En Smart Power ICs, 173–223. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/978-3-642-61395-1_5.

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Peters, Dethard, Reinhold Schoerner, Peter Friedrichs y Dietrich Stephani. "SiC Power MOSFETs – Status, Trends and Challenges". En Silicon Carbide and Related Materials 2005, 1255–60. Stafa: Trans Tech Publications Ltd., 2006. http://dx.doi.org/10.4028/0-87849-425-1.1255.

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Gudjónsson, G., Fredrik Allerstam, H. Ö. Ólafsson, Per Åke Nilsson, Hans Hjelmgren, Kristoffer Andersson, Einar O. Sveinbjörnsson, Herbert Zirath, T. Rödle y R. Jos. "High Power-Density 4H-SiC RF MOSFETs". En Silicon Carbide and Related Materials 2005, 1277–80. Stafa: Trans Tech Publications Ltd., 2006. http://dx.doi.org/10.4028/0-87849-425-1.1277.

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Nakamura, Takashi, Mineo Miura, Noriaki Kawamoto, Yuki Nakano, Takukazu Otsuka, Keiji Oku-Mura y Akira Kamisawa. "Development of SiC Diodes, Power MOSFETs and Intelligent Power Modules". En Silicon Carbide, 291–319. Weinheim, Germany: Wiley-VCH Verlag GmbH & Co. KGaA, 2011. http://dx.doi.org/10.1002/9783527629077.ch12.

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López, Toni, Reinhold Elferich y Eduard Alarcón. "Model Level 0: Switching Behavior of Power MOSFETs". En Voltage Regulators for Next Generation Microprocessors, 67–132. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7560-7_2.

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Tanimoto, Satoshi, Hideaki Tanaka, Tetsuya Hayashi, Yoshio Shimoida, Masakatsu Hoshi y Teruyoshi Mihara. "High-Reliability ONO Gate Dielectric for Power MOSFETs". En Materials Science Forum, 677–80. Stafa: Trans Tech Publications Ltd., 2005. http://dx.doi.org/10.4028/0-87849-963-6.677.

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Actas de conferencias sobre el tema "Power MOSFETs"

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Ye, Hua y Pradeep Haldar. "Development of Cryogenic Power Modules for Superconducting Hybrid Power Electronic System". En ASME 2008 International Mechanical Engineering Congress and Exposition. ASMEDC, 2008. http://dx.doi.org/10.1115/imece2008-69274.

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This paper presents the developments of high-performance integrated cryogenic power modules, where both driver components and power MOSFETs are integrated in a single package. These modules are designed to be used in liquid nitrogen environment with extreme thermal cycling for the cryogenic power inverters. Compact high-voltage, cryogenic integrated power modules with single power MOSFET that exhibited more than 14x improvement in on-resistance and continuous current-carrying capability exceeding 40A. A multi-power MOSFETs integrated cryogenic power module is then developed in order to further increase the power density and reduce the size and weight of the cryogenic power system. The multi-power MOSFETs module was demonstrated to be able to carry a current above 100A with only a small increase in footprint compared with the single power MOSFET module. At the current level of 100A, the multi-power MOSFETs module has an on-resistance of 5.5mU` at 77K, which is 6 times smaller than that of the single power MOSFET integrated module developed. Two different design approaches taken in the developments of these modules are discussed in this paper.

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Liu, Yong, Howard Allen y Stephen Martin. "Power Stack Die Package Design, Simulation and Reliability Analysis". En ASME 2010 International Mechanical Engineering Congress and Exposition. ASMEDC, 2010. http://dx.doi.org/10.1115/imece2010-40725.

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This paper presents a power stack die package design for a point of load buck converter. The buck converter system in package (SiP) consists of a lower side Mosfet and a high side Mosfet together with an IC controller. Its structure includes a premolded leadframe with an IC controller. The two Mosfets (both low side and higher side) are stacked on the premolded leadfrrame (LF) and IC controller. Solder balls are placed on the leadframe’s exposed lands, and together with the two drains of Mosfets, to form the stacked die power package. The thermal cycling simulations for the solder balls to connect the PCB and solder joints of the two Mosfet die to the leadframe pads are studied. The failure mechanism and reliability analysis of the power package in TMCL test are discussed.

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Kearney, Ian y Hank Sung. "Integrated ESD Robustness through Device Analysis of Ultra-Small Low Voltage Power MOSFETs". En ISTFA 2014. ASM International, 2014. http://dx.doi.org/10.31399/asm.cp.istfa2014p0350.

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Abstract Low voltage power MOSFETs often integrate voltage spike protection and gate oxide ESD protection. The basic concept of complete-static protection for the power MOSFETs is the prevention of static build-up where possible and the quick, reliable removal of existing charges. The power MOSFET gate is equivalent to a low voltage low leakage capacitor. The capacitor plates are formed primarily by the silicon gate and source metallization. The capacitor dielectric is the silicon oxide gate insulation. Smaller devices have less capacitance and require less charge per volt and are therefore more susceptible to ESD than larger MOSFETs. A FemtoFETTM is an ultra-small, low on-resistance MOSFET transistor for space-constrained handheld applications, such as smartphones and tablets. An ESD event, for example, between a fingertip and the communication-port connectors of a cell phone or tablet may cause permanent system damage. Through electrical characterization and global isolation by active photon emission, the authors identify and distinguish ESD failures. Thermographic analysis provided additional insight enabling further separation of ESD failmodes. This paper emphasizes the role of failure analysis in new product development from the create phase through to product ramp. Coupled with device electrical simulation, the analysis observations led to further design enhancement.

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Yining, Liu, Wang Renze, Yang Yapeng, Zhang Jiangang, Wang Ning, Feng Zongyang, Jia Linsheng y Liang Boning. "The Choice of MOSFET Manufacturing Technique Used in Emergency Response Robot". En 2020 International Conference on Nuclear Engineering collocated with the ASME 2020 Power Conference. American Society of Mechanical Engineers, 2020. http://dx.doi.org/10.1115/icone2020-16222.

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Abstract For the aim of helping the development of robots used in Radiological Emergency Planning and Preparedness, the Total Ionizing Dose (TID) effects on the threshold voltage shift (ΔVth) of different kinds of Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) with different geometry and different scaling technology was compared. The different gate width and length dependent between bulk Complementary Metal-Oxide-Semiconductor Transistor (CMOS) process and nanowire (NW) MOSFET as well as higher and lower technology node is noticed. The reason of this difference is explained from the aspects of Radiation Induced Narrow channel effect (RINCE) and Radiation Induced Short channel effect (RISCE). It is found that some studies in recent years have corrected the influence of negative bias temperature instability (NBTI) when considering radiation effects. The TID effects on ΔVth of several kinds of new devices such as MOSFETs with new layout geometry as well as Ge-channel and GaN channel MOSFETs are described which can be investigated more deeply.

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Tack, Marnix. "Energy efficient power MOSFETs". En Technology (ICICDT). IEEE, 2010. http://dx.doi.org/10.1109/icicdt.2010.5510264.

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Kearney, Ian y Stephen Brink. "3D Integrated Power—A Discrete Perspective". En ISTFA 2015. ASM International, 2015. http://dx.doi.org/10.31399/asm.cp.istfa2015p0141.

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Abstract The shift in power conversion and power management applications to thick copper clip technologies and thinner silicon dies enable high-current connections (overcoming limitations of common wire bond) and enhance the heat dissipation properties of System-in-Package solutions. Powerstage innovation integrates enhanced gate drivers with two MOSFETs combining vertical current flow with a lateral power MOSFET. It provides a low on-resistance and requires an extremely low gate charge with industry-standard package outlines - a combination not previously possible with existing silicon platforms. These advancements in both silicon and 3D Multi-Chip- Module packaging complexity present multifaceted challenges to the failure analyst. The various height levels and assembly interfaces can be difficult to deprocess while maintaining all the critical evidence. Further complicating failure isolation within the system is the integration of multiple chips, which can lead to false positives. Most importantly, the discrete MOSFET all too often gets overlooked as just a simple threeterminal device leading to incorrect deductions in determining true root cause. This paper presents the discrete power MOSFET perspective amidst the competing forces of the system-to-board-level failure analysis. It underlines the requirement for diligent analysis at every step and the importance as an analyst to contest the conflicting assumptions of challenging customers. Automatic Test Equipment (ATE) data-logs reported elevated power MOSFET leakage. Initial assumptions believed a MOSFET silicon process issue existed. Through methodical anamnesis and systematic analysis, the true failure was correctly isolated and the power MOSFET vindicated. The authors emphasize the importance of investigating all available evidence, from a macro to micro 3D package perspective, to achieve the bona fide path forward and true root cause.

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Zarebski, Janusz y Rafal Zarebski. "ON-Resistance of Power MOSFETs". En Modern Problems of Radio Engineering, Telecommunications and Computer Science. International Conference, TCSET'2006. IEEE, 2006. http://dx.doi.org/10.1109/tcset.2006.4404476.

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Yamaoka, Masami, Yukio Tsuzuki y Kazunori Kawamoto. "Self-Thermal Protecting Power MOSFETs". En SAE International Congress and Exposition. 400 Commonwealth Drive, Warrendale, PA, United States: SAE International, 1988. http://dx.doi.org/10.4271/880411.

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Tsuzuki, Y., M. Yamaoka y K. Kawamoto. "Self-thermal protecting power MOSFETs". En 1987 IEEE Power Electronics Specialists Conference. IEEE, 1987. http://dx.doi.org/10.1109/pesc.1987.7077160.

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Jiang, W., W. Diao y X. Wang. "Marx generator using power mosfets". En 2009 IEEE Pulsed Power Conference (PPC). IEEE, 2009. http://dx.doi.org/10.1109/ppc.2009.5386282.

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Informes sobre el tema "Power MOSFETs"

1

Offord, Bruce, C. Milligan, H. Jazo y J. Meloling. An Ultra Low Power 180-Degree, 1-Bit Phase Shifter using MOSFETS. Fort Belvoir, VA: Defense Technical Information Center, septiembre de 2009. http://dx.doi.org/10.21236/ada513799.

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Cook, E. Improving Switching Performance of Power MOSFETs Used in High Rep-Rate, Short Pulse, High-Power Pulsers. Office of Scientific and Technical Information (OSTI), septiembre de 2006. http://dx.doi.org/10.2172/896001.

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Cooper, James A. y Jr. Development of SiC Power MOSFETs with Low On-Resistance for Military and Commercial Applications. Fort Belvoir, VA: Defense Technical Information Center, marzo de 2003. http://dx.doi.org/10.21236/ada414680.

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Sbrockey, Nick M., Gary S. Tompa, Michael G. Spencer y Chandra M. V. S. Chandrashekhar. SiC Power MOSFET with Improved Gate Dielectric. Office of Scientific and Technical Information (OSTI), agosto de 2010. http://dx.doi.org/10.2172/1067486.

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Chow, Louis C. y Robert J. Mauriello. Utilizing ISE-TCAD Software to Simulate Power MOSFET Devices Operating at Cryogenic Temperatures. Fort Belvoir, VA: Defense Technical Information Center, abril de 2001. http://dx.doi.org/10.21236/ada387644.

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