Literatura académica sobre el tema "Poly-Si"

Crea una cita precisa en los estilos APA, MLA, Chicago, Harvard y otros

Elija tipo de fuente:

Consulte las listas temáticas de artículos, libros, tesis, actas de conferencias y otras fuentes académicas sobre el tema "Poly-Si".

Junto a cada fuente en la lista de referencias hay un botón "Agregar a la bibliografía". Pulsa este botón, y generaremos automáticamente la referencia bibliográfica para la obra elegida en el estilo de cita que necesites: APA, MLA, Harvard, Vancouver, Chicago, etc.

También puede descargar el texto completo de la publicación académica en formato pdf y leer en línea su resumen siempre que esté disponible en los metadatos.

Artículos de revistas sobre el tema "Poly-Si"

1

Geng, X. H., J. M. Xue, H. C. Ge, H. B. Li, Z. P. Wang, Q. Z. Wang y H. Z. Ren. "Modeling of a-Si/poly-Si and a-Si/poly-Si/poly-Si stacked solar cells". Solar Energy Materials and Solar Cells 75, n.º 3-4 (febrero de 2003): 489–95. http://dx.doi.org/10.1016/s0927-0248(02)00200-3.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
2

Chao, T. S., C. L. Lee y T. F. Lei. "Thickness determination of poly-Si/poly-oxide/poly-Si/SiO2/Si structure by ellipsometer". Electronics Letters 29, n.º 13 (1993): 1157. http://dx.doi.org/10.1049/el:19930774.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
3

Chao, T. S., C. L. Lee, T. F. Lei y Y. T. Yen. "Poly-oxide/poly-Si/SiO2/Si structure for ellipsometry measurement". Electronics Letters 28, n.º 12 (1992): 1144. http://dx.doi.org/10.1049/el:19920722.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
4

Kee-Chan Park, Kwon-Young Choi, Juhn-Suk Yoo y Min-Koo Han. "A new poly-Si thin-film transistor with poly-Si/a-Si double active layer". IEEE Electron Device Letters 21, n.º 10 (octubre de 2000): 488–90. http://dx.doi.org/10.1109/55.870610.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
5

Min, Byung-Hyuk, Cheol-Min Park, Juhn-Suk Yoo y Min-Koo Han. "A new poly-Si TFT to improve surface roughness at poly-oxide/poly-Si interface". Physica Scripta T69 (1 de enero de 1997): 229–32. http://dx.doi.org/10.1088/0031-8949/1997/t69/047.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
6

Maksimov, S. K. "HREM investigations of Si/SiO2/poly-si compositions". Proceedings, annual meeting, Electron Microscopy Society of America 48, n.º 4 (agosto de 1990): 580–81. http://dx.doi.org/10.1017/s0424820100176034.

Texto completo
Resumen
Application of poly-silicon conductive films in integrated circuits promises a number of advantages. In poly-Si technology, however, there are many unsolved problems. In particular, the cause of anomalously high current gains (β) observed by many authors is now being discussed. For their explanation two hypotheses are mostly put forward: according to the first the effect is accounted for by tunneling carriers through the boundary layer of SiO2. according to the second - it is associated with clustering the impurites at the interface. The present paper is an attempt to explain the effect by investigating the structure of the interfaces in Si/SiO2/poly-Si compositions.Layers of poly-Si 0.3μm thick were deposited at 620° on the Si (001) surface prepared by various ways: by etching in HF:H2O/(1:50).using a natural oxide or thermal oxide layers of different thickneses. Then Part of samples was doped with As+ ions with energy of 75 keV at dose 1×1016 cm-2 . The samples were annealed at 850° C during 1 hour; part of them were subjected to a repeat annealing during 30 min at 1000°C.
Los estilos APA, Harvard, Vancouver, ISO, etc.
7

Boehringer, M., J. E. Pillion, V. Erdmann, M. Rygula, K. Winz, P. Brauchle, D. Aquino et al. "Effect of Copper on the Breakthrough Voltage of Poly-Si - Poly-Si Capacitors". Solid State Phenomena 76-77 (enero de 2001): 279–82. http://dx.doi.org/10.4028/www.scientific.net/ssp.76-77.279.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
8

Chang, C. Y., Y. D. Wang, F. C. Tzeng, C. T. Chen y S. J. Wang. "An isolated Al-poly Si-(p)Si-(n+)Si switching device". Solid-State Electronics 29, n.º 7 (julio de 1986): 735–37. http://dx.doi.org/10.1016/0038-1101(86)90159-0.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
9

Lin, Horng-Chih. "Poly-Si Nanowire Device Technology". Nanoscience &Nanotechnology-Asia 1, n.º 2 (1 de diciembre de 2011): 109–22. http://dx.doi.org/10.2174/2210681211101020109.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
10

Lin, Horng-Chih. "Poly-Si Nanowire Device Technology". Nanoscience & Nanotechnology-Asiae 1, n.º 2 (1 de diciembre de 2011): 109–22. http://dx.doi.org/10.2174/2210682011101020109.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.

Tesis sobre el tema "Poly-Si"

1

Salman, Fatma. "EXPERIMENTAL STUDY OF PROFILES OF IMPLANTED SPECIES INTO SEMICONDUCTOR MATERIALS USING SECONDARY ION MASS SPECTROMETRY". Doctoral diss., University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3056.

Texto completo
Resumen
ABSTRACT The study of impurity diffusion in semiconductor hosts is an important field that has both fundamental appeal and practical applications. Ion implantation is a good technique to introduce impurities deep into the semiconductor substrates at relatively low temperature and is not limited by the solubility of the dopants in the host. However ion implantation creates defects and damages to the substrate. Annealing process was used to heal these damages and to activate the dopants. In this study, we introduced several species such as alkali metals (Li, Na, K), alkali earth metals (Be, Ca,), transition metals (Ti, V, Cr, Mn) and other metals (Ga, Ge) into semiconductor substrates using ion implantation. The implantation energy varies form 70 keV to 200 keV and the dosages vary between ~ 1.0x1012 and ~5.0x1015 atoms/cm2. The samples are annealed at different temperatures from 300°C to 1000°C and for different time intervals. The redistribution behaviors of the implanted ions are studied experimentally using secondary ion mass spectrometry (SIMS). We observed some complex distribution behaviors due to the defects created during the process of ion implantation. The diffusivities of some impurities are calculated and compared to previous data. It was found that the diffusivities of implanted impurities is related to the dosages, annealing temperatures and the defects and damages caused by ion implantation. Additionally, as we go from one type of semiconductor to another, the diffusion behavior of the impurities shows a different trend.
Ph.D.
Department of Physics
Sciences
Physics PhD
Los estilos APA, Harvard, Vancouver, ISO, etc.
2

Steffens, Jonathan [Verfasser]. "Dependencies Between poly-Si Composition and Solar Cell Performance of poly-Si/SiOx Passivating Contacts / Jonathan Steffens". Konstanz : KOPS Universität Konstanz, 2020. http://d-nb.info/122106259X/34.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
3

Ullah, Syed Shihab. "Solution Processing Electronics Using Si6 H12 Inks: Poly-Si TFTs and Co-Si MOS Capacitors". Thesis, North Dakota State University, 2011. https://hdl.handle.net/10365/28902.

Texto completo
Resumen
The development of new materials and processes for electronic devices has been driven by the integrated circuit (IC) industry since the dawn of the computer era. After several decades of '"Moore's Law"-type innovation, future miniaturization may be slowed down by materials and processing limitations. By way of comparison, the nascent field of flexible electronics is not driven by the smallest possible circuit dimension, but instead by cost and form-factor where features typical of 1970s CMOS (i.e., channel length - IO ?m) will enable flexible electronic technologies such as RFID, e-paper, photovoltaics and health monitoring devices. In this thesis. cyclohexasilane is proposed and used as a key reagent in solution processing of poly-Si and Co-Si thin films with the former used as the active layer in thin film transistors (TFTs) and the latter as the gate metal in metal-oxide-semiconductor (MOS) capacitors. A work function of 4.356 eV was determined for the Co-Si thin films via capacitance-voltage (C-Y) characterization which differs slightly from that extracted from ultraviolet photoemission spectroscopy (UPS) data (i.e., 4.8 eV). Simulation showed the difference between the C-V and UPS-derived data may be attributed to the existence of 8.3 x 10 (exponent 10) cm-2 interface charge density in the oxide-semiconductor junction. Poly-Si TFTs prepared using Si6 H12-based inks maintained the following electrical attributes: field effect mobility of 0.1 cm2V-1s-1; threshold voltage of 66 V; and, an on/off ratio of 1630. A BSIM3 version 3 NFET model was modified through global parametric extraction procedure to match the transfer characteristics of the fabricated poly-Si TFT. It is anticipated that this model can be utilized for future design simulation for solution-processed poly-Si circuits.
Los estilos APA, Harvard, Vancouver, ISO, etc.
4

Xiong, Zhibin. "Novel scaled-down poly-Si thin-film transistor devices and technologies /". View abstract or full-text, 2005. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202005%20XIONG.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
5

Xu, Guo-Yuan y 許國原. "Poly-oxide, niteridized poly-oxide, amorphous-oxide grown on poly-Si and amorphous-Si-characterization and modelings". Thesis, 1986. http://ndltd.ncl.edu.tw/handle/22052767226291035676.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
6

Huang, Chen-Shuo y 黃震鑠. "A Study of Poly-Si EEPROM". Thesis, 2005. http://ndltd.ncl.edu.tw/handle/69476004541115860739.

Texto completo
Resumen
碩士
國立清華大學
電子工程研究所
93
With the suggestion of SoP to reduce cost and create additional value, the memory which is fabricated on glass substrate is essential for peripheral driver ICs application. We have found and studied a simple twins poly-Si TFTs EEPROM’s to suit the low temperature and simple process on glass substrate. First, we actually fabricated the simple twins poly-Si TFTs EEPROM’s and examined the feasibility of it. We successfully made it and that has good memory characteristic. The memory also exhibited that higher area ratio in coupling cell results in bigger on-current of devices and the better programming/erasing efficiency, the results of experiment were agreed with previous report. And than we present a concept of enhancing this memory cell performance by increasing the overlap of the source/drain and gate in coupling cell and realize it. In addition, the influence of different S/D dopant type in active cell was investigated, the N-type S/D dopant have batter memory efficiency than P-type S/D dopant.
Los estilos APA, Harvard, Vancouver, ISO, etc.
7

Tsao, Kai-Yang y 曹凱揚. "High Strength Si(111) Substrate with Poly-Si/α-Si Sealing Nanotexture for GaN". Thesis, 2017. http://ndltd.ncl.edu.tw/handle/x7thcw.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
8

Chen, Y. C. y 陳盈佳. "Excimer Laser Crystallization of Si Film for Poly-Si TFT Device". Thesis, 2002. http://ndltd.ncl.edu.tw/handle/10160203242103772068.

Texto completo
Resumen
博士
國立交通大學
材料科學與工程系
90
In this study, the crystallization of a-Si with semi-Gaussian excimer laser was investigated. After the single-shot excimer laser process, the poly-Si region showed grains with a wide range of sizes corresponding to the Gaussian distributed laser energy. From the view of laser energy, three crystallization regimes were found on the ELA a-Si films: (1) partial-melting, (2) near-complete-melting and (3) complete-melting regimes. Large super-lateral-grain-growth (SLG) grains were observed in the near-complete-melting regime. The grain size of poly-Si film using multiple shot laser annealing was constrained by the Gaussein distributed laser energy. The large grains were suppressed due to the small grains formed in the first shot. In addition, the influence of substrate temperature on the properties of polysilicon films prepared by excimer laser annealing was studied. As the substrate temperature was elevated, the maximum crystallinity and grain size increased, while the laser energy needed to obtain the maximum crystallinity of polysilicon films decreased. The elevated substrate temperature also changed the surface roughness of polysilicon films. In the partially melting regime, the surface roughness increased with laser energy and substrate temperature. The surface roughness dropped pronouncedly before reaching the super-lateral-grain-growth regime. Further increasing energy to homogeneous nucleation regime did not change much of the surface roughness. Furthermore, the influence of laser energy on the properties of excimer-laser-annealed (ELA) amorphous silicon (a-Si) and as-deposited polycrystalline silicon (poly-Si) films has been studied too. For the ELA poly-Si films, in the low energy region, the crystallinity decreased with the energy. After reaching the minimum, it increased to the maximum, and then dropped down. No SLG grains were found in the near-complete-melting regime. The largest grains were observed in the partial-melting regime. The largest grain size (100 nm) of ELA poly-Si was less than that of ELA a-Si (130 nm). Finally, the effects of energy on the microstructure of amorphous silicon (a-Si) films annealed by two-step laser process were systematically investigated. For the low-crystallinity / small-grain films, which were formed after the first low-energy laser crystallization, the grain size decreased and then increased with the energy of second laser annealing. In contrast, for the high-crystallinity films, i.e. SLG-grain films, the grain size monotonously decreased with second laser energy increased. Two-step laser annealed poly-Si films revealed that fine grains were formed and extruded at the grain boundary after the second high-energy laser annealing. High performance poly-Si TFTs can be fabricated from the poly-Si films crystallized by low-energy annealing followed by second high-energy laser annealing. When the results were compared, the poly-Si TFT using the poly-Si film crystallized by single high-energy laser annealing showed poorer mobility and subthreshold swing.
Los estilos APA, Harvard, Vancouver, ISO, etc.
9

羅傑. "Hybrid Logic/Resistive-switching Poly-Si Thin". Thesis, 2011. http://ndltd.ncl.edu.tw/handle/64642943623743268165.

Texto completo
Resumen
碩士
國立交通大學
電子研究所
100
A hybrid device combined a resistive switching (RS) memory and a logic transistor is proposed in this thesis. The hafnium oxide (HfO2) is not only the high-κ gate dielectric of the transistor but also the resistive switching layer of the RRAM, and the nickel metal gate also acts like a top electrode in a traditional MIM or MIS which is the most common structure in the previous RRAM paper . We first demonstrated a one-bit RS operation by applying a swept voltage on either the gate or drain to trigger the RS. A large amount of VT shift after the RS operation was found when we applied voltage on the gate. On the other hand, the VT shift is negligible when we swept the drain voltage with source grounded during the set/reset process. With the help of the constant voltage stress experiment, we realized that the reason caused the considerable VT shift after resistive switching operation was the charge trapping and wearout attributed to the high voltage applied during the set/reset process, which might induce F-N tunneling. iii Finally, we realized a two-bit-per cell operation mode in our structure with almost negligible VT shift after RS for the first time, which indicated that a new type of high-density memory using the resistive switching mechanism in a traditional transistor structure is possible.
Los estilos APA, Harvard, Vancouver, ISO, etc.
10

Fang, Wei-nan y 方偉南. "2-stage Hydrogenation of Poly-Si TFTs". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/89456485798733398689.

Texto completo
Resumen
碩士
大同大學
光電工程研究所
98
In this research, a parallel-plate plasma reactor(PECVD) is used to hydrogenate polysilicon thin-film transistors(TFT’s). And we find that the H+ and H have different diffusing length at different substrate temperature. Hence, we propose a new theory named 『2-stage hydrogenation』and success to improve the poly-Si TFT’s by 『2-stage hydrogenation』.Vth has decreased 42%﹐SS has reduced 17.5%, mobility has increased 27%, and Ids on/off ratio has induced 38%.
Los estilos APA, Harvard, Vancouver, ISO, etc.

Capítulos de libros sobre el tema "Poly-Si"

1

Brotherton, S. D. "Poly-Si TFT Performance". En Introduction to Thin Film Transistors, 253–300. Heidelberg: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-00002-2_8.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
2

Ishihara, Ryoichi. "Poly-Si TFT Structures". En Thin Film Transistors, 670–700. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_15.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
3

Choi, Byong-Deok, Inhwan Lee y Oh-Kyong Kwon. "Poly-Si TFT Drivers". En Thin Film Transistors, 885–949. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_22.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
4

Brotherton, S. D. "Poly-Si TFT Technology and Architecture". En Introduction to Thin Film Transistors, 185–251. Heidelberg: Springer International Publishing, 2013. http://dx.doi.org/10.1007/978-3-319-00002-2_7.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
5

Uchikoga, Shuichi. "Doping Techniques for Poly-Si TFTs". En Thin Film Transistors, 818–30. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_19.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
6

Uchikoga, Shuichi. "Gate Insulators for Poly-Si TFTs". En Thin Film Transistors, 832–47. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_20.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
7

Bonnaud, Olivier, Tayeb Mohammed-Brahim y Dieter G. Ast. "Poly-Si Thin Film and Substrate Materials". En Thin Film Transistors, 533–618. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_13.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
8

Sameshima, Toshiyuki. "Poly-Si TFTs by Laser Crystallization Methods". En Thin Film Transistors, 701–44. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_16.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
9

Jang, Jin. "Poly-Si TFTs by Direct Deposition Methods". En Thin Film Transistors, 799–816. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_18.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
10

Kuo, Yue. "Poly-Si TFT for non-LCD Applications". En Thin Film Transistors, 989–1021. Boston, MA: Springer US, 2004. http://dx.doi.org/10.1007/978-1-4615-0397-2_24.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.

Actas de conferencias sobre el tema "Poly-Si"

1

Hamada, K., S. Saito, K. Sera, F. Okumura, F. Uesugi y I. Nishiyama. "Improvement of Poly-Si TFT Characteristics by Hydrogenation at SiO2/Poly-Si Interfaces, Characterized by TDS Measurement of Deuterium Terminated Poly-Si". En 1994 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 1994. http://dx.doi.org/10.7567/ssdm.1994.a-3-1.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
2

Kaneko, A., S. Inumiya, K. Sekine, M. Sato, Y. Kamimuta, K. Eguchi y Y. Tsunashima. "Flatband Voltage Shift Caused by Dopants Diffused from Poly-Si Gate Electrode in Poly-Si/HfSiO/SiO2/Si". En 2003 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2003. http://dx.doi.org/10.7567/ssdm.2003.c-2-1.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
3

Tung-Ming Pan, Chih-Jen Chang, Ching-Lin Chan, Sheng-Han Su y Wu-Ching Lin. "CF4 plasma treated poly-Si film by PECVD for high-k PrTiO3 poly-Si TFTs". En 2009 International Semiconductor Device Research Symposium (ISDRS 2009). IEEE, 2009. http://dx.doi.org/10.1109/isdrs.2009.5378022.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
4

Hara, A., K. Kondo y T. Sato. "Monolithic Integration of Ni-SPC Poly-Si TFTs and Lateral Large-grained Poly-Si TFTs". En 2010 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2010. http://dx.doi.org/10.7567/ssdm.2010.p-9-11.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
5

Feldmann, Frank, Christian Reichel, Ralph Muller y Martin Hermle. "Si solar cells with top/rear poly-Si contacts". En 2016 IEEE 43rd Photovoltaic Specialists Conference (PVSC). IEEE, 2016. http://dx.doi.org/10.1109/pvsc.2016.7750076.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
6

Syu, Hong-Jhang, Shu-Chia Shiu y Ching-Fuh Lin. "Si/silicon nanowire/poly(3,4-ethylenedioxythiophene): poly(styrenesulfonate) heterojunction solar cells". En SPIE Solar Energy + Technology, editado por Loucas Tsakalakos. SPIE, 2011. http://dx.doi.org/10.1117/12.893353.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
7

JOHANSEN, JARLE ANDRE, HALLVAR FIGENSCHAU, XUYUAN CHEN, ARTHUR VAN RHEENEN y CORA SALM. "LOW FREQUENCY NOISE IN POLY-SI- AND POLY-SIGE-GATED MOSFETS". En Proceedings of the 16th International Conference. WORLD SCIENTIFIC, 2001. http://dx.doi.org/10.1142/9789812811165_0036.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
8

Ito, Kazumasa, J. Togawa, T. Yonezaki, M. Hashimoto, Michio Ishikawa y Y. Ota. "Low-temperature poly-Si TFT mass production system: CMD-450 poly". En Electronic Imaging '97, editado por Tolis Voutsas y Tsu-Jae King. SPIE, 1997. http://dx.doi.org/10.1117/12.270296.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
9

Santbergen, Rudi, Guangtao Yang, Paul Procel, Gianluca Limodio, Arthur Weeber, Olindo Isabella y Miro Zeman. "Optical Analysis of Poly-Si and Poly-SiOx Carrier-Selective Passivating Contacts for c-Si Solar Cells". En Optical Nanostructures and Advanced Materials for Photovoltaics. Washington, D.C.: OSA, 2017. http://dx.doi.org/10.1364/pv.2017.pw3a.5.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
10

Hayashi, T., Y. Nishida, S. Sakashita, M. Mizutani, S. Yamanari, M. Higashi, T. Kawahara et al. "Cost Worthy and High Performance LSTP CMIS; Poly-Si/HfSiON nMIS and Poly-Si/TiN/HfSiON pMIS". En 2006 International Electron Devices Meeting. IEEE, 2006. http://dx.doi.org/10.1109/iedm.2006.347009.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.

Informes sobre el tema "Poly-Si"

1

Atwater, H. A. Low-Temperature, High Throughput Process for Thin, Large-Grained Poly Si: Final Technical Report, 24 May 1999--25 July 2003. Office of Scientific and Technical Information (OSTI), septiembre de 2003. http://dx.doi.org/10.2172/15004719.

Texto completo
Los estilos APA, Harvard, Vancouver, ISO, etc.
Ofrecemos descuentos en todos los planes premium para autores cuyas obras están incluidas en selecciones literarias temáticas. ¡Contáctenos para obtener un código promocional único!

Pasar a la bibliografía