Bibliografías temáticas / Pipeline datapath

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Literatura académica sobre el tema "Pipeline datapath"

Autor: Grafiati
Publicado: 25 de mayo de 2024
Última modificación: 31 de julio de 2025

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Artículos de revistas sobre el tema "Pipeline datapath"

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D.PREETHI, G.KEERTHANA K.RESHMA Mr.A.RAJA. "ENGINEERING DESIGN OF RECONFIGURABLE PIPELINED DATAPATH." Journal For Innovative Development in Pharmaceutical and Technical Science 2, no. 12 (2019): 26–29. https://doi.org/10.5281/zenodo.3600025.

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Configurable processing has caught the creative mind of numerous draftsmen who need the exhibition of use explicit equipment joined with the re programmability of universally useful PCs. Sadly, Configurable processing has had rather constrained achievement generally on the grounds that the FPGAs on which they are constructed are more fit to executing arbitrary rationale than registering assignments. This paper presents RaPiD, another coarse-grained FPGA engineering that is enhanced for exceptionally monotonous, calculation escalated errands. Extremely profound application-explicit calculation
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Ravikumar, C. P., and V. Saxena. "TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis." VLSI Design 5, no. 1 (1996): 77–87. http://dx.doi.org/10.1155/1996/65320.

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In this paper, we describe TOGAPS, a Testability-Oriented Genetic Algorithm for Pipeline Synthesis. The input to TOGAPS is an unscheduled data flow graph along with a specification of the desired pipeline latency. TOGAPS generates a register-level description of a datapath which is near-optimal in terms of area, meets the latency requirement, and is highly testable. Genetic search is employed to explore a 3-D search space, the three dimensions being the chip area, average latency, and the testability of the datapath. Testability of a design is evaluated by counting the number of self-loops in
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Kirat, Pal Singh, and Dod Shiwani. "Performance Improvement in MIPS Pipeline Processor based on FPGA." International Journal of Engineering Technology, Management and Applied Sciences 4, no. 1 (2016): 57–64. https://doi.org/10.5281/zenodo.48482.

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The paper describes the design and synthesis of a basic 5 stage pipelined MIPS-32 processor for finding the longer path delay using different process technologies. The large propagation delay or critical path within the circuit and improving the hardware which causes delay is a standard method for increasing the performance. The organization of pipeline stages in such a way that pipeline can be clocked at a high frequency. The design has been synthesized at different process technologies targeting using Spartan3, Spartan6, Virtex4, Virtex5 and Virtex6 devices. The synthesis report indicates th
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Kirat, Pal Singh, and Kumar Dilip. "Performance Evaluation of Low Power MIPS Crypto Processor based on Cryptography Algorithms." International Journal of Engineering Research and Applications 2, no. 3 (2012): 1625–34. https://doi.org/10.5281/zenodo.33251.

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This paper presents the design and implementation of low power 32-bit encrypted and decrypted MIPS processor for Data Encryption Standard (DES), Triple DES, Advanced Encryption Standard (AES) based on MIPS pipeline architecture. The organization of pipeline stages has been done in such a way that pipeline can be clocked at high frequency. Encryption and Decryption blocks of three standard cryptography algorithms on MIPS processor and dependency among themselves are explained in detail with the help of a block diagram. Clock gating technique is used to reduce the power consumption in MIPS crypt
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Kingyens, Jeffrey, and J. Gregory Steffan. "The Potential for a GPU-Like Overlay Architecture for FPGAs." International Journal of Reconfigurable Computing 2011 (2011): 1–15. http://dx.doi.org/10.1155/2011/514581.

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We propose a soft processor programming model and architecture inspired by graphics processing units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and pipelinable computation. In particular, our soft processor architecture exploits multithreading, vector operations, and predication to supply a floating-point pipeline of 64 stages via hardware support for up to 256 concurrent thread contexts. The key new contributions of our architecture are mechanisms for managing threads and register files that maximize data-level and instruction-level parallelism while overc
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Kirat, Pal Singh, and Parmar Shivani. "Vhdl Implementation of A Mips-32 Pipeline Processor." International Journal of Applied Engineering Research 7, no. 11 (2012): 1952–56. https://doi.org/10.5281/zenodo.33247.

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This paper presents the design and implement a basic five stage pipelined MIPS-32 CPU. Particular attention will be paid to the reduction of clock cycles for lower instruction latency as well as taking advantage of high-speed components in an attempt to reach a clock speed of at least 100 MHz. The final results allowed the CPU to be run at over 200 MHz with a very reasonable chip area of around 900,000nm2.
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Gaurav Yadav. "Efficient SIMD computations on FPGA: Architectures, design techniques, and applications." World Journal of Advanced Research and Reviews 26, no. 1 (2025): 197–209. https://doi.org/10.30574/wjarr.2025.26.1.1056.

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Field-Programmable Gate Arrays (FPGAs) provide a flexible and efficient platform for implementing Single Instruction, Multiple Data (SIMD) computations, offering advantages over traditional CPUs and GPUs through customizable architectures. This article explores the design considerations, optimization techniques, and practical applications of SIMD operations on FPGAs. We examine how vector processing units, specialized memory organizations, and interconnect architectures can be tailored to application requirements, while investigating methods for datapath optimization, memory access enhancement
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Lee, Y. H., M. Khalil-Hani, and M. N. Marsono. "An FPGA-Based Quantum Computing Emulation Framework Based on Serial-Parallel Architecture." International Journal of Reconfigurable Computing 2016 (2016): 1–18. http://dx.doi.org/10.1155/2016/5718124.

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Hardware emulation of quantum systems can mimic more efficiently the parallel behaviour of quantum computations, thus allowing higher processing speed-up than software simulations. In this paper, an efficient hardware emulation method that employs a serial-parallel hardware architecture targeted for field programmable gate array (FPGA) is proposed. Quantum Fourier transform and Grover’s search are chosen as case studies in this work since they are the core of many useful quantum algorithms. Experimental work shows that, with the proposed emulation architecture, a linear reduction in resource u
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Kashima, Ryota, Ikki Nagaoka, Masamitsu Tanaka, Taro Yamashita, and Akira Fujimaki. "64-GHz Datapath Demonstration for Bit-Parallel SFQ Microprocessors Based on a Gate-Level-Pipeline Structure." IEEE Transactions on Applied Superconductivity 31, no. 5 (2021): 1–6. http://dx.doi.org/10.1109/tasc.2021.3061353.

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Sergiyenko, Anatoliy, and Ivan Mozghovyi. "Method for Mapping Cyclo-Dynamic Dataflow Into Pipelined Datapath." Information, Computing and Intelligent systems, no. 4 (October 2, 2024): 4–15. http://dx.doi.org/10.20535/2786-8729.4.2024.304965.

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An overview of high-level synthesis (HLS) systems for designing pipelined datapaths is presented in the paper. The goal is to explore methods of mapping algorithms to the pipelined datapaths implementing the cyclic data flow graphs with dynamic schedules. The cyclo-dynamic dataflow (CDDF) is selected as the very expressive model for describing a wide domain of the dataflow algorithms. CDDF is distinguished in that, the algorithm period depends on the calculated data and has a dynamic schedule. A set of mapping conditions is formulated that provide the deadlock-free schedule of CDDF when it is
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Tesis sobre el tema "Pipeline datapath"

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Cronquist, Darren C. "Reconfigurable pipelined datapaths /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6988.

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Ait, Bensaid Samira. "Formal Semantics of Hardware Compilation Framework." Electronic Thesis or Diss., université Paris-Saclay, 2023. http://www.theses.fr/2023UPASG085.

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Les analyses statiques de pire temps d’exécution sont utilisées pour garantir les délais requis pour les systèmes critiques. Afin d’estimer des bornes précises sur ces temps d’exécution, ces analyses temporelles nécessitent des considérations sur la (micro)- architecture. Habituellement, ces modèles de micro-architecture sont construits à la main à partir des manuels des processeurs. Cependant, les initiatives du matériel libre et les langages de description de matériel de haut niveau (HCLs), permettent de réaborder la problématique de la génération automatique de ces modèles de micro-architec
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Pasca, Bogdan Mihai. "Calcul flottant haute performance sur circuits reconfigurables." Phd thesis, Ecole normale supérieure de lyon - ENS LYON, 2011. http://tel.archives-ouvertes.fr/tel-00654121.

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De plus en plus de constructeurs proposent des accélérateurs de calculs à base de circuits reconfigurables FPGA, cette technologie présentant bien plus de souplesse que le microprocesseur. Valoriser cette flexibilité dans le domaine de l'accélération de calcul flottant en utilisant les langages de description de circuits classiques (VHDL ou Verilog) reste toutefois très difficile, voire impossible parfois. Cette thèse a contribué au développement du logiciel FloPoCo, qui offre aux utilisateurs familiers avec VHDL un cadre C++ de description d'opérateurs arithmétiques génériques adapté au calcu
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Lu, Chin-Te, and 呂進德. "Area-Efficient Design and Implementation of Deep-Pipeline Latency Datapath." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/22100268830966382822.

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碩士<br>國立交通大學<br>電子工程系所<br>97<br>Datapath is primarily the most critical element that affects performance. The allocations and design of datapath depends various application requirements. General speaking, for high-performance processors like Intel’s Pentium Processors, IBM’s Cell Processors and so on, the designers extremely rise up operating frequency by board VLSI techniques. On the contrary, such as lightweight applications in the embedded system, the goal of datapath design is to seek low-power, small chip area and so on. The instruction set architecture (ISA) has different ways of impleme
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Lin, Sheng-Hsun, and 林聖勳. "A Single Pipeline Datapath Design for Joinable Narrow-operand Operations." Thesis, 2006. http://ndltd.ncl.edu.tw/handle/64738928061451413217.

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碩士<br>國立交通大學<br>資訊科學與工程研究所<br>94<br>Most general-purpose processors and embedded processors have 32-bit word widths or wider. However, integer operations rarely need the full 32-bit dynamic range of the datapath. If we partition the operand bus, result bus, and ALU into several blocks, the datapath could perform more than one operation in parallel. In this thesis, mechanisms to join two narrow-operand operations together to share a single datapath are proposed. We proposed one novel ALU-sharing scheme by turning around operation-block ordering. Efficient designs to merge operands to share buse
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Vlad, Ciubotariu. "Automatic Datapath Abstraction Of Pipelined Circuits." Thesis, 2011. http://hdl.handle.net/10012/5804.

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Pipelined circuits operate as an assembly line that starts processing new instructions while older ones continue execution. Control properties specify the correct behaviour of the pipeline with respect to how it handles the concurrency between instructions. Control properties stand out as one of the most challenging aspects of pipelined circuit verification. Their verification depends on the datapath and memories, which in practice account for the largest part of the state space of the circuit. To alleviate the state explosion problem, abstraction of memories and datapath becomes mandatory. Th
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Hsiao, Pi-Chen, and 蕭丕承. "Efficient Datapath Design for Clustered & Pipelined VLIW DSP Processors." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/24419684455805579987.

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碩士<br>國立交通大學<br>電子工程系所<br>94<br>Most DSP applications feature a high degree of data-level and instruction-level parallelism, which enables efficient datapath design with clustering and deep pipelining. However, the ad-hoc data forwarding and inter-cluster communications in most processors significantly compensate the advantages. This thesis presents analytical formulae which are based on cell-based implementation with flip-flops and multiplexers to analyze the complexity of forwarding unit and inter-cluster communication mechanisms. We also propose a complexity-aware data forwarding architectu
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Libros sobre el tema "Pipeline datapath"

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Tamás, Visegrády, and Jankovits István, eds. High level synthesis of pipelined datapaths. Wiley, 2001.

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Péter Arató, Tamás Visegrády, and István Jankovits. High Level Synthesis of Pipelined Datapaths. Wiley, 2001.

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Capítulos de libros sobre el tema "Pipeline datapath"

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Ebeling, Carl, Darren C. Cronquist, and Paul Franklin. "RaPiD — Reconfigurable pipelined datapath." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 1996. http://dx.doi.org/10.1007/3-540-61730-2_13.

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Actas de conferencias sobre el tema "Pipeline datapath"

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Nurvitadhi, Eriko, James C. Hoe, Shih-Lien L. Lu, and Timothy Kam. "Automatic multithreaded pipeline synthesis from transactional datapath specifications." In the 47th Design Automation Conference. ACM Press, 2010. http://dx.doi.org/10.1145/1837274.1837356.

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Asato, C., C. Ditzen, and S. Dholakia. "A datapath multiplier with automatic insertion of pipeline stages." In 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56815.

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Isshiki, Tsuyoshi, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, and Hiroaki Kunieda. "A new FPGA architecture for high-performance bit-serial pipeline datapath (abstract)." In the 1998 ACM/SIGDA sixth international symposium. ACM Press, 1998. http://dx.doi.org/10.1145/275107.275147.

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Istoan, Matei, and Florent de Dinechin. "Automating the pipeline of arithmetic datapaths." In 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2017. http://dx.doi.org/10.23919/date.2017.7927080.

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Kikkeri, N., and P. M. Seidel. "Formal co-verification of pipelined datapaths." In 48th Midwest Symposium on Circuits and Systems, 2005. IEEE, 2005. http://dx.doi.org/10.1109/mwscas.2005.1594050.

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Cronquist, D. C., C. Fisher, M. Figueroa, P. Franklin, and C. Ebeling. "Architecture design of reconfigurable pipelined datapaths." In Proceedings 20th Anniversary Conference on Advanced Research in VLSI. IEEE, 1999. http://dx.doi.org/10.1109/arvlsi.1999.756035.

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Sergiyenko, Anatoliy, Anastasia Serhienko, and Vitaliy Romankevich. "Genetic Programming of Pipelined Datapaths for FPGA." In 2020 IEEE 40th International Conference on Electronics and Nanotechnology (ELNANO). IEEE, 2020. http://dx.doi.org/10.1109/elnano50318.2020.9088773.

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Hanoun, Abdulrahman, Henning Manteuffel, F. Mayer-Lindenberg, and Wjatscheslaw Galjan. "Architecture of a Pipelined Datapath Coarse-Grain Reconfigurable Coprocessor Array." In 2007 IEEE International Conference on Signal Processing and Communications. IEEE, 2007. http://dx.doi.org/10.1109/icspc.2007.4728448.

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Passaretti, Daniele, and Thilo Pionteck. "Configurable Pipelined Datapath for Data Acquisition in Interventional Computed Tomography." In 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2021. http://dx.doi.org/10.1109/fccm51124.2021.00044.

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McGraw, Robert, James H. Aylor, and Robert H. Klenke. "A top-down design environment for developing pipelined datapaths." In the 35th annual conference. ACM Press, 1998. http://dx.doi.org/10.1145/277044.277105.

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