Literatura académica sobre el tema "Non-Volatile Main Memory (NVMM)"

In high-performance computing (HPC), data and metadata are stored on special server nodes and client applications access the servers’ data and metadata through a network, which induces network latencies and resource contention. These server nodes are typically equipped with (slow) magnetic disks, while the client nodes store temporary data on fast SSDs or even on non-volatile main memory (NVMM). Therefore, the full potential of parallel file systems can only be reached if fast client side storage devices are included into the overall storage architecture. In this article, we propose an NVMM-based hierarchical persistent client cache for the Lustre file system (NVMM-LPCC for short). NVMM-LPCC implements two caching modes: a read and write mode (RW-NVMM-LPCC for short) and a read only mode (RO-NVMM-LPCC for short). NVMM-LPCC integrates with the Lustre Hierarchical Storage Management (HSM) solution and the Lustre layout lock mechanism to provide consistent persistent caching services for I/O applications running on client nodes, meanwhile maintaining a global unified namespace of the entire Lustre file system. The evaluation results presented in this article show that NVMM-LPCC can increase the average read throughput by up to 35.80 times and the average write throughput by up to 9.83 times compared with the native Lustre system, while providing excellent scalability.

The performance of mobile devices such as smartphones and tablets has been rapidly improving in recent years. However, these improvements have been seriously affecting power consumption. One of the greatest challenges is to achieve efficient power management for battery-equipped mobile devices. To solve this problem, the authors focus on the emerging non-volatile memory (NVM), which has been receiving increasing attention in recent years. Since its performance is comparable with that of DRAM, it is possible to replace the main memory with NVM, thereby reducing power consumption. However, the price and capacity of NVM are problematic. Therefore, the authors provide a large memory space without performance degradation by combining NVM with other memory devices. In this study, they propose a design for non-volatile main memory systems that use DRAM as a swap space. This enables both high performance and energy efficient memory management through dynamic power management in NVM and DRAM.

The Non-Volatile Memory (NVM), such as PRAM or STT-MRAM, is often adopted as the main memory in portable embedded systems. The non-volatility triggers a security issue against physical attacks, which is a vulnerability caused by memory extraction and snapshots. However, simply encrypting the NVM degrades the performance of the memory (high energy consumption, short lifetime), since typical encryption causes an avalanche effect while most NVMs suffer from the memory-write operation. In this paper, we propose NVM-shelf: Secure Hybrid Encryption with Less Flip (shelf) for Non-Volatile Memory (NVM), which is hybrid encryption to reduce the flip penalty. The main idea is that a stream cipher, such as block cipher CTR mode, is flip-tolerant when the keystream is reused. By modifying the CTR mode in AES block cipher, we let the keystream updated in a short period and reuse the keystream to achieve flip reduction while maintaining security against physical attacks. Since the CTR mode requires additional storage for the nonce, we classify write-intensive cache blocks and apply our CTR mode to the write-intensive blocks and apply the ECB mode for the rest of the blocks. To extend the cache-based NVM-shelf implementation toward SPM-based systems, we also propose an efficient compiler for SA-SPM: Security-Aware Scratch Pad Memory, which ensures the security of main memories in SPM-based embedded systems. Our compiler is the first approach to support full encryption of memory regions (i.e., stack, heap, code, and static variables) in an SPM-based system. By integrating the NVM-shelf framework to the SA-SPM compiler, we obtain the NVM-shelf implementation for both cache-based and SPM-based systems. The cache-based experiment shows that the NVM-shelf achieves encryption flip penalty less than 3%, and the SPM-based experiment shows that the NVM-shelf reduces the flip penalty by 31.8% compared to the whole encryption.

Several promising non-volatile memories (NVMs) such as magnetic RAM (MRAM), spin-transfer torque RAM (STTRAM), ferroelectric RAM (FeRAM), resistive RAM (RRAM), and phase-change memory (PCM) are being investigated to keep the static leakage within a tolerable limit. These new technologies offer high density and consume zero leakage power and can bridge the gap between processor and memory. The desirable properties of emerging NVMs make them suitable candidates for several applications including replacement of conventional memories. However, their unique characteristics introduce new data privacy and security issues. Some of them are already available in the market as discrete chips or a part of full system implementation. They are considered to become ubiquitous in future computing devices. Therefore, it is important to ensure their security/privacy issues. Note that these NVMs can be considered for cache, main memory, or storage application. They are also suitable to implement in-memory computation which increases system throughput and eliminates von Neumann bottleneck. Compute-capable NVMs impose new security and privacy challenges that are fundamentally different than their storage counterpart. This work identifies NVM vulnerabilities and attack vectors originating from the device level all the way to circuits and systems, considering both storage and compute applications. We also summarize the circuit/system-level countermeasures to make the NVMs robust against security and privacy issues.

During the recent decades, non-volatile memory (NVM) has been anticipated to scale up the main memory size, improve the performance of applications, and reduce the speed gap between main memory and storage devices, while supporting persistent storage to cope with power outages. However, to fit NVM, all existing DRAM-based applications have to be rewritten by developers. Therefore, the developer must have a good understanding of targeted application codes, so as to manually distinguish and store data fit for NVM. In order to intelligently facilitate NVM deployment for existing legacy applications, we propose a universal heterogeneous cache hierarchy which is able to automatically select and store the appropriate data of applications for non-volatile memory (UHNVM), without compulsory code understanding. In this article, a program context (PC) technique is proposed in the user space to help UHNVM to classify data. Comparing to the conventional hot or cold files categories, the PC technique can categorize application data in a fine-grained manner, enabling us to store them either in NVM or SSDs efficiently for better performance. Our experimental results using a real Optane dual-inline-memory-module (DIMM) card show that our new heterogeneous architecture reduces elapsed times by about 11% compared to the conventional kernel memory configuration without NVM.

In the big data era, a huge number of services has placed a fast-growing demand on the capacity of DRAM-based main memory. However, due to the high hardware cost and serious leakage power/energy consumption, the growth rate of DRAM capacity cannot meet the increased rate of the required main memory space when the energy or hardware cost is a critical concern. To tackle this issue, hybrid main-memory devices/modules have been proposed to replace the pure DRAM main memory with a hybrid main memory module that provides a large main memory space by integrating a small-sized DRAM and a large-sized non-volatile memory (NVM) into the same memory module. Although NVMs have high-density and low-cost features, they suffer from the low read/write performance and low endurance issue, compared to DRAM. Thus, inside the hybrid main-memory module, it also includes a memory management design to use DRAM as the cache of NVMs to enhance its performance and lifetime. However, it also introduces new design challenges in both the OS and the memory module. In this work, we rethink the interactivity of OS and hybrid main-memory module, and propose a cross-layer cache design that (1) utilizes the information from the operating system to optimize the hit ratio of the DRAM cache inside the memory module, and (2) takes advantage of the bulk-size (or block-based) read/write feature of NVM to minimize the time overhead on the data movement between DRAM and NVM. At the same time, this cross-layer cache design is very lightweight and only introduces limited runtime management overheads. A series of experiments was conducted to evaluate the effectiveness of the proposed cross-layer cache design. The results show that the proposed design could improve access performance for up to 88%, compared to the investigated well-known page replacement algorithms.

The development of the semiconductor industry through the CMOS technology has been possible thanks to the unique properties of the silicon and silicon dioxide material. Nevertheless the continuous scaling of the device dimension and the increase of the integration level, i.e. the capability to follow for more than 20 years the so-called Moore’s law, has been enabled not only by the Si-SiO2 system, but also by the use of other materials. The introduction of new materials every generation has allowed the integration of sub-micron and now of nanometer scale devices: different types of dielectrics, like Si3N4 or doped-SiO2, to form spacer, barrier and separation layers; conductive films, like WSi2, TiSi2, CoSi2 and NiSi2, to build low resistive gates; metals, like W, Ti, TiN, to have low resistive contacts, or like Al or Cu, to have low resistive interconnects. Although the technology development has been mainly driven by the CMOS transistor downscaling, other devices and most of all Non-Volatile Memories (NVM) have been able to evolve due to the large exploitation of these materials. NVM today represent a large portion of the overall semiconductor market and one of the most important technologies for the mobile application segment. In particular the main technology line in the NVM field is represented by the Flash Memory. Flash memory cell is based on the concept of a MOS transistor with a Floating-Gate (FG). The writing/reading operations of the cell are possible thanks again to the unique properties of the SiO2 system, being a quasi-ideal dielectric at low electric field, enabling the Flash memory to store electrons for several years, and becoming a fair conductor at higher electric field by tunnel effect, thus allowing reaching fast programming speeds. Flash have now reached the integration of many billions of bits in one monolithic component with cell dimension of 0.008um2 at 45nm technology node, always based on the FG concept. Nevertheless Flash have technological and physical constraint that will make more difficult their further scaling, even if the scaling limits are still under debate. In this contest there is the industrial interest for alternative technologies that exploit new materials and concepts to go beyond the Flash technology, to allow better scaling, and to enlarge the memory performance. Hence other technologies, alternative to floating gate devices, have been proposed and are under investigation. These new proposals exploit different physical mechanisms and different materials to store the information: magnetism and magnetoresistive materials (e.g. Co, Ni, Fe, Mn) in magnetic memories or MRAM; ferroelectricity and perovskite materials (e.g. PbTixZr1-xO3 or SrBi2Ta2O9 or BaxSr1-xTiO3) in ferroelectric memories or FeRAM; phase change and chalcogenide materials (e.g. Ge2Sb2Te5 or AsInSbTe) in phase-change memory or PCM. Among these alternative NVM, PCM are one of the most promising candidates to become a mainstream NVM, having the potentiality to improve the performance compared to Flash - random access time, read throughput, direct write, bit granularity, endurance - as well as to be scalable beyond Flash technology.

Resistive random access memory (RRAM), which is considered as one of the most promising next-generation non-volatile memory (NVM) devices and a representative of memristor technologies, demonstrated great potential in acting as an artificial synapse in the industry of neuromorphic systems and artificial intelligence (AI), due its advantages such as fast operation speed, low power consumption, and high device density. Graphene and related materials (GRMs), especially graphene oxide (GO), acting as active materials for RRAM devices, are considered as a promising alternative to other materials including metal oxides and perovskite materials. Herein, an overview of GRM-based RRAM devices is provided, with discussion about the properties of GRMs, main operation mechanisms for resistive switching (RS) behavior, figure of merit (FoM) summary, and prospect extension of GRM-based RRAM devices. With excellent physical and chemical advantages like intrinsic Young’s modulus (1.0 TPa), good tensile strength (130 GPa), excellent carrier mobility (2.0 × 105 cm2∙V−1∙s−1), and high thermal (5000 Wm−1∙K−1) and superior electrical conductivity (1.0 × 106 S∙m−1), GRMs can act as electrodes and resistive switching media in RRAM devices. In addition, the GRM-based interface between electrode and dielectric can have an effect on atomic diffusion limitation in dielectric and surface effect suppression. Immense amounts of concrete research indicate that GRMs might play a significant role in promoting the large-scale commercialization possibility of RRAM devices.

Emerging <u>N</u>on-<u>V</u>olatile <u>M</u>emory (NVM) technologies like 3DX-point promise significant performance potential for OLTP databases. However, transactional databases need to be redesigned because the key assumptions that non-volatile storage is orders of magnitude slower than DRAM and only supports blocked-oriented access have changed. NVMs are byte-addressable and almost as fast as DRAM. The capacity of NVM is much (4-16x) larger than DRAM. Such NVM characteristics make it possible to build OLTP database entirely in NVM main memory. This paper studies the structure of OLTP engines with hybrid NVM and DRAM memory. We observe three challenges to design an OLTP engine for NVM: tuple metadata modifications, NVM write redundancy, and NVM space management. We propose Zen, a high-throughput log-free OLTP engine for NVM. Zen addresses the three design challenges with three novel techniques: metadata enhanced tuple cache, log-free persistent transactions, and light-weight NVM space management. Experimental results on a real machine equipped with Intel Optane DC Persistent Memory show that Zen achieves up to 10.1x improvement compared with existing solutions to run an OLTP database as large as the size of NVM while achieving fast failure recovery.

Les ordinateurs modernes sont construits autour de deux éléments : leur CPU etleur mémoire principale volatile, ou RAM. Depuis les années 1970, ce principe a étéconstamment amélioré pour offrir toujours plus de fonctionnalités et de performances.Dans cette thèse, nous étudions deux paradigmes de mémoire qui proposent denouvelles façons d'interagir avec la mémoire dans les systèmes modernes : la mémoirenon-volatile et les accès mémoire distants. Nous mettons en œuvre des outils logicielsqui exploitent ces nouvelles approches afin de les rendre compatibles et d'exploiterleurs performances avec des applications concrètes. Nous analysons égalementl'impact des technologies utilisées, et les perspectives de leur évolution dans lesannées à venir.Pour la mémoire non-volatile, comme les performances de la mémoire sont essentiellespour atteindre le potentiel d'un CPU, cette fonctionnalité a historiquement été abandonnée.Même si les premiers ordinateurs ont été conçus avec des formes de mémoire nonvolatiles, les architectes informatiques ont commencé à utiliser la RAM volatilepour ses performances inégalées, et n'ont jamais remis en question cette décisionpendant des années. Cependant, en 2019, Intel a commercialisé un nouveau composantappelé Optane DCPMM qui rend possible l'utilisation de NVMM. Ce produit proposeune nouvelle façon de penser la persistance des données. Mais il remet égalementen question l'architecture de nos machines et la manière dont nous les programmons.Avec cette nouvelle forme de mémoire, nous avons implémenté NVCACHE, un cacheen mémoire non-volatile qui permet d'accélérer les interactions avec des supportsde stockage persistants plus lents, tels que les SSD. Nous montrons que NVCACHEest particulièrement performant pour les tâches qui nécessitent une granularitéélevée des garanties de persistance, tout en étant aussi simple à utiliser que l'interfacePOSIX traditionnelle. Comparé aux systèmes de fichiers conçus pour NVMM, NVCACHEpeut atteindre un débit similaire ou supérieur lorsque la mémoire non volatile estutilisée. De plus, NVCACHE permet aux programmes d'exploiter les performancesde NVMM sans être limité par la quantité de NVMM installée sur la machine.Un autre changement majeur dans le paysage informatique a été la popularité dessystèmes distribués. Alors que les machines ont individuellement tendance à atteindredes limites de performances, l'utilisation de plusieurs machines et le partage destâches sont devenus la nouvelle façon de créer des ordinateurs puissants. Bien quece mode de calcul permette d'augmenter le nombre de CPU utilisés simultanément,il nécessite une connexion rapide entre les nœuds de calcul. Pour cette raison,plusieurs protocoles de communication ont implémententé RDMA, un moyen delire ou d'écrire directement dans la mémoire d'un serveur distant. RDMA offre defaibles latences et un débit élevé, contournant de nombreuses étapes de la pileréseau.Cependant, RDMA reste limité dans ses fonctionnalités natives. Par exemple, iln'existe pas d'équivalent de multicast pour les fonctions RDMA les plus efficaces.Grâce à un switch programmable (le switch Intel Tofino), nous avons implémentéun mode spécial pour RDMA qui permet de lire ou d'écrire sur plusieurs serveursen même temps, sans pénalité de performances. Notre système appelé Byp4ss faitparticiper le switch aux transferts, en dupliquant les paquets RDMA. Grâce à Byp4ss,nous avons implémenté un protocole de consensus nommé DISMU. De par sa conception,DISMU est optimal en termes de latence et de débit, car il peut réduire au minimumle nombre de paquets échangés sur le réseau pour parvenir à un consensus.Enfin, en utilisant ces deux technologies, nous remarquons que les futures générationsde matériel pourraient nécessiter une nouvelle interface pour les mémoires detoutes sortes, afin de faciliter l'interopérabilité dans des systèmes qui ont tendanceà devenir de plus en plus hétérogènes et complexes
Modern computers are built around two main parts: their Central Processing Unit (CPU), and their volatile main memory, or Random Access Memory (RAM). The basis of this architecture takes its roots in the 1970's first computers. Since, this principle has been constantly upgraded to provide more functionnality and performance.In this thesis, we study two memory paradigms that drastically change the way we can interact with memory in modern systems: non-volatile memory and remote memory access. We implement software tools that leverage them in order to make them compatible and exploit their performance with concrete applications. We also analyze the impact of the technologies underlying these new memory medium, and the perspectives of their evolution in the coming years.For non-volatile memory, as the main memory performance is key to unlock the full potential of a CPU, this feature has historically been abandoned on the race for performance. Even if the first computers were designed with non-volatile forms of memory, computer architects started to use volatile RAM for its incomparable performance compared to durable storage, and never questioned this decision for years. However, in 2019 Intel released a new component called Optane DC Persistent Memory (DCPMM), a device that made possible the use of Non-Volatile Main Memory (NVMM). That product, by its capabilities, provides a new way of thinking about data persistence. Yet, it also challenges the hardware architecture used in our current machines and the way we program them.With this new form of memory we implemented NVCACHE, a cache designed for non-volatile memory that helps boosting the interactions with slower persistent storage medias, such as solid state drive (SSD). We find NVCACHE to be quite performant for workloads that require a high granularity of persistence guarantees, while being as easy to use as the traditional POSIX interface. Compared to file systems designed for NVMM, NVCACHE can reach similar or higher throughput when the non-volatile memory is used. In addition, NVCACHE allows the code to exploit NVMM performance while not being limited by the amount of NVMM installed in the machine.Another major change of in the computer landscape has been the popularity of distributed systems. As individual machines tend to reach performance limitations, using several machines and sharing workloads became the new way to build powerful computers. While this mode of computation allows the software to scale up the number of CPUs used simultaneously, it requires fast interconnection between the computing nodes. For that reason, several communication protocols implemented Remote Direct Memory Access (RDMA), a way to read or write directly into a distant machine's memory. RDMA provides low latencies and high throughput, bypassing many steps of the traditional network stack.However, RDMA remains limited in its native features. For instance, there is no advanced multicast equivalent for the most efficient RDMA functions. Thanks to a programmable switch (the Intel Tofino), we implemented a special mode for RDMA that allows a client to read or write in multiple servers at the same time, with no performance penalty. Our system called Byp4ss makes the switch participate in transfers, duplicating RDMA packets. On top of Byp4ss, we implement a consensus protocol named DISMU, which shows the typical use of Byp4ss features and its impact on performance. By design, DISMU is optimal in terms of latency and throughput, as it can reduce to the minimum the number of packets exchanged through the network to reach a consensus.Finally, by using these two technologies, we notice that future generations of hardware may require a new interface for memories of all kinds, in order to ease the interoperability in systems that tend to get more and more heterogeneous and complex

A group of new non-volatile memory technologies with characteristics making them worthy of consideration for different parts of the memory hierarchy, including the main memory, are emerging. In this thesis I discuss the state of STT-RAM, ReRAM and PCM technologies which are three of the front runners in this group of new technologies. I also simulate the performance of PCM used as main memory using Intel’s binary instrumentation framework Pin and compare it to DRAM to explore three research questions. Firstly, in the case of horizontally integrated PCM and DRAM I test a data mapping policy where an application’s stack is mapped to DRAM and the heap is mapped to PCM. I find that in the case of my simulation this mapping have no benefits since most of the stack is continually kept in the cache which causes the DRAM to end up unutilized. Secondly, I compare the read latency between PCM and DRAM and find an average increase 48 %for PCM. Thirdly, I compare the energy costs of two write policiesfor PCM. The first being write-through of dirty bytes at byte granularity and the second being full row buffer write-back. I find that the first method has on average less than a third of the energy cost compared to the second method.T

碩士
國立交通大學
資訊科學與工程研究所
101
In general system, all data in main memory are lost when occur power interruption.Use UPS(uninterruptible power supply) to protect entire system is a approach for reduce data losing. But it is also expensive for large system which need a high capacity UPS.We propose a new apporach:use standby power to protect main memory instead protect entire system. Maintain in-memory data until power restore and then write data to disk.We integrate characteristic of non-volatile memory and file-system journaling for reduce data losing in on power interrupt.

This paper describes the architecture of eNVy, a large non-volatile main memory storage system built primarily with Flash memory. Flash provides persistent storage with solid-state memory access times at a lower cost than other solid-state technologies. eNVy presents its storage space as a linear, memory mapped array rather than as a disk emulator in order to provide an efficient and easy to use software interface. Flash chips are write-once, bulk-erase devices whose contents cannot be updated in-place. They suffer from slow write times and limited program/erase cycles. eNVy uses a copy-on-write scheme, some battery-backed SRAM, and parallel operation to overcome these problems and provide low latency in-place update semantics. A specialized cleaning algorithm maximizes the lifetime of the Flash array. Simulations show that eNVy can handle I/O rates corresponding to approximately 30,000 TPS on the TPC-A benchmark with average latencies as low as 180ns for reads and 200ns for writes.

碩士
國立清華大學
資訊工程學系
104
The non-volatile main memory architecture is often proposed, because it can solve the problem of data storage of in-memory database when encountering a system failure (e.g., system crash, power failure). To achieve fast execution time, we proposed a cache-optimized tree, referred to as xB+-tree. It focuses on access the smallest number of cache lines and reduce the cache miss rate by using access-locality in insertion and query operations. The experimental results show that compared with previous unsorted leaf scheme, xB+-tree achieves up to 33.48% speedups for insertion and up to 2.74-3.16% speedups for query; compared with previous wB+-tree scheme, xB+-tree achieves up to 43.48% speedups for insertion and up to 6.98% speedups for query.

In the last decade, computer hardware progressed by leaps and bounds. The advancements of hardware include the application of multi-core CPUs, use of GPUs in data intensive tasks, bigger and bigger main memory capacity, maturity and production use of non-volatile memory, etc. Database systems immediately benefit from faster CPU/GPU and bigger memory and run faster. However, there are some pitfalls. For example, database systems running on multi-core processors may suffer from cache conflicts when the number of concurrently executing DB processes increases. To fully exploit advantages of new hardware to improve the performance of database systems, database software should be more or less revised. This chapter introduces some efforts of database research community in this aspect.

In the last decade, computer hardware progresses with leaps and bounds. The advancements of hardware include: widely application of multi-core CPUs, using of GPUs in data intensive tasks, bigger and bigger main memory capacity, maturity and production use of non-volatile memory etc. Database systems immediately benefit from faster CPU/GPU and bigger memory, and run faster. However, there are some pitfalls. For example, database systems running on multi-core processors may suffer from cache conflicts when the number of concurrently executing DB processes increases. To fully exploit advantages of new hardware to improve the performance of database systems, database software should be more or less revised. This chapter introduces some efforts of database research community in this aspect.

Multiferroic BiFeO3 deals with spintronic devices involved spin-charge processes and applicable in new non-volatile memory devices to store information for computing performance and the magnetic random access memories storage. Since multiferroic leads to the new generation memory devices for which the data can be written electrically and read magnetically. The main advantage of present study of multiferroic BiFeO3 is that to observe magnetoelectric effects at room temperature. The nanostructural growth (for both size and shape) of BiFeO3 may depend on the selection of appropriate synthesis route, reaction conditions and heating processes. In pure BiFeO3, the ferroelectricity is induced by 6s2 lone-pair electrons of Bi3+ ions and the G-type antiferromagnetic ordering resulting from Fe3+ spins order of cycloidal (62-64 nm wavelength) occurred below Neel temperature, TN = 640 K. The multiferroicity of BiFeO3 is disappeared due to factors such as impurity phases, leakage current and low value of magnetization. Therefore, to overcome such factors to get multiferroic enhancement in BiFeO3, there are different possible ways like changes dopant ions and their concentrations, BiFeO3 composites as well as thin films especially multilayers.