Artículos de revistas: "NM TECHNOLOGY NODE"

1

Itani, Toshiro. "157 nm Lithography for 70 nm Technology Node". Japanese Journal of Applied Physics 41, Part 1, No. 6B (30 de junio de 2002): 4033–36. http://dx.doi.org/10.1143/jjap.41.4033.

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2

Thompson, K., J. H. Booske, Y. B. Gianchandani y R. F. Cooper. "Electromagnetic annealing for the 100 nm technology node". IEEE Electron Device Letters 23, n.º 3 (marzo de 2002): 127–29. http://dx.doi.org/10.1109/55.988813.

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3

Ogawa, Yoshihiro. "Cleaning Technology for Advanced Devices beyond 20 nm Node". Solid State Phenomena 195 (diciembre de 2012): 7–12. http://dx.doi.org/10.4028/www.scientific.net/ssp.195.7.

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Several attempts have recently been made to use novel high-k dielectric materials, such as AlxOy, HfxAlyOz, HfxSiyOz, and HfxOy, to improve electrical device characteristics of advanced devices. Moreover, it is becoming increasingly important in the ULSI manufacturing process to suppress contamination by metal or particles from the wafer backside or edge. This paper reviews the wafer backside/edge control technology for suppression of metal contamination.

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4

SHAHIDI, GHAVAM G. "ARE WE AT THE END OF CMOS SCALING?" International Journal of High Speed Electronics and Systems 16, n.º 01 (marzo de 2006): 3–8. http://dx.doi.org/10.1142/s0129156406003503.

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CMOS scaling enabled by advances in lithography has been behind the information revolution. Over the last 15 years, there has been a new CMOS technology node approximately every two years. The key feature of every node has been 2X density shrink and ~35% performance gain per technology node. At 90 nm node a number usual knobs that have enabled the scaling have approached their limits. Furthermore chip power (both active and stand-by) has been increasing rapidly, approaching air cool limit. Chip stand-by power, which was negligible a few years ago, is now about the same order of magnitude as the active power in high end microprocessors. In this talk it will be argued that because of power density limitation of 90 nm, 65 nm, and beyond nodes, performance and ability to shrink are more than ever linked, and in fact if the performance gain would significantly slow down (for the designs that operate at the existing cooling limit). It is more than ever critical to come up with technology features that will enhance the performance, at a given device leakage.

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5

Feudel, Thomas. "Advanced Annealing Schemes for High-Performance SOI Logic Technologies". Materials Science Forum 573-574 (marzo de 2008): 387–400. http://dx.doi.org/10.4028/www.scientific.net/msf.573-574.387.

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We have extensively studied the impact of advanced annealing schemes for highperformance SOI logic technologies. Starting with the 130 nm technology node, we introduced spike rapid thermal annealing (sRTA). Continuous temperature reduction combined with implant scaling helped to improve transistor performance and short channel behavior. During the development of the 90 nm technology we evaluated flash lamp and laser annealing (FLA). These techniques became an essential part of the 65 nm node. At this node we also faced major challenges in terms of compatibility with new materials like SiGe as well as the need for reduction of process parameter fluctuations. Scaling will be continued with the 45 nm technology node towards a truly diffusionless process.

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6

Li, Zongru, Christopher Jarrett Elash, Chen Jin, Li Chen, Jiesi Xing, Zhiwu Yang y Shuting Shi. "Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies". Electronics 11, n.º 11 (1 de junio de 2022): 1757. http://dx.doi.org/10.3390/electronics11111757.

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Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 gates were used to observe the output frequency drift and current draw. Experimental results show a noticeable increased device current draw and decreases in RO frequencies where NOR2 ROs have the most degradation. As well, the functionality of a 256 kb SRAM block and shift-register chains were evaluated during C0-60 irradiation. SRAM functionality deteriorated at 325 krad(Si) of the total dosage, while the FF chains remained functional up to 1 Mrad(Si). Overall, the 22-nm FD SOI results show better resilience to TID effects compared to the 28-nm FD SOI technology node.

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7

Suganaga, Toshifumi. "157 nm lithography with high numerical aperture lens for the 70 nm technology node". Journal of Micro/Nanolithography, MEMS, and MOEMS 1, n.º 3 (1 de octubre de 2002): 206. http://dx.doi.org/10.1117/1.1501565.

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8

Allgair, John, Benjamin Bunday, Aaron Cordes, Pete Lipscomb, Milt Godwin, Victor Vartanian, Michael Bishop, Doron Arazi y Kye-Weon Kim. "Metrology Requirements for the 32 nm Technology Node and Beyond". ECS Transactions 18, n.º 1 (18 de diciembre de 2019): 151–60. http://dx.doi.org/10.1149/1.3096443.

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9

Wakabayashi, H., G. S. Samudra, I. J. Djomehri, H. Nayfeh y D. A. Antoniadis. "Supply-voltage optimization for below-70-nm technology-node MOSFETs". IEEE Transactions on Semiconductor Manufacturing 15, n.º 2 (mayo de 2002): 151–56. http://dx.doi.org/10.1109/66.999586.

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10

Takeda, Eiji, Eiichi Murakami, Kazuyoshi Torii, Yutaka Okuyama, Eishi Ebe, Kenji Hinode y Shin'ichiro Kimura. "Reliability issues of silicon LSIs facing 100-nm technology node". Microelectronics Reliability 42, n.º 4-5 (abril de 2002): 493–506. http://dx.doi.org/10.1016/s0026-2714(02)00029-x.

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11

Saxena, Shubhangi y Kamsali Manjunathachari. "Novel Nanoelectronic Materials and Devices: For Future Technology Node". ECS Transactions 107, n.º 1 (24 de abril de 2022): 15701–11. http://dx.doi.org/10.1149/10701.15701ecst.

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Since the last six decades, technology node has grown smaller from micrometer to nanometer dimensions. In continuation of Moore's Law, the research is going on for device/supply voltage shrinking to go beyond 22 nm CMOS technology node. However, many physical and quantum challenges appear at a smaller scale, which causes shrinking beyond 22 nm critical and needs innovative materials and devices for scaling in the nanometer regime. Incorporating nanoengineered materials to realize research achievements has shown timely development with significant influence in electronic industries. These new materials and devices hold promise as potential device candidates to be integrated onto the silicon platform to enhance semiconductor industry growth and extend Moore's Law. Here we address state–of–the–art research trends in nanomaterials and nanodevices for future technology node and discuss associated challenges.

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12

Tomita, Hiroshi, Yuji Yamada, Hidenobu Nagashima, Norio Ishikawa y Yumiko Taniguchi. "New FEOL Cleaning Technology for Advanced Devices beyond 45 nm Node". Solid State Phenomena 134 (noviembre de 2007): 185–88. http://dx.doi.org/10.4028/www.scientific.net/ssp.134.185.

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13

Kim, Juhyun, Myunggon Kang, Jongwook Jeon y Hyungcheol Shin. "Device Optimization of Nano-Plate Transistors for 3.5 nm Technology Node". Journal of Nanoscience and Nanotechnology 19, n.º 10 (1 de octubre de 2019): 6771–75. http://dx.doi.org/10.1166/jnn.2019.17108.

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14

Berry, C., J. Warnock, J. Badar, D. G. Bair, E. Behnen, B. Bell, A. Buyuktosunoglu et al. "IBM z14 design methodology enhancements in the 14-nm technology node". IBM Journal of Research and Development 62, n.º 2/3 (1 de marzo de 2018): 9:1–9:12. http://dx.doi.org/10.1147/jrd.2018.2800218.

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15

Jang, Doyoung, Dmitry Yakimets, Geert Eneman, Pieter Schuddinck, Marie Garcia Bardon, Praveen Raghavan, Alessio Spessot, Diederik Verkest y Anda Mocuta. "Device Exploration of NanoSheet Transistors for Sub-7-nm Technology Node". IEEE Transactions on Electron Devices 64, n.º 6 (junio de 2017): 2707–13. http://dx.doi.org/10.1109/ted.2017.2695455.

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16

Xu, Peng, Yinghua Piao, Liang Ge, Cheng Hu, Lun Zhu, Zhiwei Zhu, David Wei Zhang y Dongping Wu. "Investigation of Novel Junctionless MOSFETs for Technology Node Beyond 22 nm". ECS Transactions 44, n.º 1 (15 de diciembre de 2019): 33–39. http://dx.doi.org/10.1149/1.3694293.

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17

Holmes, Steven. "22-nm-node technology active-layer patterning for planar transistor devices". Journal of Micro/Nanolithography, MEMS, and MOEMS 9, n.º 1 (1 de enero de 2010): 013001. http://dx.doi.org/10.1117/1.3302125.

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18

Vandervorst, Wilfried, Trudo Clarysse y Pierre Eyben. "Spreading resistance roadmap towards and beyond the 70 nm technology node". Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 20, n.º 1 (2002): 451. http://dx.doi.org/10.1116/1.1446455.

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19

Nagase, Masatoshi, Takuya Maruyama y Makoto Sekine. "Advanced CD Control Technology for 65-nm Node Dual Damascene Process". IEEE Transactions on Semiconductor Manufacturing 20, n.º 3 (agosto de 2007): 245–51. http://dx.doi.org/10.1109/tsm.2007.901842.

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20

Lazzaz, Abdelaziz, Khaled Bousbahi y Mustapha Ghamnia. "Performance analysis of FinFET based inverter, NAND and NOR circuits at 10 NM,7 NM and 5 NM node technologies". Facta universitatis - series: Electronics and Energetics 36, n.º 1 (2023): 1–16. http://dx.doi.org/10.2298/fuee2301001l.

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Advancement in the semiconductor industry has transformed modern society. A miniaturization of a silicon transistor is continuing following Moore?s empirical law. The planar metal-oxide semiconductor field effect transistor (MOSFET) structure has reached its limit in terms of technological node reduction. To ensure the continuation of CMOS scaling and to overcome the Short Channel Effect (SCE) issues, a new MOS structure known as Fin field-effect transistor (FinFET) has been introduced and has led to significant performance enhancements. This paper presents a comparative study of CMOS gates designed with FinFET 10 nm, 7 nm and 5 nm technology nodes. Electrical parameters like the maximum switching current ION, the leakage current IOFF, and the performance ratio ION/IOFF for N and P FinFET with different nodes are presented in this simulation. The aim and the novelty of this paper is to extract the operating frequency for CMOS circuits using Quantum and Stress effects implemented in the Spice parameters on the latest Microwind software. The simulation results show a fitting with experimental data for FinFET N and P 10 nm strctures using quantum correction. Finally, we have demonstrate that FinFET 5 nm can reach a minimum time delay of td=1.4 ps for CMOS NOT gate and td=1 ps for CMOS NOR gate to improve Integrated Circuits IC.

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21

Hussain, Inamul y Saurabh Chaudhury. "CNFET Based Low Power Full Adder Circuit for VLSI Applications". Nanoscience & Nanotechnology-Asia 10, n.º 3 (17 de junio de 2020): 286–91. http://dx.doi.org/10.2174/2210681209666190220122553.

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Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime. Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET as well as different CMOS technology nodes. Method: A new low power full adder cell has been proposed with a hybrid XOR/XNOR module by using CNFET, which is also compatible for the CMOS technology nodes. The performance of the adder cell is validated with HSPICE simulation in terms of power, delay and power delay product. It is observed that the proposed adder cell performs better than the CMOS, CPL, TGA, 10 T, 14 T, 24 T, HSPC and Hybrid_FA adder cells. The CNFET full adder is designed in 32 nm CNFET model and to appraise its compatibility with Bulk-Si CMOS technology, 90 nm and 32 nm CMOS technology node is used. Conclusion: The proposed adder is very much suitable for both CMOS and CNFET technology based circuits and systems. To validate the result, simulation has been carried out with Synopsis tool. This full adder will definitely dominate other full adder cells at various technology nodes for VLSI applications.

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22

Šedivý, Josef, Petr Průša, Jiří Čejka y Ladislav Bartuška. "Utilization of the Capacitated Vehicle Routing Problem with the Capacity Limitation of Nodes in Water Transportation". Naše more 69, n.º 3 (noviembre de 2022): 149–58. http://dx.doi.org/10.17818/nm/2022/3.5.

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The paper discusses the option of using the capacitated vehicle routing problem with the capacity limitation of nodes in water transportation. The problem is used to design circular routes for vehicles of different carriers, each of which services the selected nodes of the transportation network. The goal is to design circular routes where the capacity of vehicles is not exceeded and the value of the objective function is minimal. The limited capacity of nodes is given by the limited number of vehicles that can be operated at a particular node at any given time. The problem allows to design circulation so that the waiting time of vehicles to release the capacity of the node is minimized. This makes it possible to achieve an additional reduction in the total traffic time. The possibility of using the role of the CVRPCLN in water transportation is demonstrated in a case study for the design of circular routes for vessels serving ports. The design of routes is performed using the described problem and using the capacitated vehicle routing problem, which does not take into account the limited capacity of the nodes. To solve both problems, the author uses an evolutionary algorithm, which is part of the optimization module Solver. A comparison of the results indicates that the use of the investigated task can lead to a significant reduction in waiting times in ports for selected tasks in the field of water transportation. This also leads to a significant reduction in the total traffic time.

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23

Bonifacio, Cecile, Michael Campin, Kevin McIlwrath y Paul Fischione. "Post-FIB Cleaning of TEM Specimens from 14 nm and Other FinFETs by Concentrated Argon Ion Milling". EDFA Technical Articles 21, n.º 4 (1 de noviembre de 2019): 4–12. http://dx.doi.org/10.31399/asm.edfa.2019-4.p004.

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Abstract TEM specimens prepared using a Ga FIB are susceptible to artifacts, such as surface amorphization and ion-implanted layers, that can be problematic in advanced technology nodes, particularly for FinFETs. As this article shows, however, post-FIB cleaning via concentrated argon ion milling makes for a fast and effective specimen preparation process for FinFET devices controlled to a thickness of less than 20 nm. Although the results presented here are based on 14 nm node FinFETs, the method is also applicable to the 10 and 7 nm FinFET technologies currently in production.

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24

Dash, T. P., S. Dey, S. Das, J. Jena, E. Mahapatra y C. K. Maiti. "Source/Drain Stressor Design for Advanced Devices at 7 nm Technology Node". Nanoscience & Nanotechnology-Asia 10, n.º 4 (26 de agosto de 2020): 447–56. http://dx.doi.org/10.2174/2210681209666190809101307.

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Background:: In nano and microelectronics, device performance enhancement is limited by downscaling. Introduction of intentional mechanical stress is a potential mobility booster to overcome these limitations. This paper explores the key design challenges of stress-engineered FinFETs based on the epitaxial SiGe S/D at 7 nm Technology node. Objective:: To study the mechanical stress evolution in a tri-gate FinFET at 7 nm technology node using technology CAD (TCAD) simulations. Using stress maps, we analyze the mechanical stress impact on the transfer characteristics of the devices through device simulation. Methods: 3D sub-band Boltzmann transport analysis for tri-gate PMOS FinFETs was used, with 2D Schrödinger solution in the fin cross-section and 1D Boltzmann transport along the channel. Results:: Using stress maps, the mechanical stress impact on the transfer characteristics of the device through device simulation has been analyzed. Conclusion:: Suitability of predictive TCAD simulations to explore the potential of innovative strain-engineered FinFET structures for future generation CMOS technology is demonstrated.

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25

Huang, Zhengfeng, Di Cao, Jianguo Cui, Yingchun Lu, Yiming Ouyang, Haochen Qi, Qi Xu, Huaguo Liang y Tianming Ni. "Design of Multiple Node Upset Tolerant Latch in 32 nm CMOS Technology". Journal of Computer-Aided Design & Computer Graphics 33, n.º 3 (1 de marzo de 2021): 346–55. http://dx.doi.org/10.3724/sp.j.1089.2021.18385.

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26

Zhu, Jinlong, Jiamin Liu, Tianlai Xu, Shuai Yuan, Zexu Zhang, Hao Jiang, Honggang Gu, Renjie Zhou y Shiyuan Liu. "Optical wafer defect inspection at the 10 nm technology node and beyond". International Journal of Extreme Manufacturing 4, n.º 3 (21 de abril de 2022): 032001. http://dx.doi.org/10.1088/2631-7990/ac64d7.

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Abstract The growing demand for electronic devices, smart devices, and the Internet of Things constitutes the primary driving force for marching down the path of decreased critical dimension and increased circuit intricacy of integrated circuits. However, as sub-10 nm high-volume manufacturing is becoming the mainstream, there is greater awareness that defects introduced by original equipment manufacturer components impact yield and manufacturing costs. The identification, positioning, and classification of these defects, including random particles and systematic defects, are becoming more and more challenging at the 10 nm node and beyond. Very recently, the combination of conventional optical defect inspection with emerging techniques such as nanophotonics, optical vortices, computational imaging, quantitative phase imaging, and deep learning is giving the field a new possibility. Hence, it is extremely necessary to make a thorough review for disclosing new perspectives and exciting trends, on the foundation of former great reviews in the field of defect inspection methods. In this article, we give a comprehensive review of the emerging topics in the past decade with a focus on three specific areas: (a) the defect detectability evaluation, (b) the diverse optical inspection systems, and (c) the post-processing algorithms. We hope, this work can be of importance to both new entrants in the field and people who are seeking to use it in interdisciplinary work.

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27

Huang, Zhengfeng, Yang Guo, Shangjie Pan, Yingchun Lu, Huaguo Liang, Haochen Qi, Yiming Ouyang, Tianming Ni y Qi Xu. "Tri-Node Upsets Self-Recovery Latch Design in 32 nm CMOS Technology". Journal of Computer-Aided Design & Computer Graphics 32, n.º 12 (1 de diciembre de 2020): 2013–20. http://dx.doi.org/10.3724/sp.j.1089.2020.18160.

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28

KANG, Yesung y Youngmin KIM. "Intra-Gate Length Biasing for Leakage Optimization in 45 nm Technology Node". IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E96.A, n.º 5 (2013): 947–52. http://dx.doi.org/10.1587/transfun.e96.a.947.

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29

SANDHYA, KESHARWANI y DEDHE VAIBHAV. "DOUBLE NODE UPSET RADIATION IMMUNE LATCH DESIGN IN 65 NM CMOS TECHNOLOGY". i-manager's Journal on Circuits and Systems 6, n.º 3 (2018): 21. http://dx.doi.org/10.26634/jcir.6.3.14624.

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30

Baklanov, Mikhail R., Evgeny A. Smirnov y Larry Zhao. "Ultra Low Dielectric Constant Materials for 22 nm Technology Node and Beyond". ECS Transactions 35, n.º 4 (16 de diciembre de 2019): 717–28. http://dx.doi.org/10.1149/1.3572315.

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31

Hook, Terence B. "Power and Technology Scaling into the 5 nm Node with Stacked Nanosheets". Joule 2, n.º 1 (enero de 2018): 1–4. http://dx.doi.org/10.1016/j.joule.2017.10.014.

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32

Dash, Tara Prasanna, Suprava Dey, Sanghamitra Das, Eleena Mohapatra, Jhansirani Jena y Chinmay Kumar Maiti. "Strain-engineering in nanowire field-effect transistors at 3 nm technology node". Physica E: Low-dimensional Systems and Nanostructures 118 (abril de 2020): 113964. http://dx.doi.org/10.1016/j.physe.2020.113964.

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33

Oboňa, Jozef Vincenc, Tomáš Hrnčíř, Sharang, Marek Šikula y Andrey Denisyuk. "Xe plasma FIB Delayering of IC based on 14 nm node technology". Microscopy and Microanalysis 22, S3 (julio de 2016): 56–57. http://dx.doi.org/10.1017/s1431927616001136.

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34

Ono, Kazuo, Kenzo Kurotsuchi, Yoshihisa Fujisaki, Riichiro Takemura, Motoyasu Terao y Norikatsu Takaura. "Resistive Switching Ion-Plug Memory for 32-nm Technology Node and Beyond". Japanese Journal of Applied Physics 48, n.º 4 (20 de abril de 2009): 04C160. http://dx.doi.org/10.1143/jjap.48.04c160.

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35

Lin, Jen-Chieh, Teng-Chun Tsai, Chia-Lin Hsu, Welch Lin, Chien-Chung Huang, Chih-Hsien Chen y J. Y. Wu. "Advanced Rework Process Development for Cu-CMP at 28 nm Technology Node". ECS Transactions 33, n.º 10 (17 de diciembre de 2019): 175–80. http://dx.doi.org/10.1149/1.3489058.

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36

Broussous, Lucile, D. Krejcirova, K. Courouble, S. Zoll, A. Iwasaki, H. Ishikawa, F. Buisine, A. Lamaury y D. Fuard. "TiN Hard Mask Cleans with SC1 Solutions, for 64nm Pitch BEOL Patterning". Solid State Phenomena 219 (septiembre de 2014): 209–12. http://dx.doi.org/10.4028/www.scientific.net/ssp.219.209.

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Titanium Nitride metal hard mask was first introduced for BEOL patterning at 65 nm [1] and 45 nm nodes [2]. Indeed, in this “Trench First Hard Mask” (TFHM) backend architecture, the dual hard mask stack (SiO2 & TiN) allows a minimized exposure of ULK materials to damaging plasma chemistries, both for line/via etch sequence, and lithography reworks operations. This integration scheme was successfully used for a BEOL pitch down to 90 nm for the 28 nm node, however, for the 14 nm technology node, 64 nm BEOL minimum pitch is required for the first metal levels. Because it is unable to resolve features below 80 nm pitch in a single exposure, conventional 193 nm immersion lithography must be associated with dual patterning schemes, so called Lithography-Etch-Lithography-Etch (LELE) patterning [3] for line levels and self-aligned via (SAV) process [4] for via patterning. In both cases, 2 lithography/etch/clean sequences are necessary to obtain one desired pattern, and associated reworks also become more challenging since first pattern is exposed to resist removal processes (plasma + wet clean). The reference wet cleans that were developed for 65 to 28 nm TiN hardmask patterning, utilizes commonly used chemistry for BEOL post-etch cleans, i.e. diluted hydrofluoric acid (dHF) followed by deionized water Nanospray (DIWNS) on 300 mm single wafer tool.

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37

Jain, Amitabh. "Ultra-Shallow Junction Formation Using Rapid Thermal Processing". Materials Science Forum 573-574 (marzo de 2008): 305–18. http://dx.doi.org/10.4028/www.scientific.net/msf.573-574.305.

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One of the main materials challenges of the 130 nm silicon technology node was the need to find a processing solution to the anomalous diffusion behavior of ion-implanted dopants known from three decades of research. Reduction of implantation energy no longer proved sufficient when trying to reduce source/drain extension junction depth, increase abruptness, and limit sheet resistance. Spike-annealing, a new process in which ion implanted silicon could be heated rapidly to temperatures required for dopant activation and then cooled down without dwelling at temperature, adequately addressed the scaling requirements of this node. The resulting junctions achieved high dopant concentration values very close to the surface while limiting junction depth. However, this increased the propensity for dopant migration to overlying layers associated with the source/drain spacer. Loss of device performance due to this and other phenomena became a strong motivating factor for further materials research in order to sustain progress through the 130 nm and 90 nm nodes. Complex interactions between various layers have been understood and the resulting developments in spacer materials have enabled high performance devices. The requirements of the 65 and 45 nm nodes stretch spike-annealing to its limit and newer ultra-high temperature anneals must be considered.

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38

Lamy, Magali, Marc de la Bardonnie, Frederic Lorut, Ryan Ross, Christophe Wyon y Laurens F. Tz Kwakman. "How Effective Are Failure Analysis Methods for the 65 nm CMOS Technology Node?" EDFA Technical Articles 8, n.º 2 (1 de mayo de 2006): 14–20. http://dx.doi.org/10.31399/asm.edfa.2006-2.p014.

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Abstract This article assesses the capabilities of failure analysis techniques in the context of 65 nm CMOS ICs. It demonstrates the use of OBIRCH, voltage contrast, Seebeck effect imaging, SEM and TEM techniques, and FIB cross-sectioning on failures such as dielectric breakdown, open and resistive vias, voids, shorts, delaminations, and gate oxide defects.

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39

De, Indranil, Deepak Johri, Anadi Srivastava y C. M. Osburn. "Impact of gate workfunction on device performance at the 50 nm technology node". Solid-State Electronics 44, n.º 6 (junio de 2000): 1077–80. http://dx.doi.org/10.1016/s0038-1101(99)00323-8.

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40

Gao, Weimin, Ivan Ciofi, Yves Saad, Philippe Matagne, Michael Bachmann, Werner Gillijns, Kevin Lucas, Wolfgang Demmerle y Thomas Schmoeller. "Rigorous assessment of patterning solution of metal layer in 7 nm technology node". Journal of Micro/Nanolithography, MEMS, and MOEMS 15, n.º 1 (19 de febrero de 2016): 013505. http://dx.doi.org/10.1117/1.jmm.15.1.013505.

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41

Orlowski, Marius y Andreas Wild. "Can 3-D Devices Extend Moore's Law Beyond the 32 nm Technology Node?" ECS Transactions 3, n.º 6 (21 de diciembre de 2019): 3–17. http://dx.doi.org/10.1149/1.2357050.

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42

Park, Dae-Gyu, Mike Chudzik y Haizhou Yin. "Challenges in FEOL Logic Device Integration for 32 nm Technology Node and Beyond". ECS Transactions 11, n.º 6 (19 de diciembre de 2019): 371–77. http://dx.doi.org/10.1149/1.2778394.

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43

Yan, Jhih-Yang, Sun-Rong Jan, Yi-Chung Huang, Huang-Siang Lan, Y. H. Huang, Bigchoug Hung, K. T. Chan, Michael Huang, M. T. Yang y C. W. Liu. "Asymmetric Keep-Out Zone of Through-Silicon Via Using 28-nm Technology Node". IEEE Electron Device Letters 36, n.º 9 (septiembre de 2015): 938–40. http://dx.doi.org/10.1109/led.2015.2456179.

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44

Rezgui, Houssem, Faouzi Nasri, Giovanni Nastasi, Mohamed Fadhel Ben Aissa, Salah Rahmouni, Vittorio Romano, Hafedh Belmabrouk y Amen Allah Guizani. "Design optimization of nanoscale electrothermal transport in 10 nm SOI FinFET technology node". Journal of Physics D: Applied Physics 53, n.º 49 (25 de septiembre de 2020): 495103. http://dx.doi.org/10.1088/1361-6463/abaf7c.

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45

Noguchi, J., K. Sato, N. Konishi, S. Uno, T. Oshima, K. Ishikawa, H. Ashihara et al. "Process and Reliability of Air-Gap Cu Interconnect Using 90-nm Node Technology". IEEE Transactions on Electron Devices 52, n.º 3 (marzo de 2005): 352–59. http://dx.doi.org/10.1109/ted.2005.843886.

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46

Huang, Zhengfeng, Yan Zhang, Wenhui Wu, Lanxi Duan, Huaguo Liang, Yiming Ouyang, Aibin Yan y Tai Song. "A high-speed quadruple-node-upset-tolerant latch in 22 nm CMOS technology". Microelectronics Reliability 147 (agosto de 2023): 115032. http://dx.doi.org/10.1016/j.microrel.2023.115032.

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47

Lu, Peng, Can Yang, Yifei Li, Bo Li y Zhengsheng Han. "Three-Dimensional TID Hardening Design for 14 nm Node SOI FinFETs". Eng 2, n.º 4 (3 de diciembre de 2021): 620–31. http://dx.doi.org/10.3390/eng2040039.

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The fin field-effect transistor (FinFET) has been the mainstream technology on the VLSI platform since the 22 nm node. The silicon-on-insulator (SOI) FinFET, featuring low power consumption, superior computational power and high single-event effect (SEE) resistance, shows advantages in integrated circuits for space applications. In this work, a rad-hard design methodology for SOI FinFETs is shown to improve the devices’ tolerance against the Total Ionizing Dose (TID) effect. Since the fin height direction enables a new dimension for design optimization, a 3D Source/Drain (S/D) design combined with a gate dielectric de-footing technique, which has been readily developed for the 14 nm node FinFETs, is proposed as an effective method for SOI FinFETs’ TID hardening. More importantly, the governing mechanism is thoroughly investigated using fully calibrated technology computer-aided design (TCAD) simulations to guide design optimizations. The analysis demonstrates that the 3D rad-hard design can modulate the leakage path in 14 nm node n-type SOI FinFETs, effectively suppress the transistors’ sensitivity to the TID charge and reduce the threshold voltage shift by >2×. Furthermore, the rad-hard design can reduce the electric field in the BOX region and lower its charge capture rate under radiation, further improving the transistor’s robustness.

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48

Mo, Fabrizio, Chiara Elfi Spano, Yuri Ardesi, Massimo Ruo Roch, Gianluca Piccinini y Marco Vacca. "NS-GAAFET Compact Modeling: Technological Challenges in Sub-3-nm Circuit Performance". Electronics 12, n.º 6 (21 de marzo de 2023): 1487. http://dx.doi.org/10.3390/electronics12061487.

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NanoSheet-Gate-All-Around-FETs (NS-GAAFETs) are commonly recognized as the future technology to push the digital node scaling into the sub-3 nm range. NS-GAAFETs are expected to replace FinFETs in a few years, as they provide highly electrostatic gate control thanks to the GAA structure, with four sides of the NS channel entirely enveloped by the gate. At the same time, the NS rectangular cross-section is demonstrated to be effective in its driving strength thanks to its high saturation current, tunable through the NS width used as a design parameter. In this work, we develop a NS-GAAFET compact model and we use it to link peculiar single-device parameters to digital circuit performance. In particular, we use the well-known BSIM-CMG core solver for multigate transistors as a starting point and develop an ad hoc resistive and capacitive network to model the NS-GAAFET geometrical and physical structure. Then, we employ the developed model to design and optimize a digital inverter and a five-stage ring oscillator, which we use as a performance benchmark for the NS-GAAFET technology. Through Cadence Virtuoso SPICE simulations, we investigate the digital NS-GAAFET performance for both high-performance and low-power nodes, according to the average future node present in the International Roadmap for Devices and Systems. We focus our analysis on the main different technological parameters with regard to FinFET, i.e., the inner and outer spacers. Our results highlight that in future technological nodes, the choice of alternative low-K dielectric materials for the NS spacers will assume increasing importance, being as relevant, or even more relevant, than photolithographic alignment and resolution at the sub-nm scale.

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49

Iwasaki, Akihisa, Kristell Courouble, Steven Lippy, Fabrice Buisine, Hidekazu Ishikawa, Emanuel Cooper, Evelyn Kennedy, Stephane Zoll y Lucile Broussous. "Industrial Challenges of TiN Hard Mask Wet Removal Process for 14nm Technology Node". Solid State Phenomena 219 (septiembre de 2014): 213–16. http://dx.doi.org/10.4028/www.scientific.net/ssp.219.213.

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TiN Hard Mask (TiN-HM) integration scheme has been widely used for BEOL patterning in order to avoid ultra low-k (ULK) damage during plasma-ash process [1]. As the technology node advances, new integration schemes have to be used for the patterning of features below 80 nm pitch with 193 nm immersion lithography. In particular, thicker TiN-HM is necessary in order to ensure Self-Aligned-Via (SAV) integration which resolves via-metal short yield and TDDB issues caused by Litho-Etch-Litho-Etch (LELE) misalignment [2, 3]. The Cu filling process is significantly more difficult if the thick TiN is not removed because of the high aspect ratio of the structures. Moreover, with the use of TiN hard mask, a time-dependent crystal growth (TiCOF) residue may forms between line etch and metal deposition [4, 5], also hindering copper filling. Post-Etch-Treatment after line etching is one solution to the problem but N2plasma is not efficient enough to suppress the residue completely [6], and the CH4treatment proposed in [5] may be difficult to implement for 14 nm node, thus an efficient wet strip and clean provides a better solution.

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50

Chenyun Pan, Praveen Raghavan, Ahmet Ceyhan, Francky Catthoor, Zsolt Tokei y Azad Naeemi. "Technology/Circuit/System Co-Optimization and Benchmarking for Multilayer Graphene Interconnects at Sub-10-nm Technology Node". IEEE Transactions on Electron Devices 62, n.º 5 (mayo de 2015): 1530–36. http://dx.doi.org/10.1109/ted.2015.2409875.

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