Artículos de revistas sobre el tema "Multiply and accumulate"
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Pawar, Roshani y Dr S. S. Shriramwar. "Review on Multiply-Accumulate Unit". International Journal of Engineering Research and Applications 07, n.º 06 (junio de 2017): 09–13. http://dx.doi.org/10.9790/9622-0706040913.
Texto completoLee, Young Seo, Kyung Min Kim, Ji Heon Lee, Young-Ho Gong, Seon Wook Kim y Sung Woo Chung. "Monolithic 3D stacked multiply-accumulate units". Integration 76 (enero de 2021): 183–89. http://dx.doi.org/10.1016/j.vlsi.2020.10.006.
Texto completoMohammaden, Amr, Mohammed Fouda, Ihsen Alouani, Lobna A. Said y Ahmed Radwan. "CNTFET-Based Ternary Multiply-and-Accumulate Unit". Electronics 11, n.º 9 (30 de abril de 2022): 1455. http://dx.doi.org/10.3390/electronics11091455.
Texto completoNahmias, Mitchell A., Thomas Ferreira de Lima, Alexander N. Tait, Hsuan-Tung Peng, Bhavin J. Shastri y Paul R. Prucnal. "Photonic Multiply-Accumulate Operations for Neural Networks". IEEE Journal of Selected Topics in Quantum Electronics 26, n.º 1 (enero de 2020): 1–18. http://dx.doi.org/10.1109/jstqe.2019.2941485.
Texto completoHG, Rangaraju, Arpitha H S y Muralidhara K N. "Design of Efficient Reversible Multiply Accumulate (MAC) Unit". International Journal of Computer Applications 85, n.º 16 (16 de enero de 2014): 1–12. http://dx.doi.org/10.5120/14922-3338.
Texto completoKashfi, Fatemeh, S. Mehdi Fakhraie y Saeed Safari. "Designing an ultra-high-speed multiply-accumulate structure". Microelectronics Journal 39, n.º 12 (diciembre de 2008): 1476–84. http://dx.doi.org/10.1016/j.mejo.2008.07.006.
Texto completoIsrael, Scott, Steven C. Gustafson y Edmond S. Cooley. "Asynchronous integrated optical multiply accumulate with sideways summer". Applied Optics 25, n.º 14 (15 de julio de 1986): 2284. http://dx.doi.org/10.1364/ao.25.002284.
Texto completoNielsen, Christian D. y Alain J. Martin. "Design of a delay-insensitive multiply-accumulate unit". Integration 15, n.º 3 (octubre de 1993): 291–311. http://dx.doi.org/10.1016/0167-9260(93)90034-a.
Texto completoBhuvaneswary, N., S. Prabu, K. Tamilselvan y K. G. Parthiban. "Efficient Implementation of Multiply Accumulate Operation Unit Using an Interlaced Partition Multiplier". Journal of Computational and Theoretical Nanoscience 18, n.º 4 (1 de abril de 2021): 1321–26. http://dx.doi.org/10.1166/jctn.2021.9398.
Texto completoLiu, Xu, Xudong Zhu, Chunqing Wang, Yifan Cao, Baihang Wang, Hanwen Ou, Yizheng Wu et al. "Silicon-Based Metastructure Optical Scattering Multiply–Accumulate Computation Chip". Nanomaterials 12, n.º 13 (21 de junio de 2022): 2136. http://dx.doi.org/10.3390/nano12132136.
Texto completoKuang, S. R. y J. P. Wang. "Low-error configurable truncated multipliers for multiply-accumulate applications". Electronics Letters 42, n.º 16 (2006): 904. http://dx.doi.org/10.1049/el:20061812.
Texto completoKataeva, Irina, Henrik Engseth y Anna Kidiyarova-Shevchenko. "New design of an RSFQ parallel multiply–accumulate unit". Superconductor Science and Technology 19, n.º 5 (16 de marzo de 2006): S381—S386. http://dx.doi.org/10.1088/0953-2048/19/5/s45.
Texto completoRathore, Mallika, Peter Milder y Emre Salman. "Error Probability Models for Voltage-Scaled Multiply-Accumulate Units". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, n.º 7 (julio de 2020): 1665–75. http://dx.doi.org/10.1109/tvlsi.2020.2988204.
Texto completoChen, Jia, Jiancong Li, Yi Li y Xiangshui Miao. "Multiply accumulate operations in memristor crossbar arrays for analog computing". Journal of Semiconductors 42, n.º 1 (1 de enero de 2021): 013104. http://dx.doi.org/10.1088/1674-4926/42/1/013104.
Texto completoChikkani, Rajyalakshmi. "VLSI Implementation of Multiply and Accumulate Unit Using Distributed Arithmetic". Bioscience Biotechnology Research Communications 13, n.º 15 (25 de diciembre de 2020): 212–17. http://dx.doi.org/10.21786/bbrc/13.15/37.
Texto completoIrwin, D. "A multiply-and-accumulate selection algorithm for dynamic entropy coding". ACM SIGCOMM Computer Communication Review 16, n.º 1 (febrero de 1986): 5–12. http://dx.doi.org/10.1145/15703.15704.
Texto completoDanysh, A. y D. Tan. "Architecture and implementation of a vector/SIMD multiply-accumulate unit". IEEE Transactions on Computers 54, n.º 3 (marzo de 2005): 284–93. http://dx.doi.org/10.1109/tc.2005.41.
Texto completoBunyk, P. I., Q. P. Herr y M. W. Johnson. "Demonstration of Multiply-Accumulate Unit for Programmable Band-Pass ADC". IEEE Transactions on Appiled Superconductivity 15, n.º 2 (junio de 2005): 392–95. http://dx.doi.org/10.1109/tasc.2005.849858.
Texto completoMasadeh, Mahmoud, Osman Hasan y Sofiene Tahar. "Input-Conscious Approximate Multiply-Accumulate (MAC) Unit for Energy-Efficiency". IEEE Access 7 (2019): 147129–42. http://dx.doi.org/10.1109/access.2019.2946513.
Texto completoMohamed Asan Basiri, M. y S. k. Noor Mohammad. "Quadruple throughput fixed point quarter precision multiply accumulate circuit design". IET Computers & Digital Techniques 11, n.º 5 (7 de agosto de 2017): 183–89. http://dx.doi.org/10.1049/iet-cdt.2017.0051.
Texto completoDinah, Shalo Thanga y V. Jeyalakshm. "High Performance Multiply Accumulate (MAC) Unit Based FIR Filter Design". International Journal of Applied Engineering Research 17, n.º 6 (30 de diciembre de 2022): 565–72. http://dx.doi.org/10.37622/ijaer/17.6.2022.565-572.
Texto completoZhang, Hao, Dongdong Chen y Seok-Bum Ko. "New Flexible Multiple-Precision Multiply-Accumulate Unit for Deep Neural Network Training and Inference". IEEE Transactions on Computers 69, n.º 1 (1 de enero de 2020): 26–38. http://dx.doi.org/10.1109/tc.2019.2936192.
Texto completoSarma, Rajkumar, Cherry Bhargava y Ketan Kotecha. "An Evolutionary Normalization Algorithm for Signed Floating-Point Multiply-Accumulate Operation". Computers, Materials & Continua 72, n.º 1 (2022): 481–95. http://dx.doi.org/10.32604/cmc.2022.024516.
Texto completoS, Saravanan y Madheswaran M. "MODIFIED MULTIPLY-ACCUMULATE ARCHITECTURE WITH THE SWITCHING POWER SWIFTNESS IMPROVEMENT TECHNIQUE". International Journal on Intelligent Electronic Systems 2, n.º 1 (2008): 80–85. http://dx.doi.org/10.18000/ijies.30029.
Texto completoGarland, James y David Gregg. "Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks". IEEE Computer Architecture Letters 16, n.º 2 (1 de julio de 2017): 132–35. http://dx.doi.org/10.1109/lca.2017.2656880.
Texto completoMcGovern, B. P., R. F. Woods y C. McAllister. "Optimised multiply/accumulate architecture for very high throughput rate digital filters". Electronics Letters 31, n.º 14 (1995): 1135. http://dx.doi.org/10.1049/el:19950823.
Texto completoChen, Ke, Linbin Chen, Pedro Reviriego y Fabrizio Lombardi. "Efficient Implementations of Reduced Precision Redundancy (RPR) Multiply and Accumulate (MAC)". IEEE Transactions on Computers 68, n.º 5 (1 de mayo de 2019): 784–90. http://dx.doi.org/10.1109/tc.2018.2885044.
Texto completoChhajed, Harsh, Gopal Raut, Narendra Dhakad, Sudheer Vishwakarma y Santosh Kumar Vishvakarma. "BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator". Circuits, Systems, and Signal Processing 41, n.º 4 (8 de enero de 2022): 2045–60. http://dx.doi.org/10.1007/s00034-021-01873-9.
Texto completoRyu, Sungju, Naebeom Park y Jae-Joon Kim. "Feedforward-Cutset-Free Pipelined Multiply–Accumulate Unit for the Machine Learning Accelerator". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27, n.º 1 (enero de 2019): 138–46. http://dx.doi.org/10.1109/tvlsi.2018.2873716.
Texto completoSmith, S. C., R. F. DeMara, J. S. Yuan, M. Hagedorn y D. Ferguson. "NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation". Journal of Systems Architecture 47, n.º 12 (junio de 2002): 977–98. http://dx.doi.org/10.1016/s1383-7621(02)00060-7.
Texto completoGarland, James y David Gregg. "Low Complexity Multiply-Accumulate Units for Convolutional Neural Networks with Weight-Sharing". ACM Transactions on Architecture and Code Optimization 15, n.º 3 (8 de octubre de 2018): 1–24. http://dx.doi.org/10.1145/3233300.
Texto completoCai, Fuxi, Justin M. Correll, Seung Hwan Lee, Yong Lim, Vishishtha Bothra, Zhengya Zhang, Michael P. Flynn y Wei D. Lu. "A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations". Nature Electronics 2, n.º 7 (julio de 2019): 290–99. http://dx.doi.org/10.1038/s41928-019-0270-x.
Texto completoCho, Mannhee y Youngmin Kim. "FPGA-Based Convolutional Neural Network Accelerator with Resource-Optimized Approximate Multiply-Accumulate Unit". Electronics 10, n.º 22 (19 de noviembre de 2021): 2859. http://dx.doi.org/10.3390/electronics10222859.
Texto completoLyakhov, Pavel, Maria Valueva, Georgii Valuev y Nikolai Nagornov. "A Method of Increasing Digital Filter Performance Based on Truncated Multiply-Accumulate Units". Applied Sciences 10, n.º 24 (18 de diciembre de 2020): 9052. http://dx.doi.org/10.3390/app10249052.
Texto completoSmith, S. C. "Development of a large word-width high-speed asynchronous multiply and accumulate unit". Integration 39, n.º 1 (septiembre de 2005): 12–28. http://dx.doi.org/10.1016/j.vlsi.2004.11.001.
Texto completoEzilarasan, M. R., J. Britto Pari y Man-Fai Leung. "Reconfigurable Architecture for Noise Cancellation in Acoustic Environment Using Single Multiply Accumulate Adaline Filter". Electronics 12, n.º 4 (6 de febrero de 2023): 810. http://dx.doi.org/10.3390/electronics12040810.
Texto completoYuyun Liao y D. B. Roberts. "A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature". IEEE Journal of Solid-State Circuits 37, n.º 7 (julio de 2002): 926–31. http://dx.doi.org/10.1109/jssc.2002.1015692.
Texto completoS, Rakesh y K. S. Vijula Grace. "Power Efficient Multiply Accumulate Architectures using Modified Parallel Prefix Adders for Low Power Applications". International Journal of Computing and Digital Systems 9, n.º 4 (1 de julio de 2020): 615–23. http://dx.doi.org/10.12785/ijcds/090409.
Texto completoNakahara, Yasuhiro, Yuta Masuda, Masato Kiyama, Motoki Amagasaki y Masahiro Iida. "A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks". IPSJ Transactions on System LSI Design Methodology 15 (2022): 16–19. http://dx.doi.org/10.2197/ipsjtsldm.15.16.
Texto completoSrikanth, I. y S. Aunmetha. "High Level Synchronization and Computations of Feed Forward Cut-Set based Multiply Accumulate Unit". Journal of Physics: Conference Series 1804, n.º 1 (1 de febrero de 2021): 012201. http://dx.doi.org/10.1088/1742-6596/1804/1/012201.
Texto completoLyakhov, Pavel, Maria Valueva, Georgii Valuev y Nikolai Nagornov. "High-Performance Digital Filtering on Truncated Multiply-Accumulate Units in the Residue Number System". IEEE Access 8 (2020): 209181–90. http://dx.doi.org/10.1109/access.2020.3038496.
Texto completoJeon, Dong-Ik, Kyeong-Bin Park y Ki-Seok Chung. "HMC-MAC: Processing-in Memory Architecture for Multiply-Accumulate Operations with Hybrid Memory Cube". IEEE Computer Architecture Letters 17, n.º 1 (1 de enero de 2018): 5–8. http://dx.doi.org/10.1109/lca.2017.2700298.
Texto completoParameswar, A., H. Hara y T. Sakurai. "A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications". IEEE Journal of Solid-State Circuits 31, n.º 6 (junio de 1996): 804–9. http://dx.doi.org/10.1109/4.509866.
Texto completoTatas, K., G. Koutroumpezis, D. Soudris y A. Thanailakis. "Architecture design of a coarse-grain reconfigurable multiply-accumulate unit for data-intensive applications". Integration 40, n.º 2 (febrero de 2007): 74–93. http://dx.doi.org/10.1016/j.vlsi.2006.02.011.
Texto completoLa Guia de Solaz, Manuel y Richard Conway. "Razor Based Programmable Truncated Multiply and Accumulate, Energy-Reduction for Efficient Digital Signal Processing". IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, n.º 1 (enero de 2015): 189–93. http://dx.doi.org/10.1109/tvlsi.2014.2300173.
Texto completoDemasius, Kai-Uwe, Aron Kirschen y Stuart Parkin. "Energy-efficient memcapacitor devices for neuromorphic computing". Nature Electronics 4, n.º 10 (octubre de 2021): 748–56. http://dx.doi.org/10.1038/s41928-021-00649-y.
Texto completoGiacomin, Edouard, Sumanth Gudaparthi, Juergen Boemmels, Rajeev Balasubramonian, Francky Catthoor y Pierre-Emmanuel Gaillardon. "A Multiply-and-Accumulate Array for Machine Learning Applications Based on a 3D Nanofabric Flow". IEEE Transactions on Nanotechnology 20 (2021): 873–82. http://dx.doi.org/10.1109/tnano.2021.3132224.
Texto completoKao, J. T., M. Miyazaki y A. R. Chandrakasan. "A 175-MV multiply-accumulate unit using an adaptive supply voltage and body bias architecture". IEEE Journal of Solid-State Circuits 37, n.º 11 (noviembre de 2002): 1545–54. http://dx.doi.org/10.1109/jssc.2002.803957.
Texto completoCamus, Vincent, Linyan Mei, Christian Enz y Marian Verhelst. "Review and Benchmarking of Precision-Scalable Multiply-Accumulate Unit Architectures for Embedded Neural-Network Processing". IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9, n.º 4 (diciembre de 2019): 697–711. http://dx.doi.org/10.1109/jetcas.2019.2950386.
Texto completoKENNEDY, MICHAEL PETER, CHAI WAH WU, STANLEY PAU y JAMES TOW. "DIGITAL SIGNAL PROCESSOR-BASED INVESTIGATION OF CHUA'S CIRCUIT FAMILY". Journal of Circuits, Systems and Computers 03, n.º 02 (junio de 1993): 269–92. http://dx.doi.org/10.1142/s0218126693000204.
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