Artículos de revistas sobre el tema "MULTIPLIER CIRCUIT"
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Ganjikunta, Ganesh Kumar, Sibghatullah I. Khan y M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics". Journal of Low Power Electronics 15, n.º 3 (1 de septiembre de 2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.
Texto completoLeela, S. Naga, Boppa Manisha, Palle Bharath y Erram Praneeth. "Design of Wallace tree multiplier circuit using high performance and low power full adder". E3S Web of Conferences 391 (2023): 01025. http://dx.doi.org/10.1051/e3sconf/202339101025.
Texto completoSenthil Kumar, K. K., R. Vignesh, V. R. Vivek, Jagdish Prasad Ahirwar, Khamdamova Makhzuna y R. Ram kumar. "Approximate Multiplier based on Low power and reduced latency with Modified LSB design". E3S Web of Conferences 399 (2023): 01009. http://dx.doi.org/10.1051/e3sconf/202339901009.
Texto completoYang, Zhixi, Xianbin Li y Jun Yang. "Power Efficient and High-Accuracy Approximate Multiplier with Error Correction". Journal of Circuits, Systems and Computers 29, n.º 15 (30 de junio de 2020): 2050241. http://dx.doi.org/10.1142/s0218126620502412.
Texto completoHAGHPARAST, MAJID, MAJID MOHAMMADI, KEIVAN NAVI y MOHAMMAD ESHGHI. "OPTIMIZED REVERSIBLE MULTIPLIER CIRCUIT". Journal of Circuits, Systems and Computers 18, n.º 02 (abril de 2009): 311–23. http://dx.doi.org/10.1142/s0218126609005083.
Texto completoSubbaiah, Madaka Venkata y Galiveeti Umamaheswara Reddy. "Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier". International Journal of Electrical and Computer Engineering (IJECE) 13, n.º 2 (1 de abril de 2023): 1367. http://dx.doi.org/10.11591/ijece.v13i2.pp1367-1378.
Texto completoRashno, Meysam, Majid Haghparast y Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier". International Journal of Quantum Information 18, n.º 03 (abril de 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.
Texto completoAaron D’costa, Mr, Dr Abdul Razak y Dr Shazia Hasan. "Analysis and comparison of fast multiplier circuits based on different parameters". International Journal of Engineering & Technology 7, n.º 3 (26 de junio de 2018): 1189. http://dx.doi.org/10.14419/ijet.v7i3.12945.
Texto completoAbdulbaqia, Alaa Ghazi y Yasir Hashim. "Design and Implementation of General Hardware Binary Multiplier (2n x 2n) Bits". Journal of Physics: Conference Series 2312, n.º 1 (1 de agosto de 2022): 012084. http://dx.doi.org/10.1088/1742-6596/2312/1/012084.
Texto completoCHEN, YUAN-HO, CHIH-WEN LU, SHIAN-SHING SHYU, CHUNG-LIN LEE y TING-CHIA OU. "A MULTI-STAGE FAULT-TOLERANT MULTIPLIER WITH TRIPLE MODULE REDUNDANCY (TMR) TECHNIQUE". Journal of Circuits, Systems and Computers 23, n.º 05 (8 de mayo de 2014): 1450074. http://dx.doi.org/10.1142/s0218126614500741.
Texto completoWeikle, R. M., T. W. Crowe y E. L. Kollberg. "Multiplier and Harmonic Generator Technologies for Terahertz Applications". International Journal of High Speed Electronics and Systems 13, n.º 02 (junio de 2003): 429–56. http://dx.doi.org/10.1142/s012915640300179x.
Texto completoLoganayaki, J. y M. Vasanthi. "Image Multiplier Based on Low Power Approximate Unsigned Multiplier". International Journal of Advance Research and Innovation 7, n.º 2 (2019): 50–56. http://dx.doi.org/10.51976/ijari.721907.
Texto completoReis, Cecília, J. A. Tenreiro Machado y J. Boaventura Cunha. "Evolutionary Design of Combinational Logic Circuits". Journal of Advanced Computational Intelligence and Intelligent Informatics 8, n.º 5 (20 de septiembre de 2004): 507–13. http://dx.doi.org/10.20965/jaciii.2004.p0507.
Texto completoSuvarna, S., K. Rajesh y T. Radhu. "A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic". International Journal of Students' Research in Technology & Management 4, n.º 1 (10 de marzo de 2016): 01–05. http://dx.doi.org/10.18510/ijsrtm.2016.411.
Texto completoMonfared, Asma Taheri y Majid Haghparast. "Quantum Ternary Multiplication Gate (QTMG): Toward Quantum Ternary Multiplier and a New Realization for Ternary Toffoli Gate". Journal of Circuits, Systems and Computers 29, n.º 05 (3 de julio de 2019): 2050071. http://dx.doi.org/10.1142/s0218126620500711.
Texto completoJagadeeswara Rao, E., K. Jayaram Kumar y Dr T. V. Prasad. "Design of high speed Wallace tree multiplier using 8-2 and 4-2 adder compressors". International Journal of Engineering & Technology 7, n.º 4 (17 de septiembre de 2018): 2386. http://dx.doi.org/10.14419/ijet.v7i4.12261.
Texto completoChen, Wei Ping, Tian Yang Wang, Hong Lei Xu y Xiao Wei Liu. "A Four-Quadrant Analog Multiplier Based on CMOS Source Coupled Pair". Key Engineering Materials 483 (junio de 2011): 487–91. http://dx.doi.org/10.4028/www.scientific.net/kem.483.487.
Texto completoMaheswari, K., M. L. Ravi Chandra, D. Srinivasulu Reddy y V. Vijaya Kishore. "Design of Three-valued Logic Based Adder and Multiplier Circuits using Pseudo N-type CNTFETs". International Journal of Electrical and Electronics Research 11, n.º 2 (30 de junio de 2023): 518–22. http://dx.doi.org/10.37391/ijeer.110238.
Texto completoEissa, M. H., A. Malignaggi, M. Ko, K. Schmalz, J. Borngräber, A. C. Ulusoy y D. Kissinger. "A 216–256 GHz fully differential frequency multiplier-by-8 chain with 0 dBm output power". International Journal of Microwave and Wireless Technologies 10, n.º 5-6 (5 de marzo de 2018): 562–69. http://dx.doi.org/10.1017/s1759078718000235.
Texto completoSAKUL, CHAIWAT y KOBCHAI DEJHAN. "FLIPPED VOLTAGE FOLLOWER ANALOG NONLINEAR CIRCUITS". Journal of Circuits, Systems and Computers 21, n.º 03 (mayo de 2012): 1250024. http://dx.doi.org/10.1142/s0218126612500247.
Texto completoOsta, Mario, Ali Ibrahim y Maurizio Valle. "Approximate Computing Circuits for Embedded Tactile Data Processing". Electronics 11, n.º 2 (8 de enero de 2022): 190. http://dx.doi.org/10.3390/electronics11020190.
Texto completoBhusare, Saroja S. y V. S. Kanchana Bhaaskaran. "Low-Power High-Accuracy Fixed-Width Radix-8 Booth Multiplier Using Probabilistic Estimation Technique". Journal of Circuits, Systems and Computers 26, n.º 05 (8 de febrero de 2017): 1750079. http://dx.doi.org/10.1142/s0218126617500797.
Texto completoRayudu, Kurada Verra Bhoga Vasantha, Dhananjay Ramachandra Jahagirdar y Patri Srihari Rao. "Design and testing of systolic array multiplier using fault injecting schemes". Computer Science and Information Technologies 3, n.º 1 (1 de marzo de 2022): 1–9. http://dx.doi.org/10.11591/csit.v3i1.p1-9.
Texto completoPerisic, D. M., A. C. Zoric y Z. Gavric. "A Frequency Multiplier Based on Time Recursive Processing". Engineering, Technology & Applied Science Research 7, n.º 6 (18 de diciembre de 2017): 2104–8. http://dx.doi.org/10.48084/etasr.1499.
Texto completoSadeghi, Mohsen, Mahya Zahedi y Maaruf Ali. "The Cascade Carry Array Multiplier – A Novel Structure of Digital Unsigned Multipliers for Low-Power Consumption and Ultra-Fast Applications". Annals of Emerging Technologies in Computing 3, n.º 3 (1 de julio de 2019): 19–27. http://dx.doi.org/10.33166/aetic.2019.03.003.
Texto completoDattatraya, Kore Sagar, Belgudri Ritesh Appasaheb, Ramdas Bhanudas Khaladkar y V. S. Kanchana Bhaaskaran. "Low Power, High Speed and Area Efficient Binary Count Multiplier". Journal of Circuits, Systems and Computers 25, n.º 04 (2 de febrero de 2016): 1650027. http://dx.doi.org/10.1142/s0218126616500274.
Texto completoDurgam, Veena y Dr K. Ragini. "Design of 32x32 Reversible Unsigned Multiplier Using Dadda Tree Algorithm". ECS Transactions 107, n.º 1 (24 de abril de 2022): 16251–58. http://dx.doi.org/10.1149/10701.16251ecst.
Texto completoWang, Yong Xi y Mei Hu. "Analog Circuit Parameters Measurement System Based on Multiplier". Advanced Materials Research 989-994 (julio de 2014): 3041–44. http://dx.doi.org/10.4028/www.scientific.net/amr.989-994.3041.
Texto completoBibilo, P. N. "Synthesis of Modular Multipliers". Programmnaya Ingeneria 14, n.º 8 (14 de agosto de 2023): 377–87. http://dx.doi.org/10.17587/prin.14.377-387.
Texto completoWasaki, H., Y. Horio y S. Nakamura. "Current multiplier/divider circuit". Electronics Letters 27, n.º 6 (1991): 504. http://dx.doi.org/10.1049/el:19910317.
Texto completoPERRI, STEFANIA, MARIA ANTONIA IACHINO y PASQUALE CORSONELLO. "SIMD MULTIPLIERS FOR ACCELERATING EMBEDDED PROCESSORS IN FPGAs". Journal of Circuits, Systems and Computers 15, n.º 04 (agosto de 2006): 537–50. http://dx.doi.org/10.1142/s0218126606003210.
Texto completoMelnyk, Oleksandr, Maksym Kravets y Valerii Kravets. "Comparative Computer Design of Four-bits Nanomultiplier". Electronics and Control Systems 3, n.º 73 (24 de noviembre de 2022): 59–64. http://dx.doi.org/10.18372/1990-5548.73.17014.
Texto completoReaungepattanawiwat, Chalermpol y Yutthana Kanthaphayao. "Voltage Multiplier Circuits with Coupled-Inductor Applied to a High Step-Up DC-DC Converter". Applied Mechanics and Materials 781 (agosto de 2015): 418–21. http://dx.doi.org/10.4028/www.scientific.net/amm.781.418.
Texto completoAl-Khaleel, Osama, Zakaria Al-Qudah, Mohammad Al-Khaleel, Raed Bani-Hani, Christos Papachristou y Francis Wolff. "Efficient Hardware Implementations of Binary-to-BCD Conversion Schemes for Decimal Multiplication". Journal of Circuits, Systems and Computers 24, n.º 02 (27 de noviembre de 2014): 1550019. http://dx.doi.org/10.1142/s021812661550019x.
Texto completoKaufmann, Daniela, Armin Biere y Manuel Kauers. "Incremental column-wise verification of arithmetic circuits using computer algebra". Formal Methods in System Design 56, n.º 1-3 (26 de febrero de 2019): 22–54. http://dx.doi.org/10.1007/s10703-018-00329-2.
Texto completoSaini, Jitendra Kumar, Avireni Srinivasulu y Renu Kumawat. "High-Performance Low-Power 5:2 Compressor With 30 CNTFETs Using 32 nm Technology". International Journal of Sensors, Wireless Communications and Control 9, n.º 4 (17 de septiembre de 2019): 462–67. http://dx.doi.org/10.2174/2210327909666190206144601.
Texto completoLakshmi, Mutyala Sri Anantha. "Design and Implementation of Radix 8 Booth Encoding Multiplier for Low Area and High-Speed Applications". International Journal for Research in Applied Science and Engineering Technology 9, n.º 12 (31 de diciembre de 2021): 862–64. http://dx.doi.org/10.22214/ijraset.2021.39398.
Texto completoA V, Arun. "Column Bypassing Multiplier Implementation on FPGA". International Journal for Research in Applied Science and Engineering Technology 10, n.º 6 (30 de junio de 2022): 3427–41. http://dx.doi.org/10.22214/ijraset.2022.44628.
Texto completoLin, Jin-Fa, Cheng-Yu Chan y Shao-Wei Yu. "Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications". Electronics 8, n.º 12 (30 de noviembre de 2019): 1429. http://dx.doi.org/10.3390/electronics8121429.
Texto completoDündar, G., F.-C. Hsu y K. Rose. "Effects of Nonlinear Synapses on the Performance of Multilayer Neural Networks". Neural Computation 8, n.º 5 (julio de 1996): 939–49. http://dx.doi.org/10.1162/neco.1996.8.5.939.
Texto completoGlushechenko, E. N. "Microstrip doubler microwave with non-traditional implementation". Технология и конструирование в электронной аппаратуре, n.º 1-2 (2019): 20–26. http://dx.doi.org/10.15222/tkea2019.1-2.20.
Texto completoVozna, Natalia, Yaroslav Nykolaychuk y Alina Davletova. "Multi-bit structure improvement methods for multiplier devices of matrix type". Physico-mathematical modelling and informational technologies, n.º 32 (7 de julio de 2021): 80–85. http://dx.doi.org/10.15407/fmmit2021.32.080.
Texto completoUpadhyay, Shipra, R. K. Nagaria y R. A. Mishra. "Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic". VLSI Design 2013 (7 de noviembre de 2013): 1–9. http://dx.doi.org/10.1155/2013/726324.
Texto completoKeote, Minal y P. T. Karule. "Design and Implementation of Low Power Multiplier Using Proposed Two Phase Clocked Adiabatic Static CMOS Logic Circuit". International Journal of Electrical and Computer Engineering (IJECE) 8, n.º 6 (1 de diciembre de 2018): 4959. http://dx.doi.org/10.11591/ijece.v8i6.pp4959-4971.
Texto completoZhou, Duo. "The Design of Multiplier in Integrated Circuit Based on Low-Power Algorithm". Applied Mechanics and Materials 624 (agosto de 2014): 385–88. http://dx.doi.org/10.4028/www.scientific.net/amm.624.385.
Texto completoLi, Yin, Yu Zhang y Xiaoli Guo. "Efficient Nonrecursive Bit-Parallel Karatsuba Multiplier for a Special Class of Trinomials". VLSI Design 2018 (11 de enero de 2018): 1–7. http://dx.doi.org/10.1155/2018/9269157.
Texto completoYan, Aibin, Xuehua Li, Runqi Liu, Zhengfeng Huang, Patrick Girard y Xiaoqing Wen. "Designs of Array Multipliers with an Optimized Delay in Quantum-Dot Cellular Automata". Electronics 12, n.º 14 (23 de julio de 2023): 3189. http://dx.doi.org/10.3390/electronics12143189.
Texto completoSafoev, Nuriddin y Jun-Cheol Jeon. "Design and Evaluation of Cell Interaction Based Vedic Multiplier Using Quantum-Dot Cellular Automata". Electronics 9, n.º 6 (23 de junio de 2020): 1036. http://dx.doi.org/10.3390/electronics9061036.
Texto completoSwathi, Panchadi y Gudla Bhanu Gupta. "Implementation of 2-bit Multiplier Circuit Using Pass Transistor Logic". International Journal for Research in Applied Science and Engineering Technology 10, n.º 7 (31 de julio de 2022): 5013–22. http://dx.doi.org/10.22214/ijraset.2022.46100.
Texto completoZhu, R., Y. Zhang, J. Luo, S. Chang, Hao Wang, Q. Huang y Jin He. "Graphene Field Effect Transistor’s Circuit Modeling and Radio Frequency Application Study". Key Engineering Materials 645-646 (mayo de 2015): 139–44. http://dx.doi.org/10.4028/www.scientific.net/kem.645-646.139.
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