Literatura académica sobre el tema "MULTIPLIER CIRCUIT"
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Artículos de revistas sobre el tema "MULTIPLIER CIRCUIT"
Ganjikunta, Ganesh Kumar, Sibghatullah I. Khan y M. Mahaboob Basha. "A High-Performance Signed-Unsigned Multiplier Using Vedic Mathematics". Journal of Low Power Electronics 15, n.º 3 (1 de septiembre de 2019): 302–8. http://dx.doi.org/10.1166/jolpe.2019.1616.
Texto completoLeela, S. Naga, Boppa Manisha, Palle Bharath y Erram Praneeth. "Design of Wallace tree multiplier circuit using high performance and low power full adder". E3S Web of Conferences 391 (2023): 01025. http://dx.doi.org/10.1051/e3sconf/202339101025.
Texto completoSenthil Kumar, K. K., R. Vignesh, V. R. Vivek, Jagdish Prasad Ahirwar, Khamdamova Makhzuna y R. Ram kumar. "Approximate Multiplier based on Low power and reduced latency with Modified LSB design". E3S Web of Conferences 399 (2023): 01009. http://dx.doi.org/10.1051/e3sconf/202339901009.
Texto completoYang, Zhixi, Xianbin Li y Jun Yang. "Power Efficient and High-Accuracy Approximate Multiplier with Error Correction". Journal of Circuits, Systems and Computers 29, n.º 15 (30 de junio de 2020): 2050241. http://dx.doi.org/10.1142/s0218126620502412.
Texto completoHAGHPARAST, MAJID, MAJID MOHAMMADI, KEIVAN NAVI y MOHAMMAD ESHGHI. "OPTIMIZED REVERSIBLE MULTIPLIER CIRCUIT". Journal of Circuits, Systems and Computers 18, n.º 02 (abril de 2009): 311–23. http://dx.doi.org/10.1142/s0218126609005083.
Texto completoSubbaiah, Madaka Venkata y Galiveeti Umamaheswara Reddy. "Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier". International Journal of Electrical and Computer Engineering (IJECE) 13, n.º 2 (1 de abril de 2023): 1367. http://dx.doi.org/10.11591/ijece.v13i2.pp1367-1378.
Texto completoRashno, Meysam, Majid Haghparast y Mohammad Mosleh. "A new design of a low-power reversible Vedic multiplier". International Journal of Quantum Information 18, n.º 03 (abril de 2020): 2050002. http://dx.doi.org/10.1142/s0219749920500021.
Texto completoAaron D’costa, Mr, Dr Abdul Razak y Dr Shazia Hasan. "Analysis and comparison of fast multiplier circuits based on different parameters". International Journal of Engineering & Technology 7, n.º 3 (26 de junio de 2018): 1189. http://dx.doi.org/10.14419/ijet.v7i3.12945.
Texto completoAbdulbaqia, Alaa Ghazi y Yasir Hashim. "Design and Implementation of General Hardware Binary Multiplier (2n x 2n) Bits". Journal of Physics: Conference Series 2312, n.º 1 (1 de agosto de 2022): 012084. http://dx.doi.org/10.1088/1742-6596/2312/1/012084.
Texto completoCHEN, YUAN-HO, CHIH-WEN LU, SHIAN-SHING SHYU, CHUNG-LIN LEE y TING-CHIA OU. "A MULTI-STAGE FAULT-TOLERANT MULTIPLIER WITH TRIPLE MODULE REDUNDANCY (TMR) TECHNIQUE". Journal of Circuits, Systems and Computers 23, n.º 05 (8 de mayo de 2014): 1450074. http://dx.doi.org/10.1142/s0218126614500741.
Texto completoTesis sobre el tema "MULTIPLIER CIRCUIT"
Tang, Wing Ho Aaron. "Optimum MESFET frequency multiplier design". Thesis, Queen's University Belfast, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.239221.
Texto completoComerma, Montells Albert. "Development of a multichannel integrated circuit for Silicon Photo-Multiplier arrays readout". Doctoral thesis, Universitat de Barcelona, 2014. http://hdl.handle.net/10803/134876.
Texto completoL’objectiu d’aquesta tesi és presentar una solució per a la lectura de matrius de fotomultiplicadors de silici (SiPM) millorant les característiques de sistemes actuals. Amb aquesta finalitat s’ha dissenyat i provat el circuit d’una nova etapa d’entrada. En primer lloc s’ha dissenyat pensant en aplicacions genèriques i per a imatge mèdica, concretament per a escàners PET (Positron Emission Tomography). Però més endavant s’aplica la mateixa topologia per a una aplicació més concreta i específica com és un detector de partícules (l’actualització del Tracker a l’experiment LHCb). Els SiPM són uns dispositius electrònics relativament nous amb la possibilitat de comptar fotons i millorant algunes característiques dels sensors actuals, com serien la tensió d’operació més baixa, més guany o immunitat a camps magn`etics, mentre manté unes prestacions excel•lents respecte el guany, resolució temporal i rang dinàmic. Aquest tipus de dispositius es troben en constant evolució encara i una gran varietat de fabricants intenten millorar les prestacions, sobretot respecte la eficiència en la detecció de llum, reduir el corrent d’obscuritat, construir matrius més grans i augmentar l’espectre al qual són sensibles. En aquest document es presenta el disseny d’un circuit integrat específic amb les següents característiques: gran rang dinàmic, alta velocitat, multicanal, amb entrada en corrent i baixa impedància d’entrada, baix consum, control de la tensió de polarització del SiPM i amb les sortides de; temps, càrrega i apilament.
Srinivasan, Venkataramanujam. "Gigahertz-Range Multiplier Architectures Using MOS Current Mode Logic (MCML)". Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/9643.
Texto completoMaster of Science
Ramasamy, Lakshminarayanan. "First Order Mobility Independent ASIC for a Point-of-Care In-Vitro Diagnostic Device". University of Cincinnati / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1326296847.
Texto completoEl, Hassan Bachar. "Architecture VLSI asynchrone utilisant la logique différentielle à précharge : application aux opérateurs arithmétiques". Grenoble INPG, 1995. http://www.theses.fr/1995INPG0099.
Texto completoRemund, Craig Timothy. "Design of CMOS Four-Quadrant Gilbert Cell Multiplier Circuits in Weak and Moderate Inversion". Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd611.pdf.
Texto completoOzalevli, Erhan. "Exploiting Floating-Gate Transistor Properties in Analog and Mixed-Signal Circuit Design". Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/14048.
Texto completoNormand, Guy. "Les circuits translineaires : contribution a leur etude et a leur mise en oeuvre dans les domaines analogique et logique". Nantes, 1987. http://www.theses.fr/1987NANT2056.
Texto completoChoudens, Philippe de. "Test intégré de processeur facilement testable". Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00319265.
Texto completoTang, Guang-ming. "Studies on Datapath Circuits for Superconductor Bit-Slice Microprocessors". 京都大学 (Kyoto University), 2016. http://hdl.handle.net/2433/217208.
Texto completoLibros sobre el tema "MULTIPLIER CIRCUIT"
Kursun, Volkan. Multiple-voltage CMOS circuit design. Chichester, UK: John Wiley, 2006.
Buscar texto completoKursun, Volkan. Multiple supply and threshold voltage CMOS circuits. Chichester, England: John Wiley, 2006.
Buscar texto completoT, Butler Jon, ed. Multiple-valued logic in VLSI design. Los Alamitos, Calif: IEEE Computer Society Press, 1991.
Buscar texto completoChedid, Andrée. L'enfant multiple. [Paris]: Flammarion, 1991.
Buscar texto completoUnited States. Bureau of Mines, ed. Multiple-channel trigger circuit for noise discrimination in ultrasonic acoustic emission studies. [Washington, D.C.?]: U.S. Dept. of the Interior, Bureau of Mines, 1995.
Buscar texto completoHanson, David R. Multiple-channel trigger circuit for noise discrimination in ultrasonic acoustic emission studies. [Washington, D.C.?]: U.S. Dept. of the Interior, Bureau of Mines, 1995.
Buscar texto completoHanson, David R. Multiple-channel trigger circuit for noise discrimination in ultrasonic acoustic emission studies. [Washington, D.C.?]: U.S. Dept. of the Interior, Bureau of Mines, 1995.
Buscar texto completoHanson, David R. Multiple-channel trigger circuit for noise discrimination in ultrasonic acoustic emission studies. [Washington, D.C.?]: U.S. Dept. of the Interior, Bureau of Mines, 1995.
Buscar texto completoHanson, David R. Multiple-channel trigger circuit for noise discrimination in ultrasonic acoustic emission studies. Washington, DC: U.S. Dept. of the Interior, Bureau of Mines, 1995.
Buscar texto completoHanson, David R. Multiple-channel trigger circuit for noise discrimination in ultrasonic acoustic emission studies. [Washington, D.C.?]: U.S. Dept. of the Interior, Bureau of Mines, 1995.
Buscar texto completoCapítulos de libros sobre el tema "MULTIPLIER CIRCUIT"
Selvam, K. C. "Circuit Simulation". En Multiplier-Cum-Divider Circuits, 197–202. New York: CRC Press, 2021. http://dx.doi.org/10.1201/9781003168515-14.
Texto completoSaas, C., A. Schlaffer y J. A. Nossek. "An Adiabatic Multiplier". En Integrated Circuit Design, 276–84. Berlin, Heidelberg: Springer Berlin Heidelberg, 2000. http://dx.doi.org/10.1007/3-540-45373-3_29.
Texto completoKaufmann, Daniela y Armin Biere. "AMulet 2.0 for Verifying Multiplier Circuits". En Tools and Algorithms for the Construction and Analysis of Systems, 357–64. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-72013-1_19.
Texto completoSelvam, K. C. "Peak Responding Multiplier cum Dividers—Switching". En Design of Function Circuits with 555 Timer Integrated Circuit, 137–53. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003362968-8.
Texto completoSelvam, K. C. "Peak Responding Multiplier cum Dividers—Multiplexing". En Design of Function Circuits with 555 Timer Integrated Circuit, 119–35. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003362968-7.
Texto completoSelvam, K. C. "Time Division Multiplier cum Divider—Switching". En Design of Function Circuits with 555 Timer Integrated Circuit, 93–117. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003362968-6.
Texto completoSelsiya, M. James, M. Kalaiarasi, S. Rajaram y V. R. Venkatasubramani. "Efficient Quantum Circuit for Karatsuba Multiplier". En Studies in Computational Intelligence, 79–96. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-19-9530-9_5.
Texto completoBabu, Hafiz Md Hasan. "LUT-Based Matrix Multiplier Circuit Using Pigeonhole Principle". En VLSI Circuits and Embedded Systems, 233–86. Boca Raton: CRC Press, 2022. http://dx.doi.org/10.1201/9781003269182-22.
Texto completoMandal, Sumana, Dhoumendra Mandal, Mrinal Kanti Mandal y Sisir Kumar Garai. "Design of Optical Quaternary Multiplier Circuit Using Polarization Switch". En Lecture Notes in Electrical Engineering, 111–19. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-13-6159-3_13.
Texto completoWu, Ying, Chuangtao Chen, Chenyi Wen, Weikang Qian, Xunzhao Yin y Cheng Zhuo. "Approximate Multiplier Design for Energy Efficiency: From Circuit to Algorithm". En Approximate Computing, 51–76. Cham: Springer International Publishing, 2012. http://dx.doi.org/10.1007/978-3-030-98347-5_3.
Texto completoActas de conferencias sobre el tema "MULTIPLIER CIRCUIT"
Banerjee, A. y A. Pathak. "Reversible Multiplier Circuit". En Third International Conference on Emerging Trends in Engineering and Technology (ICETET 2010). IEEE, 2010. http://dx.doi.org/10.1109/icetet.2010.70.
Texto completoZhu, Binxin, Yao Chen, Han Wang y Mahinda Vilathgamuwa. "Multiple Input-Terminal Voltage Multiplier Circuit". En 2019 4th International Conference on Intelligent Green Building and Smart Grid (IGBSG). IEEE, 2019. http://dx.doi.org/10.1109/igbsg.2019.8886172.
Texto completoHatkar, A. P., A. A. Hatkar y N. P. Narkhede. "ASIC Design of Reversible Multiplier Circuit". En 2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies (ICESC). IEEE, 2014. http://dx.doi.org/10.1109/icesc.2014.16.
Texto completoMongkolwai, Pratya y Worapong Tangsrirat. "CFTA-based current multiplier/divider circuit". En 2011 International Symposium on Intelligent Signal Processing and Communications Systems (ISPACS 2011). IEEE, 2011. http://dx.doi.org/10.1109/ispacs.2011.6146074.
Texto completoEl-Slehdar, A. A. y Ahmed G. Radwan. "Memristor-MOS hybrid circuit redundant multiplier". En 2014 26th International Conference on Microelectronics (ICM). IEEE, 2014. http://dx.doi.org/10.1109/icm.2014.7071836.
Texto completoKwang-Jow Gan, Ping-Feng Wu, Wu-Yan Shie, Cher-Shiung Tsai, Dong-Shong Liang, Cheng-Hsiung Tsai y Wen-Kuan Yeh. "Frequency multiplier design using BiCMOS-based multiple-peak NDR circuit". En 2010 IEEE International Conference of Electron Devices and Solid- State Circuits (EDSSC). IEEE, 2010. http://dx.doi.org/10.1109/edssc.2010.5713683.
Texto completoOzenli, Deniz, Ersin Alaybeyoglu y Hakan Kuntman. "A Grounded Capacitance Multiplier Circuit Employing VDTA". En 2021 13th International Conference on Electrical and Electronics Engineering (ELECO). IEEE, 2021. http://dx.doi.org/10.23919/eleco54474.2021.9677731.
Texto completoHussain, Inamul, Chandan Kumar Pandey y Saurabh Chaudhury. "Design and Analysis of High Performance Multiplier Circuit". En 2019 Devices for Integrated Circuit (DevIC). IEEE, 2019. http://dx.doi.org/10.1109/devic.2019.8783322.
Texto completoSarker, Ankur, Mohd Istiaq Sharif, S. M. Mahbubur Rashid y Hafiz Md Hasan Babu. "Implementation of reversible multiplier circuit using Deoxyribonucleic acid". En 2013 IEEE 13th International Conference on Bioinformatics and Bioengineering (BIBE). IEEE, 2013. http://dx.doi.org/10.1109/bibe.2013.6701637.
Texto completoAkhter, Shamim y Saurabh Chaturvedi. "Modified Binary Multiplier Circuit Based on Vedic Mathematics". En 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN). IEEE, 2019. http://dx.doi.org/10.1109/spin.2019.8711583.
Texto completoInformes sobre el tema "MULTIPLIER CIRCUIT"
Butler, Jon T. y Tsutomu Sasao. Multiple-Valued Combinational Circuits with Feedback. Fort Belvoir, VA: Defense Technical Information Center, enero de 1994. http://dx.doi.org/10.21236/ada599933.
Texto completoChang, Young-hoon y Jon T. Butler. The Design of Current Mode CMOS Multiple-Valued Circuits. Fort Belvoir, VA: Defense Technical Information Center, enero de 1991. http://dx.doi.org/10.21236/ada608087.
Texto completoSchueller, Kriss A. y Jon T. Butler. Complexity Analysis of the Cost-Table Approach to the Design of Multiple-Valued Logic Circuits. Fort Belvoir, VA: Defense Technical Information Center, octubre de 1995. http://dx.doi.org/10.21236/ada605390.
Texto completoNestleroth. L52298 Augmenting MFL Tools With Sensors that Assess Coating Condition. Chantilly, Virginia: Pipeline Research Council International, Inc. (PRCI), marzo de 2009. http://dx.doi.org/10.55274/r0010396.
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