Artículos de revistas sobre el tema "Multi-Processor System-on-Chip"
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Nurmi, Jari. "International Symposium on System-on-Chip 2010". International Journal of Embedded and Real-Time Communication Systems 2, n.º 4 (octubre de 2011): 38–45. http://dx.doi.org/10.4018/ijertcs.2011100103.
Texto completoLee, Seung Eun. "Reusing existing resources for testing a multi-processor system-on-chip". International Journal of Electronics 100, n.º 3 (marzo de 2013): 355–70. http://dx.doi.org/10.1080/00207217.2012.713011.
Texto completoCui, Yuan y Bo Nian Li. "A Multimedia System Based on OMAP3530". Applied Mechanics and Materials 40-41 (noviembre de 2010): 506–9. http://dx.doi.org/10.4028/www.scientific.net/amm.40-41.506.
Texto completoLiu, Lin y Yuanyuan Yang. "Energy-aware routing in hybrid optical network-on-chip for future multi-processor system-on-chip". Journal of Parallel and Distributed Computing 73, n.º 2 (febrero de 2013): 189–97. http://dx.doi.org/10.1016/j.jpdc.2012.09.018.
Texto completoLafi, Walid, Didier Lattard y Ahmed Jerrya. "An asynchronous hierarchical router for networks-on-chip-based three-dimensional multi-processor system-on-chip". Software: Practice and Experience 42, n.º 7 (7 de febrero de 2012): 877–90. http://dx.doi.org/10.1002/spe.1150.
Texto completoAMAMIYA, MAKOTO, HIDEO TANIGUCHI y TAKANORI MATSUZAKI. "AN ARCHITECTURE OF FUSING COMMUNICATION AND EXECUTION FOR GLOBAL DISTRIBUTED PROCESSING". Parallel Processing Letters 11, n.º 01 (marzo de 2001): 7–24. http://dx.doi.org/10.1142/s0129626401000397.
Texto completoLi, Shuo, Gao Chao Xu, Yu Shuang Dong y Feng Wu. "The Review of Cache Partitioning in Multi-Core Processor". Key Engineering Materials 439-440 (junio de 2010): 1223–29. http://dx.doi.org/10.4028/www.scientific.net/kem.439-440.1223.
Texto completoSLIMANI, Hayet, Abderrazak JEMAIU y Ahmed Chiheb AMMARI. "Multi-Processor System-on-Chip Power Estimation Model At the CABA Level". IFAC Proceedings Volumes 45, n.º 7 (2012): 341–46. http://dx.doi.org/10.3182/20120523-3-cz-3015.00065.
Texto completoTang, Lin y Jin Zhao Wu. "The Status and Challenges of Multi-Processor System-on-Chip’s Formal Verification". Applied Mechanics and Materials 602-605 (agosto de 2014): 2926–29. http://dx.doi.org/10.4028/www.scientific.net/amm.602-605.2926.
Texto completoBAGHERZADEH, NADER y MASARU MATSUURA. "PERFORMANCE IMPACT OF TASK-TO-TASK COMMUNICATION PROTOCOL IN NETWORK-ON-CHIP". Journal of Circuits, Systems and Computers 18, n.º 02 (abril de 2009): 283–94. http://dx.doi.org/10.1142/s021812660900506x.
Texto completoPrasad Acharya, G. y M. Asha Rani. "FPGA Prototyping of Micro-Blaze soft-processor based Multi-core System on Chip". International Journal of Engineering & Technology 7, n.º 2.16 (12 de abril de 2018): 57. http://dx.doi.org/10.14419/ijet.v7i2.16.11416.
Texto completoBreaban, Gabriela, Martijn Koedam, Sander Stuijk y Kees Goossens. "Time synchronization for an emulated CAN device on a Multi-Processor System on Chip". Microprocessors and Microsystems 52 (julio de 2017): 523–33. http://dx.doi.org/10.1016/j.micpro.2017.04.019.
Texto completoMilojevic, Dragomir, Luc Montperrus y Diederik Verkest. "Power Dissipation of the Network-on-Chip in Multi-Processor System-on-Chip Dedicated for Video Coding Applications". Journal of Signal Processing Systems 57, n.º 2 (29 de julio de 2008): 139–53. http://dx.doi.org/10.1007/s11265-008-0251-1.
Texto completoTang, Qi, Shang-Feng Wu, Jun-Wu Shi y Ji-Bo Wei. "Optimization of Duplication-Based Schedules on Network-on-Chip Based Multi-Processor System-on-Chips". IEEE Transactions on Parallel and Distributed Systems 28, n.º 3 (1 de marzo de 2017): 826–37. http://dx.doi.org/10.1109/tpds.2016.2599166.
Texto completoGaneshpure, Kunal y Sandip Kundu. "Game theoretic approach for run‐time task scheduling on an multi‐processor system on chip". IET Circuits, Devices & Systems 7, n.º 5 (septiembre de 2013): 243–52. http://dx.doi.org/10.1049/iet-cds.2013.0091.
Texto completoLesecq, Suzanne, Diego Puschini, Edith Beigné, Pascal Vivet y Yeter Akgul. "Low-Cost and Robust Control of a DFLL for Multi-Processor System-on-Chip". IFAC Proceedings Volumes 44, n.º 1 (enero de 2011): 1940–45. http://dx.doi.org/10.3182/20110828-6-it-1002.01706.
Texto completoKhan, Haroon-Ur-Rashid, Feng Shi, WeiXing Ji, YuJin Gao, YiZhuo Wang, CaiXia Liu, Ning Deng y JiaXin Li. "Computationally efficient locality-aware interconnection topology for multi-processor system-on-chip (MP-SoC)". Chinese Science Bulletin 55, n.º 29 (octubre de 2010): 3363–71. http://dx.doi.org/10.1007/s11434-010-4118-z.
Texto completoDeng, Yao Hua, Gui Xiong Liu, Wei Han, Zi Wei Fang, Li Ming Wu y Qing Fu Liao. "Research on Multi-Core Collaborative Computing for FWP Image Processing Algorithm by FPGA". Advanced Materials Research 230-232 (mayo de 2011): 1340–44. http://dx.doi.org/10.4028/www.scientific.net/amr.230-232.1340.
Texto completoSalamy, Hassan. "Energy-Aware Schedules Under Chip Reliability Constraint for Multi-Processor Systems-on-a-Chip". Journal of Circuits, Systems and Computers 29, n.º 09 (29 de octubre de 2019): 2050135. http://dx.doi.org/10.1142/s0218126620501352.
Texto completoSalamy, Hassan y Semih Aslan. "Pipelined-Scheduling of Multiple Embedded Applications on a Multi-Processor-SoC". Journal of Circuits, Systems and Computers 26, n.º 03 (21 de noviembre de 2016): 1750042. http://dx.doi.org/10.1142/s0218126617500426.
Texto completoJia, Hao, Shanglin Yang, Ting Zhou, Sizhu Shao, Xin Fu, Lei Zhang y Lin Yang. "WDM-compatible multimode optical switching system-on-chip". Nanophotonics 8, n.º 5 (27 de abril de 2019): 889–98. http://dx.doi.org/10.1515/nanoph-2019-0005.
Texto completoHan, Pei Cen, Zhao Hui Ye, Yong Ming Zhou y Shi Yuan Yang. "SOPC-Based Motion Controller with NURBS Interpolator". Advanced Materials Research 898 (febrero de 2014): 937–43. http://dx.doi.org/10.4028/www.scientific.net/amr.898.937.
Texto completoBorejko, Tomasz, Krzysztof Marcinek, Krzysztof Siwiec, Paweł Narczyk, Adam Borkowski, Igor Butryn, Arkadiusz Łuczyk et al. "NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor". Sensors 20, n.º 4 (16 de febrero de 2020): 1069. http://dx.doi.org/10.3390/s20041069.
Texto completoMhaidat, Khaldoon Moosa, Ahmad Baset y Osama Al-Khaleel. "OpenSPARC Processor Evaluation Using Virtex-5 FPGA and High Performance Embedded Computing (HPEC) Benchmark Suite". International Journal of Embedded and Real-Time Communication Systems 5, n.º 1 (enero de 2014): 61–74. http://dx.doi.org/10.4018/ijertcs.2014010104.
Texto completoZuo, Qi. "Task Assignment for Multiple-Application Workload with Streaming Ones in MPSoC Using Shared Memory". Applied Mechanics and Materials 263-266 (diciembre de 2012): 1781–85. http://dx.doi.org/10.4028/www.scientific.net/amm.263-266.1781.
Texto completoPelissier, Frantz, Hanen Chenini, François Berry, Alexis Landrault y Jean-Pierre Derutin. "Embedded multi-processor system-on-programmable chip for smart camera pose estimation using nonlinear optimization methods". Journal of Real-Time Image Processing 12, n.º 4 (30 de septiembre de 2014): 663–79. http://dx.doi.org/10.1007/s11554-014-0454-6.
Texto completoAbbes, Hanen, Hafedh Abid, Kais Loukil, Mohamed Abid y Ahmad Toumi. "Fuzzy-based MPPT algorithm implementation on FPGA chip for multi-channel photovoltaic system". International Journal of Reconfigurable and Embedded Systems (IJRES) 11, n.º 1 (1 de marzo de 2022): 49. http://dx.doi.org/10.11591/ijres.v11.i1.pp49-58.
Texto completoLiu, Jian Qun, Dong Xu, Ji Rong Wu, Xiao Li y Jian Huang. "The Design of Carton Samplemaker’s Embedded Numerical Control System Based on Windows CE". Advanced Materials Research 211-212 (febrero de 2011): 330–35. http://dx.doi.org/10.4028/www.scientific.net/amr.211-212.330.
Texto completoSingh, Akhilesh K., Kevin M. Sullivan, George R. Leal y Tony Gong. "Assembly challenges with Flip Chip multi-die and interposer-based SiP Modules". International Symposium on Microelectronics 2019, n.º 1 (1 de octubre de 2019): 000001–5. http://dx.doi.org/10.4071/2380-4505-2019.1.000001.
Texto completoWang, Shiyu, Shengbing Zhang, Xiaoping Huang y Libo Chang. "Single-chip multi-processing architecture for spaceborne SAR imaging and intelligent processing". Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 39, n.º 3 (junio de 2021): 510–20. http://dx.doi.org/10.1051/jnwpu/20213930510.
Texto completoShahid, Arsalan, Muhammad Yasir Qadri, Martin Fleury, Hira Waris, Ayaz Ahmad y Nadia N. Qadri. "AC-DSE: Approximate Computing for the Design Space Exploration of Reconfigurable MPSoCs". Journal of Circuits, Systems and Computers 27, n.º 09 (26 de abril de 2018): 1850145. http://dx.doi.org/10.1142/s0218126618501451.
Texto completoBAHN, JUN HO, SEUNG EUN LEE, YOON SEOK YANG, JUNGSOOK YANG y NADER BAGHERZADEH. "ON DESIGN AND APPLICATION MAPPING OF A NETWORK-ON-CHIP(NOC) ARCHITECTURE". Parallel Processing Letters 18, n.º 02 (junio de 2008): 239–55. http://dx.doi.org/10.1142/s0129626408003363.
Texto completoWen, Wu, De Hua He, Hua Feng y Peng Gu. "The Design of a New Network Cabling Experimental Instrument Based on Embedded System". Advanced Materials Research 328-330 (septiembre de 2011): 2427–31. http://dx.doi.org/10.4028/www.scientific.net/amr.328-330.2427.
Texto completoGarzia, Fabio, Roberto Airoldi y Jari Nurmi. "Implementation of FFT on General-Purpose Architectures for FPGA". International Journal of Embedded and Real-Time Communication Systems 1, n.º 3 (julio de 2010): 24–43. http://dx.doi.org/10.4018/jertcs.2010070102.
Texto completoZhang, Diandian, Li Lu, Jeronimo Castrillon, Torsten Kempf, Gerd Ascheid, Rainer Leupers y Bart Vanthournout. "Efficient Implementation of Application-Aware Spinlock Control in MPSoCs". International Journal of Embedded and Real-Time Communication Systems 4, n.º 1 (enero de 2013): 64–84. http://dx.doi.org/10.4018/jertcs.2013010104.
Texto completoMuscheid, T., A. Boebel, N. Karcher, T. Vanat, L. Ardila-Perez, I. Cheviakov, M. Schleicher, M. Zimmer, M. Balzer y O. Sander. "DTS-100G — a versatile heterogeneous MPSoC board for cryogenic sensor readout". Journal of Instrumentation 18, n.º 02 (1 de febrero de 2023): C02067. http://dx.doi.org/10.1088/1748-0221/18/02/c02067.
Texto completoZhang, Diandian, Han Zhang, Jeronimo Castrillon, Torsten Kempf, Bart Vanthournout, Gerd Ascheid y Rainer Leupers. "Optimized Communication Architecture of MPSoCs with a Hardware Scheduler". International Journal of Embedded and Real-Time Communication Systems 2, n.º 3 (julio de 2011): 1–20. http://dx.doi.org/10.4018/jertcs.2011070101.
Texto completoZhou, Xinbing, Peng Hao y Dake Liu. "PCCNoC: Packet Connected Circuit as Network on Chip for High Throughput and Low Latency SoCs". Micromachines 14, n.º 3 (21 de febrero de 2023): 501. http://dx.doi.org/10.3390/mi14030501.
Texto completoBellemou, A., N. Benblidia, M. Anane y M. Issad. "MicroBlaze-Based Multiprocessor Embedded Cryptosystem on FPGA for Elliptic Curve Scalar Multiplication Over Fp". Journal of Circuits, Systems and Computers 28, n.º 03 (24 de febrero de 2019): 1950037. http://dx.doi.org/10.1142/s0218126619500373.
Texto completoGaniee, Sajad Ahmad, Shabeer Ahmad Ganiee y Jehangir Rashid Dar. "FPGA Design of 8 bit 4×4 Crossbar Switch for Multi Processor System on Chip Using Round Robin Arbitration Algorithm". International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering 04, n.º 01 (20 de enero de 2015): 109–19. http://dx.doi.org/10.15662/ijareeie.2015.0401010.
Texto completoMehner, T., L. E. Ardila-Perez, M. N. Balzer, O. Sander, D. Tcherniakhovski, M. Schleicher, M. Fuchs et al. "ZynqMP-based board-management mezzanines for Serenity ATCA-blades". Journal of Instrumentation 17, n.º 03 (1 de marzo de 2022): C03009. http://dx.doi.org/10.1088/1748-0221/17/03/c03009.
Texto completoBossuet, Lilian y El Mehdi Benhani. "Performing Cache Timing Attacks from the Reconfigurable Part of a Heterogeneous SoC—An Experimental Study". Applied Sciences 11, n.º 14 (20 de julio de 2021): 6662. http://dx.doi.org/10.3390/app11146662.
Texto completoKumar, K. Suresh, S. Anitha y M. Gayathri. "3D Stacked Cache Data Management for Energy Minimization of 3D Chip Multiprocessor". International Journal of Students' Research in Technology & Management 3, n.º 2 (27 de septiembre de 2015): 264–68. http://dx.doi.org/10.18510/ijsrtm.2015.325.
Texto completoDey, Somdip, Samuel Isuwa, Suman Saha, Amit Kumar Singh y Klaus McDonald-Maier. "CPU-GPU-Memory DVFS for Power-Efficient MPSoC in Mobile Cyber Physical Systems". Future Internet 14, n.º 3 (14 de marzo de 2022): 91. http://dx.doi.org/10.3390/fi14030091.
Texto completoLeon, Vasileios, George Lentaris, Evangelos Petrongonas, Dimitrios Soudris, Gianluca Furano, Antonis Tavoularis y David Moloney. "Improving Performance-Power-Programmability in Space Avionics with Edge Devices: VBN on Myriad2 SoC". ACM Transactions on Embedded Computing Systems 20, n.º 3 (abril de 2021): 1–23. http://dx.doi.org/10.1145/3440885.
Texto completoVandendriessche, Jurgen, Bruno da Silva, Lancelot Lhoest, An Braeken y Abdellah Touhafi. "M3-AC: A Multi-Mode Multithread SoC FPGA Based Acoustic Camera". Electronics 10, n.º 3 (29 de enero de 2021): 317. http://dx.doi.org/10.3390/electronics10030317.
Texto completoEL-MOURSY, ALI A. y FADI N. SIBAI. "V-SET CACHE: AN EFFICIENT ADAPTIVE SHARED CACHE FOR MULTI-CORE PROCESSORS". Journal of Circuits, Systems and Computers 23, n.º 07 (2 de junio de 2014): 1450095. http://dx.doi.org/10.1142/s0218126614500959.
Texto completoBallan, Oscar, Pierre Maillard, Jue Arver, Christina Smith, Roland Petersson, Alexander Griessing y Federico Venini. "Evaluation of ISO 26262 and IEC 61508 metrics for transient faults of a multi-processor system-on-chip through radiation testing". Microelectronics Reliability 107 (abril de 2020): 113601. http://dx.doi.org/10.1016/j.microrel.2020.113601.
Texto completoAshkenazi, A. y D. Akselrod. "Platform independent overall security architecture in multi-processor system-on-chip integrated circuits for use in mobile phones and handheld devices". Computers & Electrical Engineering 33, n.º 5-6 (septiembre de 2007): 407–24. http://dx.doi.org/10.1016/j.compeleceng.2007.05.003.
Texto completoWang, Shiyu, Shengbing Zhang, Xiaoping Huang y Hao Lyu. "On-chip data organization and access strategy for spaceborne SAR real-time imaging processor". Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 39, n.º 1 (febrero de 2021): 126–34. http://dx.doi.org/10.1051/jnwpu/20213910126.
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