Tesis sobre el tema "Multi-Processor System-on-Chip"
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Ghaeini, Bentolhoda. "A Fault-Aware Resource Manager for Multi-Processor System-on-Chip". Thesis, Linköpings universitet, Institutionen för datavetenskap, 2013. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-101010.
Texto completoHegde, Sridhar. "FUNCTIONAL ENHANCEMENT AND APPLICATIONS DEVELOPMENT FOR A HYBRID, HETEROGENEOUS SINGLE-CHIP MULTIPROCESSOR ARCHITECTURE". UKnowledge, 2004. http://uknowledge.uky.edu/gradschool_theses/252.
Texto completoRyu, Kyeong Keol. "Automated Bus Generation for Multi-processor SoC Design". Diss., Georgia Institute of Technology, 2004. http://hdl.handle.net/1853/5076.
Texto completoKliem, Daniel [Verfasser]. "A Flexible Multi-Processor System-on-a-Chip Architecture for Safety- and Security-Critical Applications / Daniel Kliem". Aachen : Shaker, 2013. http://d-nb.info/1050342682/34.
Texto completoPoletti, Francesco <1977>. "Multi processor system on chip platform and studying of the best architecture and software solution for an application". Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2007. http://amsdottorato.unibo.it/407/1/Tesi_pol.pdf.
Texto completoPoletti, Francesco <1977>. "Multi processor system on chip platform and studying of the best architecture and software solution for an application". Doctoral thesis, Alma Mater Studiorum - Università di Bologna, 2007. http://amsdottorato.unibo.it/407/.
Texto completoWang, Zheng [Verfasser], Anupam [Akademischer Betreuer] Chattopadhyay y Tobias G. [Akademischer Betreuer] Noll. "High-level estimation and exploration of reliability for multi-processor system-on-chip / Zheng Wang ; Anupam Chattopadhyay, Tobias G. Noll". Aachen : Universitätsbibliothek der RWTH Aachen, 2015. http://d-nb.info/1125910704/34.
Texto completoDruyer, Rémy. "Réseau sur puce sécurisé pour applications cryptographiques sur FPGA". Thesis, Montpellier, 2017. http://www.theses.fr/2017MONTS023/document.
Texto completoWhether through smartphones, portable game consoles, or high performances computing, Systems-on-Chip (SoC) have seen their use widely spread over the last two decades. This can be explained by the low power consumption of these circuits with the regard of the performances they are able to deliver, and the numerous function they can integrate. Since SoC are improving every day, they require better performances from interconnects that support their communications. In order to address this issue Network-on-Chip have emerged.In addition to ASICs, FPGA circuits are one of the possible choices when conceiving a SoC. Our first contribution was therefore to perform and study the performance of Hermes NoC initially designed for ASIC, on reconfigurable circuit. This allowed us to confirm that the architecture of the interconnection system must be adapted to that of the circuit in order to achieve the best possible performances. Thus, our second contribution was to design TrustNoC, an optimized NoC for FPGA platform, with low latency, high operating frequency, and a moderate quantity of logical resources required for implementation.Security is also a primordial aspect of systems-on-chip, and more generally, of all digital systems. Our latest contribution was to study the threats that target SoCs during all their life cycle, then to develop and integrate hardware security mechanisms to TrustNoC in order to counter IP hijacking, and software attacks. During the design of security mechanisms, we tried to limit as much as possible the overhead on NoC performances
Faure, Etienne. "Communications matérielles / logicielles dans les systèmes sur puces multi-processeurs orientés télécommunications". Paris 6, 2007. http://www.theses.fr/2007PA066201.
Texto completoBelhadj, Amor Hela. "Hiérarchie mémoire dans les systèmes intégrés multiprocesseurs construits autour de réseaux sur puce". Thesis, Université Grenoble Alpes (ComUE), 2017. http://www.theses.fr/2017GREAM049/document.
Texto completoMulti/many-cores parallel systems for high-power computing at low energy costs are nowadays a reality. However, exploiting the performance of these architectures depends on the efficiency of the system in managing data accesses. The aim of our work is to improve the efficiency of these accesses by exploiting the hardware architecture characteristics.In a first part, we propose a new cache hierarchy organization that aims at maximizing the use of the available storage space at each level. This solution, based on non-uniform cache access architectures (NUCA), supports inter and intra-level transfers of the hierarchy. It requires a cache coherency protocol that suits its specifications.Obviously, the transfer of data in the hierarchy is also a determinant of the system performance. In a second part, we consider the specific communication needs of the protocol. We suggest the use of a virtualized network as an ad-hoc communication medium to manage consistency traffic at a lower cost. It links the caches of the same level to support intra-level transfers, which are a specificity of our protocol, in order to reduce the average access latency
Mallangi, Siva Sai Reddy. "Low-Power Policies Based on DVFS for the MUSEIC v2 System-on-Chip". Thesis, KTH, Skolan för informations- och kommunikationsteknik (ICT), 2017. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-229443.
Texto completoNuförtiden så har multifunktionella bärbara hälsoenheter fått en betydande roll. Dessa enheter drivs vanligtvis av batterier och är därför begränsade av batteritiden (från ett par timmar till ett par veckor beroende på tillämpningen). På senaste tiden har det framkommit att dessa enheter som används vid en fast spänning och frekvens kan användas vid flera spänningar och frekvenser. Genom att byta till lägre spänning och frekvens på grund av effektbehov så kan enheterna få enorma fördelar när det kommer till energibesparing. Dynamisk skalning av spänning och frekvens-tekniker (såkallad Dynamic Voltage and Frequency Scaling, DVFS) har visat sig vara användbara i detta sammanhang för en effektiv avvägning mellan energi och beteende. Hos Imec så använder sig bärbara enheter av den internt utvecklade MUSEIC v2 (Multi Sensor Integrated circuit version 2.0). Systemet är optimerat för effektiv och korrekt insamling, bearbetning och överföring av data från flera (hälso) sensorer. MUSEIC v2 har begränsad möjlighet att styra spänningen och frekvensen dynamiskt. I detta examensarbete undersöker vi hur traditionella DVFS-tekniker kan appliceras på MUSEIC v2. Experiment utfördes för att ta reda på de optimala effektlägena och för att effektivt kunna styra och även skala upp matningsspänningen och frekvensen. Eftersom att ”overhead” skapades vid växling av spänning och frekvens gjordes också en övergångsanalys. Realtidsoch icke-realtidskalkyler genomfördes baserat på dessa tekniker och resultaten sammanställdes och analyserades. I denna process granskades flera toppmoderna schemaläggningsalgoritmer och skalningstekniker för att hitta en lämplig teknik. Genom att använda vår föreslagna skalningsteknikimplementering har vi uppnått 86,95% effektreduktion i jämförelse med det konventionella sättet att MUSEIC v2-chipets processor arbetar med en fast spänning och frekvens. Tekniker som inkluderar lätt sömn och djupt sömnläge studerades och implementerades, vilket testade systemets förmåga att tillgodose DPM-tekniker (Dynamic Power Management) som kan uppnå ännu större fördelar. En ny metod för att genomföra den djupa sömnmekanismen föreslogs också och enligt erhållna resultat så kan den ge upp till 71,54% lägre energiförbrukning jämfört med det traditionella sättet att implementera djupt sömnläge.
Лисенко, Дмитро Сергійович. "Методи формування цифрового потоку для систем широкосмугового радіодоступу". Doctoral thesis, Київ, 2013. https://ela.kpi.ua/handle/123456789/3337.
Texto completoVasudevan, Siddarth. "Design and Development of a CubeSat Hardware Architecture with COTS MPSoC using Radiation Mitigation Techniques". Thesis, KTH, Skolan för elektroteknik och datavetenskap (EECS), 2020. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-285577.
Texto completoCubeSat-uppdrag behöver komponenter som är toleranta mot strålningen i rymden. Maskinvarukomponenterna måste vara pålitliga och funktionaliteten ombord får inte äventyras under uppdraget. Samtidigt bör kostnaden för hårdvara och dess utveckling inte vara hög. Därför diskuterar denna avhandling design och utveckling av en CubeSatarkitektur med hjälp av COTS (eng. Custom-off-The-Shelf) MPSoC (eng. Multi Processor System-on-Chip). Arkitekturen använder en prisvärd strålningshärdad (eng. Rad-Hard) Micro-Controller Unit(MCU) som Övervakare för MPSoC:en och använder också flera tekniker för att begränsa strålningens effekter såsom kretser för att skydda kretsen från s.k. Single Event Latch-Ups (SELs), återläsningsskrubbning för icke-volatila minnen (eng. Non-Volatile Memories) NVMs som NOR Flash och skrubbning av konfigurationsminnet skrubbning för FPGA:er i MPSoC:en för att skydda dem mot Single-Event Upsets (SEUs), och tillhandahålla pålitlig kommunikation mha CRC och Space Packet Protocol. Bortsett från sådana funktioner utför Övervakaren uppgifter som Watchdog för att övervaka att applikationerna som körs i MPSoC:en fortfarande är vid liv, dataloggning, och Over- the-Air-uppdateringar av programvaran/Firmware. Examensarbetet implementerar funktioner såsom kommunikation, återläsningsskrubbning av minnet, konfigurationsminnesskrubbning mha SEM- IP, Watchdog och uppdatering av programvara/firmware. Exekveringstiderna för utförandet av funktionerna presenteras för den applikationen som körs i Övervakaren. När det gäller konfigurationsminnesskrubbningen som implementerats i den programmerbara logiken i FPGA:n, rapporteras area och latens.
Chou, Chih-Chieh y 周志杰. "Task Binding on Multi-Processor System-on-Chip". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/z92xvg.
Texto completo國立交通大學
電子工程系所
92
Network-on-Chip is a new design paradigm for designing core based System-on-Chip. It features high degree of reusability and scalability. In this thesis, we describe a two-step task binding algorithm that has been used to build a tool to map an application, described by a parameterized task graph, onto Multi-Processor System-on-Chip platform with a two dimensional mesh of switches as a communication backbone. The algorithm tries to find a mapping of tasks to available computational resources so that the overall execution time of the application is minimized and the system performance gain is maximized. By incorporating software processor and switch models, a system simulation can be performed. And in few minutes, the system performance gain can be assessed and some important platform parameters can be extracted.
Huang, Pao-Jui y 黃保瑞. "A switch design for multi-processor system on chip". Thesis, 2004. http://ndltd.ncl.edu.tw/handle/77vu7j.
Texto completo國立交通大學
電子工程系所
92
Driven by the advance of semiconductor technology, it is possible to integrate hundreds of processing elements on a single chip in the next decade. At the moment, communication between the components will become the limiting factor for system performance and a communication-driven system design methodology will be needed. In this thesis, we propose an on-chip communication infrastructure for multi-processor system-on-chip. By appropriate configuration, the network can work as circuit switching, packet switching, and dedicated bus. System designers can also benefit from our framework to analyze the system performance and make better decisions at higher level because our platform exhibits predictable performance. The experiments of performance evaluation show that the communication fabrics can efficiently transfer data within system.
Lin, Yi-ciang y 林易瑲. "Design of Low Power Snoop Protocol for Multi-Processor System on Chip". Thesis, 2012. http://ndltd.ncl.edu.tw/handle/58574573683635342929.
Texto completo國立臺南大學
資訊工程學系碩士班
100
In multiprocessor system on chip (MPSoC), processors can access expectable shared data by using snoop protocol even though the writing or reading operations have time difference. However, the design will generate a large number of snoops which consume some unnecessary energy. The main objective of this thesis is to present an energy-saving architecture such that the number of snoops of the multiprocessor system can be reduced. The data accessed synchronous by multiple processors is known as the critical section in multiprocessor system. When the data in critical section is accessed by a processor, the critical section will be locked immediately so that other processors cannot access the data. With the procedure executing, there exists a time point called snoop-activity turning point in which the processor in the critical section has not common accessing data with the other processors. In this thesis, we first add buffers to the caches of processors and shared buses to label the number of processors, which have common accessing data. Therefore, we only need to snoop the processors labeled in buffers before the snoop-activity turning point。Next, all snoops are abbreviated after snoop-activity turning point because there are no common accessing data between the processor in the critical section and the other processors during the time. The experimental results have shown that the proposed methods can achieve the purpose of energy saving.
Yen-ChangChen y 陳彥彰. "The implementation of real-time process migration on NUMA shared memory in multi-processor system-on-chip". Thesis, 2010. http://ndltd.ncl.edu.tw/handle/73586277965504472608.
Texto completo國立成功大學
資訊工程學系碩博士班
98
Today, computer systems need high computing power, multimedia integration and reliable communication functionality. Single processor may not satisfy these requirements. In general, the solution is using multi-processors to overcome these requirements. Especially, heterogeneous processors are more popular on multi-core, because system can dispatch suitable process to suitable processor for high processor utilization. Not only to personal computers but also the requirements of embedded system multi-processors provide low power consumption and high performance. Now, how to increase processors utilization becomes an important issue. In this paper, we implement a multi-kernel system on a multiprocessors environment, and in order to alleviate the system load we ported kernels (MicroC/OS-II) in our system. We implement process migration mechanism, based on this mechanism we can perform process migration between kernels, so we break the constraint of applications sharing between kernels. Finally, we implement a global scheduling policy to verify the process migration mechanism. Basing the policy, we also evaluate the system performance, and in our experiment the system performance can almost be raised up to 19%.
Vikas, G. "Power Optimal Network-On-Chip Interconnect Design". Thesis, 2010. http://etd.iisc.ernet.in/handle/2005/1408.
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