Artículos de revistas sobre el tema "Multi-core execution"
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Fang, Juan y Hong Bo Zhang. "An Improved Architecture for Multi-Core Prefetching". Advanced Materials Research 505 (abril de 2012): 253–56. http://dx.doi.org/10.4028/www.scientific.net/amr.505.253.
Texto completoChen, Xiaowen. "Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips". Journal of Software 10, n.º 2 (febrero de 2015): 142–61. http://dx.doi.org/10.17706/jsw.10.2.142-161.
Texto completoMaity, Arka, Anuj Pathania y Tulika Mitra. "PkMin: Peak Power Minimization for Multi-Threaded Many-Core Applications". Journal of Low Power Electronics and Applications 10, n.º 4 (30 de septiembre de 2020): 31. http://dx.doi.org/10.3390/jlpea10040031.
Texto completoGriffin, Thomas A. N., Kenneth Shankland, Jacco van de Streek y Jason Cole. "MDASH: a multi-core-enabled program for structure solution from powder diffraction data". Journal of Applied Crystallography 42, n.º 2 (5 de marzo de 2009): 360–61. http://dx.doi.org/10.1107/s0021889809006852.
Texto completoChen, Gang, Kai Huang, Long Cheng, Biao Hu y Alois Knoll. "Dynamic Partitioned Cache Memory for Real-Time MPSoCs with Mixed Criticality". Journal of Circuits, Systems and Computers 25, n.º 06 (31 de marzo de 2016): 1650062. http://dx.doi.org/10.1142/s0218126616500626.
Texto completoSuleman, M. Aater, Onur Mutlu, Moinuddin K. Qureshi y Yale N. Patt. "Accelerating critical section execution with asymmetric multi-core architectures". ACM SIGARCH Computer Architecture News 37, n.º 1 (marzo de 2009): 253–64. http://dx.doi.org/10.1145/2528521.1508274.
Texto completoChen, Kuan-Chung y Chung-Ho Chen. "Enabling SIMT Execution Model on Homogeneous Multi-Core System". ACM Transactions on Architecture and Code Optimization 15, n.º 1 (2 de abril de 2018): 1–26. http://dx.doi.org/10.1145/3177960.
Texto completoKulkarni, Abhishek, Latchesar Ionkov, Michael Lang y Andrew Lumsdaine. "Optimizing process creation and execution on multi-core architectures". International Journal of High Performance Computing Applications 27, n.º 2 (2 de abril de 2013): 147–61. http://dx.doi.org/10.1177/1094342013481483.
Texto completoSuleman, M. Aater, Onur Mutlu, Moinuddin K. Qureshi y Yale N. Patt. "Accelerating critical section execution with asymmetric multi-core architectures". ACM SIGPLAN Notices 44, n.º 3 (28 de febrero de 2009): 253–64. http://dx.doi.org/10.1145/1508284.1508274.
Texto completoHuang, Shujuan, Yi'an Zhu, Bailin Liu y Feng Xiao. "Research on Three Dimensional Scheduling Model for Embedded Multi-Core System". Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 36, n.º 5 (octubre de 2018): 1020–25. http://dx.doi.org/10.1051/jnwpu/20183651020.
Texto completoSaidi, Salah Eddine, Nicolas Pernet y Yves Sorel. "A method for parallel scheduling of multi-rate co-simulation on multi-core platforms". Oil & Gas Science and Technology – Revue d’IFP Energies nouvelles 74 (2019): 49. http://dx.doi.org/10.2516/ogst/2019009.
Texto completoMikami, Hiro, Kei Torigoe, Makoto Inokawa y Masato Edahiro. "LLVM Instruction Latency Measurement for Software-Hardware Interface for Multi-many-core". INTERNATIONAL JOURNAL OF COMPUTERS & TECHNOLOGY 22 (27 de mayo de 2022): 50–63. http://dx.doi.org/10.24297/ijct.v22i.9231.
Texto completoRebaya, Asma, Karol Desnos y Salem Hasnaoui. "Translating Hierarchical Simulink Applications to Real-time multi-core Execution". Universal Journal of Electrical and Electronic Engineering 7, n.º 4 (agosto de 2020): 242–61. http://dx.doi.org/10.13189/ujeee.2020.070403.
Texto completoJena, Swagat Kumar, Satyabrata Das y Satya Prakash Sahoo. "Design and Development of a Parallel Lexical Analyzer for C Language". International Journal of Knowledge-Based Organizations 8, n.º 1 (enero de 2018): 68–82. http://dx.doi.org/10.4018/ijkbo.2018010105.
Texto completoRinku, Dhruva R. y M. AshaRani. "Reinforcement learning based multi core scheduling (RLBMCS) for real time systems". International Journal of Electrical and Computer Engineering (IJECE) 10, n.º 2 (1 de abril de 2020): 1805. http://dx.doi.org/10.11591/ijece.v10i2.pp1805-1813.
Texto completoLiu, Cong, Wen Wang y Zhi Ying Wang. "Speculative High Performance Computation on Heterogeneous Multi-Core". Advanced Materials Research 1049-1050 (octubre de 2014): 2126–30. http://dx.doi.org/10.4028/www.scientific.net/amr.1049-1050.2126.
Texto completoUddin, Irfan. "One-IPC high-level simulation of microthreaded many-core architectures". International Journal of High Performance Computing Applications 31, n.º 2 (28 de julio de 2016): 152–62. http://dx.doi.org/10.1177/1094342015584495.
Texto completoKarasik, O. N. y A. A. Prihozhy. "ADVANCED SCHEDULER FOR COOPERATIVE EXECUTION OF THREADS ON MULTI-CORE SYSTEM". «System analysis and applied information science», n.º 1 (4 de mayo de 2017): 4–11. http://dx.doi.org/10.21122/2309-4923-2017-1-4-11.
Texto completoSoliman, Mostafa I. "Exploiting ILP, TLP, and DLP to Improve Multi-Core Performance of One-Sided Jacobi SVD". Parallel Processing Letters 19, n.º 02 (junio de 2009): 355–75. http://dx.doi.org/10.1142/s0129626409000262.
Texto completoHU, WEI, TIANZHOU CHEN, QINGSONG SHI y SHA LIU. "CRITICAL-PATH DRIVEN ROUTERS FOR ON-CHIP NETWORKS". Journal of Circuits, Systems and Computers 19, n.º 07 (noviembre de 2010): 1543–57. http://dx.doi.org/10.1142/s021812661000689x.
Texto completoKaiser, Benjamin, Matthias Keinert, Armin Lechler y Alexander Verl. "CNC Tool Path Generation on Multi-Core Processors". Applied Mechanics and Materials 794 (octubre de 2015): 339–46. http://dx.doi.org/10.4028/www.scientific.net/amm.794.339.
Texto completoOuyang, Xiangzhen y Yian Zhu. "Core-aware combining: Accelerating critical section execution on heterogeneous multi-core systems via combining synchronization". Journal of Parallel and Distributed Computing 162 (abril de 2022): 27–43. http://dx.doi.org/10.1016/j.jpdc.2022.01.001.
Texto completoChu, Edward Tsung Hsien y Ming Ru Tsai. "Using Multi-Core to Debug Interactive Applications". Applied Mechanics and Materials 764-765 (mayo de 2015): 1007–11. http://dx.doi.org/10.4028/www.scientific.net/amm.764-765.1007.
Texto completoZhang, Lei, Ren Ping Dong y Ya Ping Yu. "Realization of SMS4 Algorithm Based on Share Memory of the Heterogeneous Multi-Core Password Chip System". Applied Mechanics and Materials 668-669 (octubre de 2014): 1368–73. http://dx.doi.org/10.4028/www.scientific.net/amm.668-669.1368.
Texto completoIman Fitri Ismail, Akmal Nizam Mohammed, Bambang Basuno, Siti Aisyah Alimuddin y Mustafa Alas. "Evaluation of CFD Computing Performance on Multi-Core Processors for Flow Simulations". Journal of Advanced Research in Applied Sciences and Engineering Technology 28, n.º 1 (11 de septiembre de 2022): 67–80. http://dx.doi.org/10.37934/araset.28.1.6780.
Texto completoSANTOS COSTA, VíTOR, INÊS DUTRA y RICARDO ROCHA. "Threads and or-parallelism unified". Theory and Practice of Logic Programming 10, n.º 4-6 (julio de 2010): 417–32. http://dx.doi.org/10.1017/s1471068410000190.
Texto completoAbdulRazzaq, Atheer Akram, Qusay Shihab Hamad y Ahmed Majid Taha. "Parallel implementation of maximum-shift algorithm using OpenMp". Indonesian Journal of Electrical Engineering and Computer Science 22, n.º 3 (1 de junio de 2021): 1529. http://dx.doi.org/10.11591/ijeecs.v22.i3.pp1529-1539.
Texto completoQiu, Yue y Jing Feng Zang. "Based on Improved Genetic Algorithm for Task Scheduling of Heterogeneous Multi-Core Processor". Advanced Materials Research 1030-1032 (septiembre de 2014): 1671–75. http://dx.doi.org/10.4028/www.scientific.net/amr.1030-1032.1671.
Texto completoMaghsoudloo, Mohammad y Hamid Zarandi. "Parallel execution tracing: An alternative solution to exploit under-utilized resources in multi-core architectures for control-flow checking". Facta universitatis - series: Electronics and Energetics 29, n.º 2 (2016): 243–60. http://dx.doi.org/10.2298/fuee1602243m.
Texto completoT R, Vinay y Ajeet A. Chikkamannur. "A Machine Learning Technique for Abstraction of Modules in Legacy System and Assigning them on Multicore Machines Using and Controlling p-threads". International Journal on Recent and Innovation Trends in Computing and Communication 10, n.º 12 (31 de diciembre de 2022): 21–25. http://dx.doi.org/10.17762/ijritcc.v10i12.5837.
Texto completoAlonso, Pedro, Manuel F. Dolz, Rafael Mayo y Enrique S. Quintana-Ortí. "Energy-efficient execution of dense linear algebra algorithms on multi-core processors". Cluster Computing 16, n.º 3 (12 de mayo de 2012): 497–509. http://dx.doi.org/10.1007/s10586-012-0215-x.
Texto completoRajalakshmi, N. R., Ankur Dumka, Manoj Kumar, Rajesh Singh, Anita Gehlot, Shaik Vaseem Akram, Divya Anand, Dalia H. Elkamchouchi y Irene Delgado Noya. "A Cost-Optimized Data Parallel Task Scheduling with Deadline Constraints in Cloud". Electronics 11, n.º 13 (28 de junio de 2022): 2022. http://dx.doi.org/10.3390/electronics11132022.
Texto completoDURAN, ALEJANDRO, EDUARD AYGUADÉ, ROSA M. BADIA, JESÚS LABARTA, LUIS MARTINELL, XAVIER MARTORELL y JUDIT PLANAS. "OmpSs: A PROPOSAL FOR PROGRAMMING HETEROGENEOUS MULTI-CORE ARCHITECTURES". Parallel Processing Letters 21, n.º 02 (junio de 2011): 173–93. http://dx.doi.org/10.1142/s0129626411000151.
Texto completoSørensen, Peter y Jan Madsen. "Generating Process Network Communication Infrastructure for Custom Multi-Core Platforms". International Journal of Embedded and Real-Time Communication Systems 1, n.º 1 (enero de 2010): 37–63. http://dx.doi.org/10.4018/jertcs.2010103003.
Texto completoNozal, Raúl y Jose Luis Bosque. "Straightforward Heterogeneous Computing with the oneAPI Coexecutor Runtime". Electronics 10, n.º 19 (29 de septiembre de 2021): 2386. http://dx.doi.org/10.3390/electronics10192386.
Texto completoBielecki, Włodzimierz, Piotr Błaszyński y Marek Pałkowski. "3D Tiled Code Generation for Nussinov’s Algorithm". Applied Sciences 12, n.º 12 (9 de junio de 2022): 5898. http://dx.doi.org/10.3390/app12125898.
Texto completoR, Maheswari, Pattabiraman V y Sharmila P. "RECONFIGURABLE FPGA BASED SOFT-CORE PROCESSOR FOR SIMD APPLICATIONS". Asian Journal of Pharmaceutical and Clinical Research 10, n.º 13 (1 de abril de 2017): 180. http://dx.doi.org/10.22159/ajpcr.2017.v10s1.19632.
Texto completoUDDIN, M. IRFAN, MICHIEL W. VAN TOL y CHRIS R. JESSHOPE. "HIGH LEVEL SIMULATION OF SVP MANY-CORE SYSTEMS". Parallel Processing Letters 21, n.º 04 (diciembre de 2011): 413–38. http://dx.doi.org/10.1142/s0129626411000308.
Texto completoDümmler, Jörg, Thomas Rauber y Gudula Rünger. "Combined Scheduling and Mapping for Scalable Computing with Parallel Tasks". Scientific Programming 20, n.º 1 (2012): 45–67. http://dx.doi.org/10.1155/2012/514940.
Texto completoWeisz, Sergiu y Marta Bertran Ferrer. "Adding multi-core support to the ALICE Grid Middleware". Journal of Physics: Conference Series 2438, n.º 1 (1 de febrero de 2023): 012009. http://dx.doi.org/10.1088/1742-6596/2438/1/012009.
Texto completoZhai, Wenzheng, Yue-Li Hu y Feng Ran. "CQPSO scheduling algorithm for heterogeneous multi-core DAG task model". Modern Physics Letters B 31, n.º 19-21 (27 de julio de 2017): 1740050. http://dx.doi.org/10.1142/s0217984917400504.
Texto completoZhang, Jikai, Haidong Lan, Yuandong Chan, Yuan Shang, Bertil Schmidt y Weiguo Liu. "BGSA: a bit-parallel global sequence alignment toolkit for multi-core and many-core architectures". Bioinformatics 35, n.º 13 (16 de noviembre de 2018): 2306–8. http://dx.doi.org/10.1093/bioinformatics/bty930.
Texto completoHuang, Kai, Ming Jing, Xiaowen Jiang, Siheng Chen, Xiaobo Li, Wei Tao, Dongliang Xiong y Zhili Liu. "Task-Level Aware Scheduling of Energy-Constrained Applications on Heterogeneous Multi-Core System". Electronics 9, n.º 12 (5 de diciembre de 2020): 2077. http://dx.doi.org/10.3390/electronics9122077.
Texto completoVivanco, José María, Matthias Keinert, Armin Lechler y Alexander Verl. "Analysis and Design of Computerized Numerical Controls for Execution on Multi-core Systems". Procedia CIRP 41 (2016): 864–69. http://dx.doi.org/10.1016/j.procir.2015.12.021.
Texto completoMuresano, Ronal, Hugo Meyer, Dolores Rexachs y Emilio Luque. "An approach for an efficient execution of SPMD applications on Multi-core environments". Future Generation Computer Systems 66 (enero de 2017): 11–26. http://dx.doi.org/10.1016/j.future.2016.06.016.
Texto completoSesha Saiteja, Maddula N. V., K. Sai Sumanth Reddy, D. Radha y Minal Moharir. "Multi-Core Architecture and Network on Chip: Applications and Challenges". Journal of Computational and Theoretical Nanoscience 17, n.º 1 (1 de enero de 2020): 239–45. http://dx.doi.org/10.1166/jctn.2020.8657.
Texto completoChen, Kuo Yi, Fuh Gwo Chen y Jr Shian Chen. "A Cost-Effective Hardware Approach for Measuring Power Consumption of Modern Multi-Core Processors". Applied Mechanics and Materials 110-116 (octubre de 2011): 4569–73. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.4569.
Texto completoChen, Yong Heng, Wan Li Zuo y Feng Lin He. "Optimization Strategy of Bidirectional Join Enumeration in Multi-Core CPUS". Applied Mechanics and Materials 44-47 (diciembre de 2010): 383–87. http://dx.doi.org/10.4028/www.scientific.net/amm.44-47.383.
Texto completoPark, Sihyeong, Mi-Young Kwon, Hoon-Kyu Kim y Hyungshin Kim. "Execution Model to Reduce the Interference of Shared Memory in ARINC 653 Compliant Multicore RTOS". Applied Sciences 10, n.º 7 (3 de abril de 2020): 2464. http://dx.doi.org/10.3390/app10072464.
Texto completoSodinapalli, Nagendra Prasad, Subhash Kulkarni, Nawaz Ahmed Sharief y Prasanth Venkatareddy. "An efficient resource utilization technique for scheduling scientific workload in cloud computing environment". IAES International Journal of Artificial Intelligence (IJ-AI) 11, n.º 1 (1 de marzo de 2022): 367. http://dx.doi.org/10.11591/ijai.v11.i1.pp367-378.
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