Literatura académica sobre el tema "Multi-core execution"
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Artículos de revistas sobre el tema "Multi-core execution"
Fang, Juan y Hong Bo Zhang. "An Improved Architecture for Multi-Core Prefetching". Advanced Materials Research 505 (abril de 2012): 253–56. http://dx.doi.org/10.4028/www.scientific.net/amr.505.253.
Texto completoChen, Xiaowen. "Command-Triggered Microcode Execution for Distributed Shared Memory Based Multi-Core Network-on-Chips". Journal of Software 10, n.º 2 (febrero de 2015): 142–61. http://dx.doi.org/10.17706/jsw.10.2.142-161.
Texto completoMaity, Arka, Anuj Pathania y Tulika Mitra. "PkMin: Peak Power Minimization for Multi-Threaded Many-Core Applications". Journal of Low Power Electronics and Applications 10, n.º 4 (30 de septiembre de 2020): 31. http://dx.doi.org/10.3390/jlpea10040031.
Texto completoGriffin, Thomas A. N., Kenneth Shankland, Jacco van de Streek y Jason Cole. "MDASH: a multi-core-enabled program for structure solution from powder diffraction data". Journal of Applied Crystallography 42, n.º 2 (5 de marzo de 2009): 360–61. http://dx.doi.org/10.1107/s0021889809006852.
Texto completoChen, Gang, Kai Huang, Long Cheng, Biao Hu y Alois Knoll. "Dynamic Partitioned Cache Memory for Real-Time MPSoCs with Mixed Criticality". Journal of Circuits, Systems and Computers 25, n.º 06 (31 de marzo de 2016): 1650062. http://dx.doi.org/10.1142/s0218126616500626.
Texto completoSuleman, M. Aater, Onur Mutlu, Moinuddin K. Qureshi y Yale N. Patt. "Accelerating critical section execution with asymmetric multi-core architectures". ACM SIGARCH Computer Architecture News 37, n.º 1 (marzo de 2009): 253–64. http://dx.doi.org/10.1145/2528521.1508274.
Texto completoChen, Kuan-Chung y Chung-Ho Chen. "Enabling SIMT Execution Model on Homogeneous Multi-Core System". ACM Transactions on Architecture and Code Optimization 15, n.º 1 (2 de abril de 2018): 1–26. http://dx.doi.org/10.1145/3177960.
Texto completoKulkarni, Abhishek, Latchesar Ionkov, Michael Lang y Andrew Lumsdaine. "Optimizing process creation and execution on multi-core architectures". International Journal of High Performance Computing Applications 27, n.º 2 (2 de abril de 2013): 147–61. http://dx.doi.org/10.1177/1094342013481483.
Texto completoSuleman, M. Aater, Onur Mutlu, Moinuddin K. Qureshi y Yale N. Patt. "Accelerating critical section execution with asymmetric multi-core architectures". ACM SIGPLAN Notices 44, n.º 3 (28 de febrero de 2009): 253–64. http://dx.doi.org/10.1145/1508284.1508274.
Texto completoHuang, Shujuan, Yi'an Zhu, Bailin Liu y Feng Xiao. "Research on Three Dimensional Scheduling Model for Embedded Multi-Core System". Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 36, n.º 5 (octubre de 2018): 1020–25. http://dx.doi.org/10.1051/jnwpu/20183651020.
Texto completoTesis sobre el tema "Multi-core execution"
Faleiro, Jose Manuel. "High Performance Multi-core Transaction Processing via Deterministic Execution". Thesis, Yale University, 2019. http://pqdtopen.proquest.com/#viewpdf?dispub=13851858.
Texto completoThe increasing democratization of server hardware with multi-core CPUs and large main memories has been one of the dominant hardware trends of the last decade. "Bare metal" servers with tens of CPU cores and over 100 gigabytes of main memory have been available for several years now. Recently, this large scale hardware has also been available via the cloud; for instance, Amazon EC2 now provides instances with 64 physical CPU cores. Database systems, with their roots in uniprocessors and paucity of main memory, have unsurprisingly been found wanting on modern hardware.
In addition to changes in hardware, database systems have had to contend with changing application requirements and deployment environments. Database systems have long provided applications with an interactive interface, in which an application can communicate with the database over several round-trips in the course of a single request. A large class of applications, however, does not require interactive interfaces, and is unwilling to pay the performance cost associated with overly flexible interfaces. Some of these applications have eschewed database systems altogether in favor of high-performance key-value stores.
Finally, modern applications are increasingly deployed at ever increasing scales, often serving hundreds of thousands to millions of simultaneous clients. These large scale deployments are more prone to errors due to consistency issues in their underlying database systems. Ever since their inception, database systems have provided applications to tradeoff consistency for performance, and often nudge applications towards weak consistency. When deployed at scale, weak consistency exposes latent consistency-related bugs, in the same way that failures are more likely to occur at scale. Nearly every widely deployed database system provides applications with weak consistency consistency by default, and its widespread use in practice significantly complicates application development, leading to latent Heisenbugs that are only exposed in production.
This dissertation proposes and explores the use of deterministic execution to address these concerns. Database systems have traditionally been non-deterministic; given an input list of transactions, the final state of the database, which corresponds to some totally ordered execution of transactions, is dependent on non-deterministic factors such as thread scheduling decisions made by the operating system and failures. Deterministic execution, on the other hand, ensures that the database's final state is always determined by its input list of transactions; in other words, the input list of transactions is the same as the total order of transactions that determines the database's state.
While non-deterministic database systems expend significant resources in determining valid total orders of transactions, we show that deterministic systems can exploit simple and low-cost up-front total ordering of transactions to execute and schedule transactions much more efficiently. We show that deterministic execution enables low-overhead, highly-parallel scheduling mechanisms, that can address the performance limitations of existing database systems on modern hardware. Deterministic database systems are designed based on the assumption that applications can submit their transactions in one-shot prepared transactions, instead of multiple round-trips. Finally, we attempt to understand the fundamental reason for the observed performance differences between various consistency levels in database systems, and based on this understanding, show that we can exploit deterministic execution to provide strong consistency at a cost that is competitive with that offered by weak consistency levels.
Grosic, Hasan y Emir Hasanovic. "Optimizing Inter-core Data-propagation Delays in Multi-core Embedded Systems". Thesis, Mälardalens högskola, Akademin för innovation, design och teknik, 2019. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-44770.
Texto completoLi, Pei. "Unified system of code transformation and execution for heterogeneous multi-core architectures". Thesis, Bordeaux, 2015. http://www.theses.fr/2015BORD0441/document.
Texto completoHeterogeneous architectures have been widely used in the domain of high performance computing. However developing applications on heterogeneous architectures is time consuming and error-prone because going from a single accelerator to multiple ones indeed requires to deal with potentially non-uniform domain decomposition, inter-accelerator data movements, and dynamic load balancing. The aim of this thesis is to propose a solution of parallel programming for novice developers, to ease the complex coding process and guarantee the quality of code. We lighted and analysed the shortcomings of existing solutions and proposed a new programming tool called STEPOCL along with a new domain specific language designed to simplify the development of an application for heterogeneous architectures. We evaluated both the performance and the usefulness of STEPOCL. The result show that: (i) the performance of an application written with STEPOCL scales linearly with the number of accelerators, (ii) the performance of an application written using STEPOCL competes with an handwritten version, (iii) larger workloads run on multiple devices that do not fit in the memory of a single device, (iv) thanks to STEPOCL, the number of lines of code required to write an application for multiple accelerators is roughly divided by ten
Gustavsson, Andreas. "Static Execution Time Analysis of Parallel Systems". Doctoral thesis, Mälardalens högskola, Inbyggda system, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-31399.
Texto completoDen strategi som historiskt sett använts för att öka processorers prestanda (genom ökad klockfrekvens och ökad instruktionsnivåparallellism) är inte längre hållbar på grund av den ökade energikonsumtion som krävs. Därför är den nuvarande trenden inom processordesign att låta mjukvaran påverka det parallella exekveringsbeteendet. Detta görs vanligtvis genom att placera multipla processorkärnor på ett och samma processorchip. Kärnorna delar vanligtvis på några av processorchipets resurser, såsom cache-minne (och därmed också det nätverk, till exempel en buss, som ansluter kärnorna till detta minne, samt alla minnen på högre nivåer). För att utnyttja all den prestanda som denna typ av processorer erbjuder så måste mjukvaran som körs på dem kunna delas upp över de tillgängliga kärnorna. Eftersom flerkärniga processorer är standard idag så måste även realtidssystem baseras på dessa och den nämnda typen av kod. Ett realtidssystem är ett datorsystem som måste vara både funktionellt och tidsmässigt korrekt. För vissa typer av realtidssystem kan ett inkorrekt tidsmässigt beteende ha katastrofala följder. Därför är det ytterst viktigt att metoder för att analysera och beräkna säkra gränser för det tidsmässiga beteendet hos parallella datorsystem tas fram. Denna avhandling presenterar en metod för att beräkna säkra gränser för exekveringstiden hos ett givet parallellt system, och visar därmed att sådana metoder existerar. Gränssnittet till metoden är ett litet formellt definierat trådat programmeringsspråk där trådarna tillåts kommunicera och synkronisera med varandra. Metoden baseras på abstrakt exekvering för att effektivt beräkna de säkra (men ofta överskattade) gränserna för exekveringstiden. Abstrakt exekvering baseras i sin tur på abstrakta interpreteringstekniker som vida används inom tidsanalys av sekventiella datorsystem. Avhandlingen bevisar även korrektheten hos den presenterade metoden (det vill säga att de beräknade gränserna för det analyserade systemets exekveringstid är säkra) och utvärderar en prototypimplementation av den.
Worst-Case Execution Time Analysis of Parallel Systems
RALF3 - Software for Embedded High Performance Architectures
Gustavsson, Andreas. "Static Timing Analysis of Parallel Systems Using Abstract Execution". Licentiate thesis, Mälardalens högskola, Inbyggda system, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:mdh:diva-26125.
Texto completoWorst-Case Execution Time Analysis of Parallel Systems
RALF3 - Software for Embedded High Performance Architectures
Nowotsch, Jan [Verfasser] y Theo [Akademischer Betreuer] Ungerer. "Interference-sensitive Worst-case Execution Time Analysis for Multi-core Processors / Jan Nowotsch. Betreuer: Theo Ungerer". Augsburg : Universität Augsburg, 2014. http://d-nb.info/1077704410/34.
Texto completoBin, Jingyi. "Controlling execution time variability using COTS for Safety-critical systems". Phd thesis, Université Paris Sud - Paris XI, 2014. http://tel.archives-ouvertes.fr/tel-01061936.
Texto completoKumar, Vijay Shiv. "Specification, Configuration and Execution of Data-intensive Scientific Applications". The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1286570224.
Texto completoHaas, Florian [Verfasser] y Theo [Akademischer Betreuer] Ungerer. "Fault-tolerant Execution of Parallel Applications on x86 Multi-core Processors with Hardware Transactional Memory / Florian Haas ; Betreuer: Theo Ungerer". Augsburg : Universität Augsburg, 2019. http://d-nb.info/1194312942/34.
Texto completoHaur, Imane. "AUTOSAR compliant multi-core RTOS formal modeling and verification". Electronic Thesis or Diss., Ecole centrale de Nantes, 2022. http://www.theses.fr/2022ECDN0057.
Texto completoFormal verification is a solution to increase the system’s implementation reliability. In our thesis work, we are interestedin using these methods to verify multi-core RTOS. We propose a model-checking approach using time Petri nets extended with colored transitions and high-level features. We use this formalism to model the Trampoline multi-core OS, compliant with the OSEK/VDX and AUTOSAR standards. We first define this formalism and show its suitability for modeling real-time concurrent systems. We then use this formalism to model the Trampoline multi-core RTOS and verify by model-checkingits conformity with the AUTOSAR standard. From this model, we can verify properties of both the OS and the application, such as the schedulability of a real-time system and the synchronization mechanisms: concurrent access to the data structures of the OS, multicore scheduling, and inter-core interrupt handling. As an illustration, this method allowed the automatic identification of two possible errors of the Trampoline OS in concurrent execution, showing insufficient data protection andfaulty synchronization
Capítulos de libros sobre el tema "Multi-core execution"
Muresano, Ronal, Dolores Rexachs y Emilio Luque. "An Approach for Efficient Execution of SPMD Applications on Multicore Clusters". En Programming multi-core and many-core computing systems, 431–50. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2017. http://dx.doi.org/10.1002/9781119332015.ch21.
Texto completoLee, Sungju, Heegon Kim y Yongwha Chung. "Power-Time Tradeoff of Parallel Execution on Multi-core Platforms". En Lecture Notes in Electrical Engineering, 157–63. Berlin, Heidelberg: Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-642-40675-1_25.
Texto completoHuang, Shiang, Jer-Min Jou, Cheng-Hung Hsieh y Ding-Yuan Lin. "Design of a Dynamic Parallel Execution Architecture for Multi-core Systems". En Advances in Intelligent Systems and Applications - Volume 2, 731–40. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-35473-1_72.
Texto completoGrass, Thomas, Alejandro Rico, Marc Casas, Miquel Moreto y Alex Ramirez. "Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors". En Lecture Notes in Computer Science, 218–29. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-14313-2_19.
Texto completoSeo, Dongyou, Myungsun Kim, Hyeonsang Eom y Heon Y. Yeom. "Bubble Task: A Dynamic Execution Throttling Method for Multi-core Resource Management". En Job Scheduling Strategies for Parallel Processing, 1–16. Cham: Springer International Publishing, 2015. http://dx.doi.org/10.1007/978-3-319-15789-4_1.
Texto completoSuraj, R., P. Chitra y S. Madumidha. "Evaluation of Worst-Case Execution Time of Tasks on Multi-core Processor". En Advances in Intelligent Systems and Computing, 441–48. New Delhi: Springer India, 2014. http://dx.doi.org/10.1007/978-81-322-2135-7_47.
Texto completoChang, Wen-Hsien, Jer-Min Jou, Cheng-Hung Hsieh y Ding-Yuan Lin. "A Distributed Run-Time Dynamic Data Manager for Multi-core System Parallel Execution". En Advances in Intelligent Systems and Applications - Volume 2, 741–50. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-35473-1_73.
Texto completoHaas, Florian, Sebastian Weis, Theo Ungerer, Gilles Pokam y Youfeng Wu. "Fault-Tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support". En Architecture of Computing Systems - ARCS 2017, 16–30. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-54999-6_2.
Texto completoPrabhakar, Raghu, R. Govindarajan y Matthew J. Thazhuthaveetil. "CUDA-For-Clusters: A System for Efficient Execution of CUDA Kernels on Multi-core Clusters". En Euro-Par 2012 Parallel Processing, 415–26. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-32820-6_42.
Texto completoLi, Ying, Jianwei Niu, Jiong Zhang, Mohammed Atiquzzaman y Xiang Long. "Real-Time Scheduling for Periodic Tasks in Homogeneous Multi-core System with Minimum Execution Time". En Collaborate Computing: Networking, Applications and Worksharing, 175–87. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-59288-6_16.
Texto completoActas de conferencias sobre el tema "Multi-core execution"
Yuan, Simon, Li Hsien Yoong y Partha S. Roop. "Compiling Esterel for Multi-core Execution". En 2011 14th Euromicro Conference on Digital System Design (DSD). IEEE, 2011. http://dx.doi.org/10.1109/dsd.2011.97.
Texto completoSgroi, Kevin J. y Scott E. Spetka. "Analysis of Multi-Threaded Code Execution on Small Multi-Core Architectures". En ASME 2010 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. ASMEDC, 2010. http://dx.doi.org/10.1115/detc2010-29135.
Texto completoInam, Rafia, Nesredin Mahmud, Moris Behnam, Thomas Nolte y Mikael Sjodin. "The Multi-Resource Server for predictable execution on multi-core platforms". En 2014 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS). IEEE, 2014. http://dx.doi.org/10.1109/rtas.2014.6925986.
Texto completoSuleman, M. Aater, Onur Mutlu, Moinuddin K. Qureshi y Yale N. Patt. "Accelerating critical section execution with asymmetric multi-core architectures". En Proceeding of the 14th international conference. New York, New York, USA: ACM Press, 2009. http://dx.doi.org/10.1145/1508244.1508274.
Texto completohayakawa, Kiyoshi y Ryusuke Yamano. "Multi-core FPGA Execution for Electromagnetic Simulation by FDTD". En 2015 2nd International Conference on Information Science and Control Engineering (ICISCE). IEEE, 2015. http://dx.doi.org/10.1109/icisce.2015.189.
Texto completoCamp, David, E. Wes Bethel y Hank Childs. "Transitioning Data Flow-Based Visualization Software to Multi-core Hybrid Parallelism". En 2013 Data-Flow Execution Models for Extreme Scale Computing (DFM). IEEE, 2013. http://dx.doi.org/10.1109/dfm.2013.12.
Texto completoSchuele, T. "Efficient parallel execution of streaming applications on multi-core processors". En 19th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2011). IEEE, 2011. http://dx.doi.org/10.1109/pdp.2011.48.
Texto completoDennis, Jack B. "On the Feasibility of a Codelet Based Multi-core Operating System". En 2014 Fourth Workshop on Data-Flow Execution Models for Extreme Scale Computing. IEEE, 2014. http://dx.doi.org/10.1109/dfm.2014.18.
Texto completoSalamat, Babak, Andreas Gal, Todd Jackson, Karthikeyan Manivannan, Gregor Wagner y Michael Franz. "Multi-variant Program Execution: Using Multi-core Systems to Defuse Buffer-Overflow Vulnerabilities". En 2008 International Conference on Complex, Intelligent and Software Intensive Systems. IEEE, 2008. http://dx.doi.org/10.1109/cisis.2008.136.
Texto completoHo, Nam, Andrea Mondelli, Alberto Scionti, Marco Solinas, Antoni Portero y Roberto Giorgi. "Enhancing an x86_64 multi-core architecture with data-flow execution support". En CF'15: Computing Frontiers Conference. New York, NY, USA: ACM, 2015. http://dx.doi.org/10.1145/2742854.2742896.
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